commit 0677219017e53b80296f3bbb926942d629905eb4
author Srikrishna Iyer <sriyer@google.com> Thu Mar 24 00:04:41 2022 -0700
committer Srikrishna Iyer <46467186+sriyerg@users.noreply.github.com> Thu Mar 24 15:48:18 2022 -0700
tree 12904890e82d5bbc73ecf2c6a6d8d4a67b467a7c
parent 3db7ca39807617662e1659be460a837dc5f041f2

[rv_dm dv] Test drive compile-time seed

This commit test-drives the compile-time randomization method by
introducing a pre-processor macro `BUILD_SEED` which is set to
the DVSim generated random seed value. This macro is added to
`common_sim_cfg.hjson`, which will apply to all simulators.

For RV_DM, the pre-processor macro `RV_DM_JTAG_IDCODE` is removed
and in the env package, the `RV_DM_JTAG_IDCODE` parameter is set
to the `BUILD_SEED` preprocessor macro instead. On successive
simulation runs, the IDCODE value in the design has shown to be
set to random values, demonstrating that this method is working.
The IDCODE value returns 1 when `--build-seed 1` is passed on
the command line.

Signed-off-by: Srikrishna Iyer <sriyer@google.com>

hw/dv/tools/dvsim/common_sim_cfg.hjson

diff --git a/hw/dv/tools/dvsim/common_sim_cfg.hjson b/hw/dv/tools/dvsim/common_sim_cfg.hjson
index 3e00794..ac65457 100644
--- a/hw/dv/tools/dvsim/common_sim_cfg.hjson
+++ b/hw/dv/tools/dvsim/common_sim_cfg.hjson
@@ -67,7 +67,13 @@
                "+define+UVM_REG_DATA_WIDTH={tl_dw}",
                "+define+UVM_REG_BYTENABLE_WIDTH={tl_dbw}",
                "+define+SIMULATION",
-               "+define+DUT_HIER={dut_instance}"]
+               "+define+DUT_HIER={dut_instance}",
+               // Introduce compile-time randomization. Use `BUILD_SEED in Verilog sources to set
+               // constants that have no side-effects, such as addition or deletion of logic. Useful
+               // to mutate fixed device values such as secret keys, identification constants, etc.
+               // across successive simulation runs. Note that this will always be a 32-bit unsigned
+               // value.
+               "+define+BUILD_SEED={seed}"]
 
   run_opts: ["+UVM_NO_RELNOTES",
              "+UVM_VERBOSITY={expand_uvm_verbosity_{verbosity}}"]

hw/ip/rv_dm/dv/env/rv_dm_env_pkg.sv

diff --git a/hw/ip/rv_dm/dv/env/rv_dm_env_pkg.sv b/hw/ip/rv_dm/dv/env/rv_dm_env_pkg.sv
index c8997f4..425ad67 100644
--- a/hw/ip/rv_dm/dv/env/rv_dm_env_pkg.sv
+++ b/hw/ip/rv_dm/dv/env/rv_dm_env_pkg.sv
@@ -27,14 +27,7 @@
 
   // parameters
   parameter uint NUM_HARTS = rv_dm_reg_pkg::NrHarts;
-
-`ifndef RV_DM_JTAG_IDCODE
-`define RV_DM_JTAG_IDCODE 32'h0000_0001 // Match the RTL default.
-`endif
-
-  parameter uint RV_DM_JTAG_IDCODE = `RV_DM_JTAG_IDCODE;
-
-`undef RV_DM_JTAG_IDCODE
+  parameter uint RV_DM_JTAG_IDCODE = `BUILD_SEED;
 
   // Design uses 5 bits for IR.
   parameter uint JTAG_IR_LEN = 5;

hw/ip/rv_dm/dv/rv_dm_sim_cfg.hjson

diff --git a/hw/ip/rv_dm/dv/rv_dm_sim_cfg.hjson b/hw/ip/rv_dm/dv/rv_dm_sim_cfg.hjson
index fff19ec..32e6e92 100644
--- a/hw/ip/rv_dm/dv/rv_dm_sim_cfg.hjson
+++ b/hw/ip/rv_dm/dv/rv_dm_sim_cfg.hjson
@@ -39,9 +39,6 @@
   // Default iterations for all tests - each test entry can override this.
   reseed: 50
 
-  // TODO: Set JTAG ID code value to a build-time random value.
-  build_opts: ["+define+RV_DM_JTAG_IDCODE=12345678"]
-
   overrides: [
     {
       // This sets the width of UVM data (UVM_REG_DATA_WIDTH) to sufficiently large value. RV_DM DV