| commit | 3db7ca39807617662e1659be460a837dc5f041f2 | [log] [tgz] |
|---|---|---|
| author | Srikrishna Iyer <sriyer@google.com> | Wed Mar 23 23:48:07 2022 -0700 |
| committer | Srikrishna Iyer <46467186+sriyerg@users.noreply.github.com> | Thu Mar 24 15:48:18 2022 -0700 |
| tree | 017becf344e396adcc0211ecf979ff8df356f579 | |
| parent | 4b186e06d80305601974c3625f040993f460ec1e [diff] |
[dvsim] Introduce Verilog compile-time seeds This commit adds a mechanism within DVSim to introduce a compile-time randomization of the design using a seed value that can be controlled via the command-line. Compile time randomization is achieved by setting a pre-processor macro with the seed value, and using the macro to mutate some constants in the design. This mechanism is particularly useful to change constants that do not have side effects in the design (such as addition of deletion of logic), but are merely used to indicate some fixed values in the design, such as a part of the secret keys. We do not have a clean mechanism to change these fixed values across successive compilations - this commit is one way to achieve that. Signed-off-by: Srikrishna Iyer <sriyer@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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