| # RISC-V Compliance Test RV32I Makefrag | |
| # | |
| # Copyright (c) 2017, Codasip Ltd. | |
| # All rights reserved. | |
| # | |
| # Redistribution and use in source and binary forms, with or without | |
| # modification, are permitted provided that the following conditions are met: | |
| # * Redistributions of source code must retain the above copyright | |
| # notice, this list of conditions and the following disclaimer. | |
| # * Redistributions in binary form must reproduce the above copyright | |
| # notice, this list of conditions and the following disclaimer in the | |
| # documentation and/or other materials provided with the distribution. | |
| # * Neither the name of the Codasip Ltd. nor the | |
| # names of its contributors may be used to endorse or promote products | |
| # derived from this software without specific prior written permission. | |
| # | |
| # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
| # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
| # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
| # PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY | |
| # DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
| # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
| # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
| # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
| # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| # | |
| # Description: Makefrag for RV32I compliance tests | |
| rv32i_sc_tests = \ | |
| I-ENDIANESS-01 \ | |
| I-RF_x0-01 \ | |
| I-RF_size-01 \ | |
| I-RF_width-01 \ | |
| I-DELAY_SLOTS-01 \ | |
| I-JAL-01 \ | |
| I-JALR-01 \ | |
| I-LUI-01 \ | |
| I-AUIPC-01 \ | |
| I-LW-01 \ | |
| I-LH-01 \ | |
| I-LHU-01 \ | |
| I-LB-01 \ | |
| I-LBU-01 \ | |
| I-SW-01 \ | |
| I-SH-01 \ | |
| I-SB-01 \ | |
| I-ADD-01 \ | |
| I-ADDI-01 \ | |
| I-AND-01 \ | |
| I-OR-01 \ | |
| I-ORI-01 \ | |
| I-XORI-01 \ | |
| I-XOR-01 \ | |
| I-SUB-01 \ | |
| I-ANDI-01 \ | |
| I-SLTI-01 \ | |
| I-SLTIU-01 \ | |
| I-BEQ-01 \ | |
| I-BNE-01 \ | |
| I-BLT-01 \ | |
| I-BLTU-01 \ | |
| I-BGE-01 \ | |
| I-BGEU-01 \ | |
| I-SRLI-01 \ | |
| I-SLLI-01 \ | |
| I-SRAI-01 \ | |
| I-SLL-01 \ | |
| I-SRL-01 \ | |
| I-SRA-01 \ | |
| I-SLT-01 \ | |
| I-SLTU-01 \ | |
| I-NOP-01 \ | |
| I-ECALL-01 \ | |
| I-EBREAK-01 \ | |
| I-IO-01 \ | |
| # These tests are broken due to flaws in riscv-compliance rather than | |
| # Ibex/OpenTitan (see https://github.com/lowRISC/ibex/issues/100) | |
| #I-MISALIGN_JMP-01 | |
| #I-MISALIGN_LDST-01 | |
| rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) | |
| target_tests += $(rv32i_tests) |