hw/ip/aon_timer/data/aon_timer.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
{
  name: "aon_timer",
  clock_primary: "clk_i",
  reset_primary: "rst_ni",
  other_clock_list: [
    "clk_aon_i"
  ],
  other_reset_list:
  [
    "rst_aon_ni"
  ],
  bus_device: "tlul",
  interrupt_list: [
    { name: "wkup_timer_expired",
      desc: "Raised if the wakeup timer has hit the specified threshold"
    },
    { name: "wdog_timer_bark",
      desc: "Raised if the watchdog timer has hit the bark threshold"
    },
  ],
  wakeup_list: [
    { name: "aon_timer_wkup_req",
      desc: "Raised if the wakeup or watchdog timer has hit the specified threshold"
    },
  ],
  reset_request_list: [
    { name: "aon_timer_rst_req",
      desc: "watchdog reset requestt"
    },
  ],
  inter_signal_list: [
    // wakeup and reset request signals
    { struct:  "logic",
      type:    "uni",
      name:    "aon_timer_wkup_req",
      act:     "req",
      package: "",
      default: "1'b0"
    },
    { struct:  "logic",
      type:    "uni",
      name:    "aon_timer_rst_req",
      act:     "req",
      package: "",
      default: "1'b0"
    },
    // Broadcast from LC
    { struct:  "lc_tx"
      type:    "uni"
      name:    "lc_cpu_en"
      act:     "rcv"
      default: "lc_ctrl_pkg::Off"
      package: "lc_ctrl_pkg"
    },
    { name:    "sleep_mode",
      type:    "uni",
      act:     "rcv",
      package: "",
      struct:  "logic",
      width:   "1"
    }
  ],
  no_auto_intr_regs: "true",
  regwidth: "32",
  registers: [
    { name: "WKUP_CTRL",
      desc: "Wakeup Timer Control register",
      swaccess: "rw",
      hwaccess: "hrw",
      hwext: "true",
      hwqe: "true",
      fields: [
        { bits: "0",
          name: "enable",
          desc: "When set to 1, the wakeup timer will count",
        }
        { bits: "12:1",
          name: "prescaler",
          desc: "Pre-scaler value for wakeup timer count",
        }
      ],
      tags: [// register implemented in clk_aon domain and does not update according to
             // normal timing
        "excl:CsrAllTests:CsrExclWriteCheck"],
    },
    { name: "WKUP_THOLD",
      desc: "Wakeup Timer Threshold Register",
      swaccess: "rw",
      hwaccess: "hrw",
      hwext: "true",
      hwqe: "true",
      fields: [
        { bits: "31:0",
          name: "threshold",
          desc: "The count at which a wakeup interrupt should be generated",
        }
      ],
      tags: [// register implemented in clk_aon domain and does not update according to
             // normal timing
        "excl:CsrAllTests:CsrExclWriteCheck"],
    },
    { name: "WKUP_COUNT",
      desc: "Wakeup Timer Count Register",
      swaccess: "rw",
      hwaccess: "hrw",
      hwext: "true",
      hwqe: "true",
      fields: [
        { bits: "31:0",
          name: "count",
          desc: "The current wakeup counter value",
        }
      ],
      tags: [// register implemented in clk_aon domain and does not update according to
             // normal timing
        "excl:CsrAllTests:CsrExclWriteCheck"],
    },
    { name: "WDOG_REGWEN",
      desc: "Watchdog Timer Write Enable Register",
      swaccess: "rw0c",
      hwaccess: "none",
      fields: [
        { bits: "0",
          name: "regwen",
          desc: "Once cleared, the watchdog configuration will be locked until the next reset",
          resval: 1
        }
      ]
    },
    { name: "WDOG_CTRL",
      desc: "Watchdog Timer Control register",
      swaccess: "rw",
      hwaccess: "hrw",
      hwext: "true",
      hwqe: "true",
      regwen: "WDOG_REGWEN",
      fields: [
        { bits: "0",
          name: "enable",
          desc: "When set to 1, the watchdog timer will count",
        },
        { bits: "1",
          name: "pause_in_sleep",
          desc: "When set to 1, the watchdog timer will not count during sleep",
        }
      ],
      tags: [// register implemented in clk_aon domain and does not update according to
             // normal timing
        "excl:CsrAllTests:CsrExclWriteCheck"],
    },
    { name: "WDOG_BARK_THOLD",
      desc: "Watchdog Timer Bark Threshold Register",
      swaccess: "rw",
      hwaccess: "hrw",
      hwext: "true",
      hwqe: "true",
      regwen: "WDOG_REGWEN",
      fields: [
        { bits: "31:0",
          name: "threshold",
          desc: "The count at which a watchdog bark interrupt should be generated",
        }
      ],
      tags: [// register implemented in clk_aon domain and does not update according to
             // normal timing
        "excl:CsrAllTests:CsrExclWriteCheck"],
    },
    { name: "WDOG_BITE_THOLD",
      desc: "Watchdog Timer Bite Threshold Register",
      swaccess: "rw",
      hwaccess: "hrw",
      hwext: "true",
      hwqe: "true",
      regwen: "WDOG_REGWEN",
      fields: [
        { bits: "31:0",
          name: "threshold",
          desc: "The count at which a watchdog bite reset should be generated",
        }
      ],
      tags: [// register implemented in clk_aon domain and does not update according to
             // normal timing
        "excl:CsrAllTests:CsrExclWriteCheck"],
    },
    { name: "WDOG_COUNT",
      desc: "Watchdog Timer Count Register",
      swaccess: "rw",
      hwaccess: "hrw",
      hwext: "true",
      hwqe: "true",
      fields: [
        { bits: "31:0",
          name: "count",
          desc: "The current watchdog counter value",
        }
      ],
      tags: [// register implemented in clk_aon domain and does not update according to
             // normal timing
        "excl:CsrAllTests:CsrExclWriteCheck"],
    },
    { name: "INTR_STATE",
      desc: "Interrupt State Register",
      swaccess: "rw1c",
      hwaccess: "hrw",
      fields: [
        { bits: "0",
          name: "wkup_timer_expired",
          desc: "Raised if the wakeup timer has hit the specified threshold",
        }
        { bits: "1",
          name: "wdog_timer_expired",
          desc: "Raised if the watchdog timer has hit the bark threshold",
        }
      ]
      tags: [// interrupt could be updated by HW
        "excl:CsrNonInitTests:CsrExclWriteCheck"],
    },
    { name: "INTR_ENABLE",
      desc: "Dummy interrupt enable register.  This is only here because of #5260.  DO NOT USE",
      swaccess: "rw",
      hwaccess: "hwo",
      hwqe: "true",
      hwext: "true",
      fields: [
        { bits: "0",
          name: "wkup_timer_expired",
          desc: "Raised if the wakeup timer has hit the specified threshold",
        }
        { bits: "1",
          name: "wdog_timer_expired",
          desc: "Raised if the watchdog timer has hit the bark threshold",
        }
      ],
      tags: [// dummy register due to #5260, don't bother checking
        "excl:CsrAllTests:CsrExclAll"],
    },
    { name: "INTR_TEST",
      desc: "Interrupt Test Register",
      swaccess: "wo",
      hwaccess: "hro",
      hwext: "true",
      hwqe: "true",
      fields: [
        { bits: "0",
          name: "wkup_timer_expired",
          desc: "Write 1 to force wkup_timer_expired interrupt",
        }
        { bits: "1",
          name: "wdog_timer_expired",
          desc: "Write 1 to force wdog_timer_expired (watchdog bark) interrupt",
        }
      ]
    },
    { name: "WKUP_CAUSE",
      desc: "Wakeup request status",
      swaccess: "rw0c",
      hwaccess: "hrw",
      hwext: "true",
      hwqe: "true",
      fields: [
        { bits: "0",
          name: "cause",
          desc: "AON timer requested wakeup, write 0 to clear",
        }
      ]
      tags: [// this could be updated by HW
        "excl:CsrNonInitTests:CsrExclWriteCheck"],
    },
  ],
}