| commit | 9d273c440c27609bf7ccd66b35d2ed93b7ea0b55 | [log] [tgz] |
|---|---|---|
| author | Eunchan Kim <eunchan@opentitan.org> | Tue May 17 13:59:03 2022 -0700 |
| committer | Eli Kim <github@elikim.dev> | Tue May 17 18:14:10 2022 -0700 |
| tree | e6ecb016c478c7963b0fcc44bb9df5e5cd2a57ac | |
| parent | 787367be6448566c4948424c5d23a8ad2d0c9eae [diff] |
fix(spi_device): Re-timing sck_cmdfifo_set clear time Related issue #11871 In previous design, the `sck_cmdfifo_set` signal is set by the ACK of CMDFIFO write port and cleared by the FIFO DEPTH == 0. THe clearing of FIFO depth depends on the SW processing time. This commit revises it to CSb assertion pulse signal. It is still bounded by the clock ratio between the SYS_CLK and the SCK. SYS_CLK should not be 3 times slower than the SCK to correctly generate the pulse signal within the opcode timeline. Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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