fix(spi_device): Missed Command Upload

This commit fixes one of the issue #11871

Problem:

    SW read incorrect opcode for Page Program.

Analysis
--------

The Page Program (0x02) opcode is adjacent to other commands that
SPI_DEVICE processes. So, the Datapath is fixed when the exact last beat
of the command opcode arrives. It is the second half of the 7th SCK.

The command parser activates Upload module at that time. However, the
top module switches the SRAM mux to the Upload module when the datapath
is latched by inverted SCK, which is right after the 8th posedge of SCK.

The Upload module, however, pushes the CMDFIFO entry (0x02 Page Program)
prior to 8th posedge of SCK to safely update the FIFO content as SCK
may not have 9th posedge if the SPI command is opcode only commands.
Examples are CHIP ERASE (0xC7), SECTOR ERASE, etc.

Resolution
----------

This commit revises the Mux design. Rather than using
`cmd_dp_sel_outclk`, it uses `cmd_dp_sel` (SCK clock) directly for the
SRAM mux. Other signals must be in inverted SCK clock domain to match
the output data phase.

Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
1 file changed
tree: 722a3cb3b2d9ac9c21216a5654651b797ce29aa7
  1. .github/
  2. ci/
  3. doc/
  4. hw/
  5. rules/
  6. site/
  7. sw/
  8. test/
  9. third_party/
  10. util/
  11. .bazelignore
  12. .bazelrc
  13. .bazelversion
  14. .clang-format
  15. .dockerignore
  16. .flake8
  17. .gitignore
  18. .style.yapf
  19. .svlint.toml
  20. .svls.toml
  21. _index.md
  22. apt-requirements.txt
  23. azure-pipelines.yml
  24. bazelisk.sh
  25. BUILD.bazel
  26. check_tool_requirements.core
  27. CLA
  28. COMMITTERS
  29. CONTRIBUTING.md
  30. LICENSE
  31. meson-config.txt
  32. meson.build
  33. meson_init.sh
  34. meson_options.txt
  35. python-requirements.txt
  36. README.md
  37. tool_requirements.py
  38. topgen-reg-only.core
  39. topgen.core
  40. WORKSPACE
  41. yum-requirements.txt
README.md

OpenTitan

OpenTitan logo

About the project

OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.

About this repository

This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.

Documentation

The project contains comprehensive documentation of all IPs and tools. You can access it online at docs.opentitan.org.

How to contribute

Have a look at [CONTRIBUTING]({{< relref “CONTRIBUTING.md” >}}) and our documentation on project organization and processes for guidelines on how to contribute code to this repository.

Licensing

Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).