blob: ed2b085063e2a5bda3345a762c9a30898595d80f [file] [log] [blame]
#include <riscv_vector.h>
#include <springbok.h>
#include <stdio.h>
#include <stdlib.h>
#include <bit>
#include <tuple>
#include "pw_unit_test/framework.h"
#include "test_v_helpers.h"
namespace vadd_vi_test {
namespace {
using namespace test_v_helpers;
uint8_t test_vector_1[MAXVL_BYTES];
uint8_t test_vector_2[MAXVL_BYTES];
class VaddViTest : public ::testing::Test {
protected:
void SetUp() override { zero_vector_registers(); }
void TearDown() override { zero_vector_registers(); }
};
TEST_F(VaddViTest, vadd_vi_demo) {
for (int i = 0; i < AVL_COUNT; i++) {
int32_t avl = AVLS[i];
int vlmax;
int vl;
std::tie(vlmax, vl) = vector_test_setup<uint8_t>(
VLMUL::LMUL_M1, avl, test_vector_1, test_vector_2);
if (avl > vlmax) {
continue;
}
int8_t *ptr_vec_1 = reinterpret_cast<int8_t *>(test_vector_1);
int8_t *ptr_vec_2 = reinterpret_cast<int8_t *>(test_vector_2);
const int8_t test_val_1 = 1;
const int8_t test_val_2 = -3;
__asm__ volatile("vadd.vi v8, v8, %[SIMM5]" ::[SIMM5] "n"(test_val_1));
__asm__ volatile("vadd.vi v8, v8, %[SIMM5]" ::[SIMM5] "n"(test_val_2));
for (int i = 0; i < vl; i++) {
ptr_vec_1[i] = test_val_1 + test_val_2;
}
__asm__ volatile("vse8.v v8, (%0)" : : "r"(ptr_vec_2));
assert_vec_elem_eq<int8_t>(vlmax, test_vector_1, test_vector_2);
}
}
#define DEFINE_TEST_VADD_VI(_SEW_, _LMUL_, TEST_VAL_1, TEST_VAL_2) \
TEST_F(VaddViTest, vadd_vi##_SEW_##m##_LMUL_) { \
for (int i = 0; i < AVL_COUNT; i++) { \
int32_t avl = AVLS[i]; \
int vlmax; \
int vl; \
std::tie(vlmax, vl) = vector_test_setup<int##_SEW_##_t>( \
VLMUL::LMUL_M##_LMUL_, avl, test_vector_1, test_vector_2); \
if (avl > vlmax) { \
continue; \
} \
int##_SEW_##_t *ptr_vec_1 = \
reinterpret_cast<int##_SEW_##_t *>(test_vector_1); \
int##_SEW_##_t *ptr_vec_2 = \
reinterpret_cast<int##_SEW_##_t *>(test_vector_2); \
const int##_SEW_##_t test_val_1 = TEST_VAL_1; \
const int##_SEW_##_t test_val_2 = TEST_VAL_2; \
__asm__ volatile("vadd.vi v8, v8, %[SIMM5]" ::[SIMM5] "n"(test_val_1)); \
__asm__ volatile("vadd.vi v8, v8, %[SIMM5]" ::[SIMM5] "n"(test_val_2)); \
for (int i = 0; i < vl; i++) { \
ptr_vec_1[i] = test_val_1 + test_val_2; \
} \
__asm__ volatile("vse" #_SEW_ ".v v8, (%0)" : : "r"(ptr_vec_2)); \
assert_vec_elem_eq<int##_SEW_##_t>(vlmax, test_vector_1, test_vector_2); \
} \
}
// TODO(gkielian): modify macro to permit more than one test per sew/lmul pair
DEFINE_TEST_VADD_VI(8, 1, -16, 15)
DEFINE_TEST_VADD_VI(8, 2, -2, 3)
DEFINE_TEST_VADD_VI(8, 4, 15, 15)
DEFINE_TEST_VADD_VI(8, 8, -15, -15)
DEFINE_TEST_VADD_VI(16, 1, -16, 15)
DEFINE_TEST_VADD_VI(16, 2, -2, 3)
DEFINE_TEST_VADD_VI(16, 4, 15, 15)
DEFINE_TEST_VADD_VI(16, 8, -15, -15)
DEFINE_TEST_VADD_VI(32, 1, -16, 15)
DEFINE_TEST_VADD_VI(32, 2, -2, 3)
DEFINE_TEST_VADD_VI(32, 4, 15, 15)
DEFINE_TEST_VADD_VI(32, 8, -15, -15)
} // namespace
} // namespace vadd_vi_test