blob: 2d132e13ba0e0c1db429de1ebfe6846d9869c8b5 [file] [log] [blame]
/*
* Copyright 2023 Google LLC
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <springbok.h>
#include <assert.h>
#define VECLEN 8
int main(int argc, char **argv) {
LOG_INFO("Vector Executive");
LOG_INFO("Built at: " __DATE__ ", " __TIME__);
uint32_t mhartid;
__asm__ volatile("csrr %0, mhartid" : "=r" (mhartid));
LOG_INFO("HARTID: 0x%08x", (unsigned int)mhartid);
uint32_t mstatus;
__asm__ volatile("csrr %0, mstatus" : "=r" (mstatus));
LOG_INFO("MSTATUS: 0x%08x", (unsigned int)mstatus);
mstatus |= (1 << 9); // Turn on vector extension
__asm__ volatile("csrw mstatus, %0" : : "r" (mstatus));
__asm__ volatile("csrr %0, mstatus" : "=r" (mstatus));
LOG_INFO("MSTATUS: 0x%08x", (unsigned int)mstatus);
// Configure vector CSRs
__asm__ volatile("csrw vxsat, 0");
__asm__ volatile("csrw vxrm, 0");
__asm__ volatile("li a1, 8");
__asm__ volatile("vsetvli t0, a1, e32, m1, tu, mu"); // 8 elements of 32 bits
// Load vectors with data. v0: 1,2,..,8. v1: 9,10,..,16.
uint32_t vector0[VECLEN];
uint32_t vector1[VECLEN];
for(int i = 0; i < VECLEN; i++) {
vector0[i] = i + 1;
vector1[i] = i + 1 + VECLEN;
}
__asm__ volatile("vle32.v v0, (%0)" : : "r" (vector0));
__asm__ volatile("vle32.v v1, (%0)" : : "r" (vector1));
uint32_t vec_mul[VECLEN];
__asm__ volatile("vmul.vv v2, v1, v0");
__asm__ volatile("vse32.v v2, (%0)" : : "r" (vec_mul));
uint32_t vec_add[VECLEN];
__asm__ volatile("vadd.vv v2, v1, v0");
__asm__ volatile("vse32.v v2, (%0)" : : "r" (vec_add));
for(int i = 0; i < VECLEN; i++) {
LOG_INFO("Expected %u, %u : Actual %u, %u", vector0[i] * vector1[i], vector0[i] + vector1[i], vec_mul[i], vec_add[i]);
assert(vector0[i] * vector1[i] == vec_mul[i]);
assert(vector0[i] + vector1[i] == vec_add[i]);
}
return 0;
}