Add vector_executive target.

Change-Id: Ife89b33683b5b3c3bd3d61fcf38eb30a77f5709c

CMakeLists.txt

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 556308a..69de19a 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -16,4 +16,5 @@
 add_subdirectory(hello_vec)
 add_subdirectory(vector_tests)
 add_subdirectory(vector_load_tests)
-add_subdirectory(vector_vadd_vsub_tests)
\ No newline at end of file
+add_subdirectory(vector_vadd_vsub_tests)
+add_subdirectory(vector_executive)
\ No newline at end of file

vector_executive/CMakeLists.txt

diff --git a/vector_executive/CMakeLists.txt b/vector_executive/CMakeLists.txt
new file mode 100644
index 0000000..326e2c5
--- /dev/null
+++ b/vector_executive/CMakeLists.txt
@@ -0,0 +1,34 @@
+cmake_minimum_required(VERSION 3.10)
+
+project(vector_executive)
+
+set(TARGET vector_executive)
+set(ELF ${TARGET}.elf)
+
+add_executable(${ELF} ${TARGET}.c)
+
+set_target_properties(${ELF} PROPERTIES LINK_DEPENDS "${LINKER_SCRIPT}")
+
+target_link_libraries(${ELF} springbok)
+
+set_target_properties(
+	${ELF}
+	PROPERTIES
+	LINK_FLAGS
+     "-specs=nano.specs \
+    -Wl,--gc-sections \
+    -Wl,--print-memory-usage \
+    -Wl,-Map=${PROJECT_NAME}.map \
+    -T${LINKER_SCRIPT}")
+
+target_compile_options(${ELF} PUBLIC
+    -Wall
+    -Werror
+    -std=c11
+    -O3
+    -g3
+    -ggdb
+    -ffreestanding
+    -ffunction-sections
+    -fstack-usage
+    -mstrict-align)

vector_executive/README.md

diff --git a/vector_executive/README.md b/vector_executive/README.md
new file mode 100644
index 0000000..ed07217
--- /dev/null
+++ b/vector_executive/README.md
@@ -0,0 +1,14 @@
+## Overview
+The `vector_executive` example will eventually evolve into the Vector Executive, which is the bare-metal program running on the vector core that executes models.
+
+Currently the `vector_executive` example shows an example of a vector multiply, add, and a test to ensure correctness.
+
+### Build
+`m shodan_test_sw_vector_executive`
+
+### Run
+```bash
+qemu-system-riscv32 -s -nographic -cpu rv32,x-v=true,vlen=256,vext_spec=v1.0 -M opentitan
+-kernel out/shodan/build-out/sw_shodan/device/examples/vector_executive/vector_executive_sim_verilator.elf
+-bios out/shodan/build-bin/sw/device/boot_rom/boot_rom_fpga_nexysvideo.elf
+```
\ No newline at end of file

vector_executive/vector_executive.c

diff --git a/vector_executive/vector_executive.c b/vector_executive/vector_executive.c
new file mode 100644
index 0000000..1a0619e
--- /dev/null
+++ b/vector_executive/vector_executive.c
@@ -0,0 +1,52 @@
+
+#include <springbok.h>
+#include <assert.h>
+#define VECLEN 8
+
+void main(int argc, char **argv) {
+
+  LOG_INFO("Vector Executive");
+  LOG_INFO("Built at: " __DATE__ ", " __TIME__);
+
+  uint32_t mhartid;
+  __asm__ volatile("csrr %0, mhartid" : "=r" (mhartid));
+  LOG_INFO("HARTID: 0x%08x", (unsigned int)mhartid);
+  uint32_t mstatus;
+  __asm__ volatile("csrr %0, mstatus" : "=r" (mstatus));
+  LOG_INFO("MSTATUS: 0x%08x", (unsigned int)mstatus);
+  mstatus |= (1 << 9);  // Turn on vector extension
+  __asm__ volatile("csrw mstatus, %0" : : "r" (mstatus));
+  __asm__ volatile("csrr %0, mstatus" : "=r" (mstatus));
+  LOG_INFO("MSTATUS: 0x%08x", (unsigned int)mstatus);
+
+  // Configure vector CSRs
+  __asm__ volatile("csrw vxsat, 0");
+  __asm__ volatile("csrw vxrm, 0");
+  __asm__ volatile("li a1, 8");
+  __asm__ volatile("vsetvli t0, a1, e32"); // 8 elements of 32 bits
+
+  // Load vectors with data. v0: 1,2,..,8. v1: 9,10,..,16.
+  uint32_t vector0[VECLEN];
+  uint32_t vector1[VECLEN];
+  for(int i = 0; i < VECLEN; i++) {
+    vector0[i] = i + 1;
+    vector1[i] = i + 1 + VECLEN;
+  }
+
+  __asm__ volatile("vle32.v  v0, (%0)" : : "r" (vector0));
+  __asm__ volatile("vle32.v  v1, (%0)" : : "r" (vector1));
+
+  uint32_t vec_mul[VECLEN];
+  __asm__ volatile("vmul.vv v2, v1, v0");
+  __asm__ volatile("vse32.v v2, (%0)" : : "r" (vec_mul));
+
+  uint32_t vec_add[VECLEN];
+  __asm__ volatile("vadd.vv v2, v1, v0");
+  __asm__ volatile("vse32.v v2, (%0)" : : "r" (vec_add));
+
+  for(int i = 0; i < VECLEN; i++) {
+    LOG_INFO("Expected %lu, %lu : Actual %lu, %lu", vector0[i] * vector1[i], vector0[i] + vector1[i], vec_mul[i], vec_add[i]);
+    assert(vector0[i] * vector1[i] == vec_mul[i]);
+    assert(vector0[i] + vector1[i] == vec_add[i]);
+  }
+}