Fix vector load instruction post increment register encoding

Fix rs1 encoding

PiperOrigin-RevId: 553227108

sim/kelvin_encoding.cc

diff --git a/sim/kelvin_encoding.cc b/sim/kelvin_encoding.cc
index a92b6c3..76a3cfe 100644
--- a/sim/kelvin_encoding.cc
+++ b/sim/kelvin_encoding.cc
@@ -296,6 +296,9 @@
           return GetRegisterDestinationOp<mpact::sim::riscv::RV32Register>(
               state_, "X0Dest", 0, xreg_alias_[0]);
         } else {
+          // `vs1` is stored in bit[19:14], but scalar xs1 is in bit[19:15]
+          // (same as the regular riscv32 encoding)
+          reg_num >>= 1;
           return GetRegisterDestinationOp<mpact::sim::riscv::RVFpRegister>(
               state_, absl::StrCat(KelvinState::kXregPrefix, reg_num), latency,
               xreg_alias_[reg_num]);