No public description

PiperOrigin-RevId: 590731784

LICENSE

diff --git a/LICENSE b/LICENSE
index 7a4a3ea..bdecd77 100644
--- a/LICENSE
+++ b/LICENSE
@@ -187,7 +187,7 @@
       same "printed page" as the copyright notice for easier
       identification within third-party archives.
 
-   Copyright [yyyy] [name of copyright owner]
+   Copyright 2023 Google LLC
 
    Licensed under the Apache License, Version 2.0 (the "License");
    you may not use this file except in compliance with the License.

sim/BUILD

diff --git a/sim/BUILD b/sim/BUILD
index 7e7068b..4722ff7 100644
--- a/sim/BUILD
+++ b/sim/BUILD
@@ -32,6 +32,7 @@
     ],
     deps = [
         "@com_google_absl//absl/functional:any_invocable",
+        "@com_google_absl//absl/log",
         "@com_google_absl//absl/log:check",
         "@com_google_absl//absl/strings",
         "@com_google_absl//absl/strings:str_format",

sim/kelvin_state.cc

diff --git a/sim/kelvin_state.cc b/sim/kelvin_state.cc
index a5c0ca3..6445099 100644
--- a/sim/kelvin_state.cc
+++ b/sim/kelvin_state.cc
@@ -21,24 +21,36 @@
 #include <string>
 
 #include "absl/log/check.h"
+#include "absl/log/log.h"
 #include "absl/strings/str_format.h"
 #include "absl/strings/string_view.h"
+#include "riscv/riscv_csr.h"
 #include "riscv/riscv_state.h"
 #include "mpact/sim/util/memory/memory_interface.h"
 
 namespace kelvin::sim {
 
+using ::mpact::sim::riscv::RiscVCsrEnum;
+
+enum class KelvinCsrEnum {
+  kKIsa = 0xFC0,
+};
+
 constexpr uint32_t kVectorRegisterWidth = 32;
 
 KelvinState::KelvinState(
     absl::string_view id, mpact::sim::riscv::RiscVXlen xlen,
     mpact::sim::util::MemoryInterface *memory,
     mpact::sim::util::AtomicMemoryOpInterface *atomic_memory)
-    : mpact::sim::riscv::RiscVState(id, xlen, memory, atomic_memory) {
+    : mpact::sim::riscv::RiscVState(id, xlen, memory, atomic_memory),
+      kisa_("kisa", static_cast<RiscVCsrEnum>(KelvinCsrEnum::kKIsa), this) {
   set_vector_register_width(kVectorRegisterWidth);
   for (int i = 0; i < acc_register_.size(); ++i) {
     acc_register_[i].fill(0);
   }
+  if (!csr_set()->AddCsr(&kisa_).ok()) {
+    LOG(FATAL) << "Failed to register kisa";
+  };
 }
 
 KelvinState::KelvinState(absl::string_view id,

sim/kelvin_state.h

diff --git a/sim/kelvin_state.h b/sim/kelvin_state.h
index 6eec9b0..5c66649 100644
--- a/sim/kelvin_state.h
+++ b/sim/kelvin_state.h
@@ -26,6 +26,7 @@
 
 #include "absl/functional/any_invocable.h"
 #include "absl/strings/string_view.h"
+#include "riscv/riscv_csr.h"
 #include "riscv/riscv_state.h"
 #include "mpact/sim/generic/instruction.h"
 #include "mpact/sim/util/memory/memory_interface.h"
@@ -110,6 +111,9 @@
 
   // Depthwise convolution accumulation register.
   DwAccArray depthwise_acc_register_;
+
+  // Kelvin-specific CSR, contains information about the Kelvin ISA version.
+  mpact::sim::riscv::RiscV32SimpleCsr kisa_;
 };
 
 }  // namespace kelvin::sim

sim/test/kelvin_top_test.cc

diff --git a/sim/test/kelvin_top_test.cc b/sim/test/kelvin_top_test.cc
index e82eb34..39c5c85 100644
--- a/sim/test/kelvin_top_test.cc
+++ b/sim/test/kelvin_top_test.cc
@@ -445,6 +445,10 @@
     read_value = result.value();
     EXPECT_EQ(read_value, write_value);
   }
+  // Custom CSRs.
+  for (auto name : {"kisa"}) {
+    EXPECT_OK(kelvin_top_->ReadRegister(name));
+  }
 }
 
 TEST_F(KelvinTopTest, RunKelvinVectorProgram) {