sim: Update UARTs to use the upstream OpenTitan UART

This stops us from using the "OpenTitan2" UART that we have in shodan
infrastructure in deference to the real one in the upstream Renode
code, which matches upstream OpenTitan and all it's register warts.

Bug: 228243751
Change-Id: I91bf4dc23ad38ff90f4043548d986abb85f189ce

platforms/secure.repl

diff --git a/platforms/secure.repl b/platforms/secure.repl
index 7c0be01..76a1a37 100644
--- a/platforms/secure.repl
+++ b/platforms/secure.repl
@@ -33,7 +33,7 @@
     size: 0x01000000
 
 // UART0             [‘h4000_0000 - ‘h4000_0FFF)   4KB UART0 for Security Core
-uart0: UART.OpenTitan2_UART @ sysbus 0x40000000
+uart0: UART.OpenTitan_UART @ sysbus 0x40000000
     TxWatermarkIRQ -> plic@1
     RxWatermarkIRQ -> plic@2
     TxEmptyIRQ -> plic@3
@@ -44,7 +44,7 @@
     RxParityErrorIRQ -> plic@8
 
 // UART1             [‘h4001_0000 - ‘h4001_0FFF)   4KB UART1 (Reserved)
-uart1: UART.OpenTitan2_UART @ sysbus 0x40010000
+uart1: UART.OpenTitan_UART @ sysbus 0x40010000
     TxWatermarkIRQ -> plic@9
     RxWatermarkIRQ -> plic@10
     TxEmptyIRQ -> plic@11
@@ -55,7 +55,7 @@
     RxParityErrorIRQ -> plic@16
 
 // UART2             [‘h4002_0000 - ‘h4002_0FFF)   4KB UART2 for Vector Core
-uart2: UART.OpenTitan2_UART @ sysbus 0x40020000
+uart2: UART.OpenTitan_UART @ sysbus 0x40020000
     TxWatermarkIRQ -> plic@17
     RxWatermarkIRQ -> plic@18
     TxEmptyIRQ -> plic@19
@@ -66,7 +66,7 @@
     RxParityErrorIRQ -> plic@24
 
 // UART3             [‘h4003_0000 - ‘h4003_0FFF)   4KB UART3 (Reserved)
-uart3: UART.OpenTitan2_UART @ sysbus 0x40030000
+uart3: UART.OpenTitan_UART @ sysbus 0x40030000
     TxWatermarkIRQ -> plic@25
     RxWatermarkIRQ -> plic@26
     TxEmptyIRQ -> plic@27