cheriot: Added cheriot's testbench

- Added a sail.repl that matches sail.json spec
- Removed uart specification from cheriot.repl; they should be added in sencha_smc.repl and sail.repl, as appropriate
- cheriot.resc should load sail.repl and test-suite to run the tests in standalone cheriot

Bypass-Presubmit-Reason: no sencha CI tests

Change-Id: I42ed7701087b2818660d7e3d30afbdd2035880de

cheriot.resc

diff --git a/cheriot.resc b/cheriot.resc
index bf8b901..bf46c98 100644
--- a/cheriot.resc
+++ b/cheriot.resc
@@ -20,7 +20,7 @@
 EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.MpactCPU.MpactCheriotCPU"
 EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.MpactCPU.MpactCheriotPeripheral"
 
-$platformfile?=@sim/config/platforms/cheriot.repl
+$platformfile?=@sim/config/platforms/sail.repl
 
 machine LoadPlatformDescription $platformfile
 
@@ -43,8 +43,7 @@
 
 logLevel 0 sysbus.cpu1
 
-$bin?=@out/cheriot/sencha/release/cheriot/cheriot/release/soundstream-firmware
-#$bin?=@sw/cheriot-rtos/examples/01.hello_world/build/cheriot/cheriot/release/hello_world
+$bin?=@out/cheriot/sencha/release/cheriot/cheriot/release/test-suite
 
 # Load the ELF file (useVirtualAddress = false, allowLoadsOnlyToMemory = false)
 sysbus LoadELF $bin false false

platforms/cheriot.repl

diff --git a/platforms/cheriot.repl b/platforms/cheriot.repl
index 3e10869..59c12ec 100644
--- a/platforms/cheriot.repl
+++ b/platforms/cheriot.repl
@@ -26,8 +26,6 @@
     baseAddress: 0x80000000
     mpactCpu: cpu1
 
-uart5: Antmicro.Renode.Peripherals.UART.TrivialUart @ sysbus 0x54000000
-
 smc_plic: IRQControllers.PlatformLevelInterruptController @sysbus 0x60000000
     0 -> cpu1@11
     numberOfSources: 42

platforms/sail.repl

diff --git a/platforms/sail.repl b/platforms/sail.repl
new file mode 100644
index 0000000..e723c38
--- /dev/null
+++ b/platforms/sail.repl
@@ -0,0 +1,21 @@
+//
+// Copyright (c) 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     https://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// This is compatible with the board sail.json
+
+using "sim/config/platforms/cheriot.repl"
+
+uart5: Antmicro.Renode.Peripherals.UART.TrivialUart @ sysbus 0x10000000
+

platforms/sencha_smc.repl

diff --git a/platforms/sencha_smc.repl b/platforms/sencha_smc.repl
index 702642a..8910567 100644
--- a/platforms/sencha_smc.repl
+++ b/platforms/sencha_smc.repl
@@ -18,6 +18,9 @@
 // ***************************************************
 
 using "sim/config/platforms/cheriot.repl"
+
+uart5: Antmicro.Renode.Peripherals.UART.TrivialUart @ sysbus 0x54000000
+
 // Control block for the SMC, lets us pause/restart the core at an arbitrary PC.
 smc_control: MpactCPU.SmcCheriot_ControlBlock @ sysbus 0x54020000
     cpu: cpu1