shodan_infrastructure/SmcRiscV32.cs

//
// Copyright (c) 2021 Google LLC
//
// This file is licensed under the MIT License.
// Full license text is available in 'licenses/MIT.txt'.
//
using Antmicro.Renode.Core;
using Antmicro.Renode.Logging;
using Antmicro.Renode.Peripherals.Bus;

namespace Antmicro.Renode.Peripherals.CPU
{
  public class SmcRiscV32_ControlBlock : IDoubleWordPeripheral, IKnownSize
  {
    public SmcRiscV32_ControlBlock(RiscV32 cpu)
    {
      this.cpu = cpu;
    }

    public void Reset() // IPeripheral
    {
    }

    public uint ReadDoubleWord(long offset) // IDoubleWordPeripheral
    {
      return cpu.PC;
    }

    public void WriteDoubleWord(long offset, uint value) // IDoubleWordPeripheral
    {
      if (value == 0) {
        this.Log(LogLevel.Noisy, "Stopping SMC");
        cpu.PC = 0;
        cpu.IsHalted = true;
      }
      else {
        this.Log(LogLevel.Noisy, "Starting SMC at 0x{0:X8}", value);
        cpu.PC = value;
        cpu.IsHalted = false;
      }
    }

    public long Size => 0x4;
    private RiscV32 cpu;
  }
}