sencha_smc: add plic comments

Clarify plic interrupt configuration; the cheri-enabled core does not
implement S  mode.

Change-Id: I666b041972932137e62707be7b33c05cbc95ce38

platforms/sencha_smc.repl

diff --git a/platforms/sencha_smc.repl b/platforms/sencha_smc.repl
index e6d2519..c457b35 100644
--- a/platforms/sencha_smc.repl
+++ b/platforms/sencha_smc.repl
@@ -41,9 +41,13 @@
     [0, 1] ->cpu1@[3, 7]
 
 smc_plic: IRQControllers.PlatformLevelInterruptController @ sysbus 0x60000000 // TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR @ top_matcha.h
+    // Numbers on the left (0 ->) index PLIC GetGPIOs.
+    //
+    // Numbers on the right reference bits in the target MIP.
+    // Bit 11 corresponds MEIP and bit 9 to SEIP.
     0 -> cpu1@11
     numberOfSources: 42
-    numberOfContexts: 1
+    numberOfContexts: 1  // MEIP only
     prioritiesEnabled: false
 
 // XXX use TrivialUart until cheriot-rtos has an OpenTitan_UART driver