OSS cleanup Add OSS headers, license, readme, and contributing doc. Remove obsolete components and simulation configs Bug: 306427497 Change-Id: I67a7615f20d5ce96557637c192575a835a35f9be
diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md new file mode 100644 index 0000000..593455a --- /dev/null +++ b/CONTRIBUTING.md
@@ -0,0 +1,28 @@ +# How to Contribute + +We'd love to accept your patches and contributions to this project. There are +just a few small guidelines you need to follow. + +## Contributor License Agreement + +Contributions to this project must be accompanied by a Contributor License +Agreement. You (or your employer) retain the copyright to your contribution; +this simply gives us permission to use and redistribute your contributions as +part of the project. Head over to <https://cla.developers.google.com/> to see +your current agreements on file or to sign a new one. + +You generally only need to submit a CLA once, so if you've already submitted one +(even if it was for a different project), you probably don't need to do it +again. + +## Code Reviews + +All submissions, including submissions by project members, require review. We +use Gerrit code review for this purpose. Consult +[Gerrit User Guide](https://gerrit-documentation.storage.googleapis.com/Documentation/3.8.2/intro-user.html) +for more information. + +## Community Guidelines + +This project follows +[Google's Open Source Community Guidelines](https://opensource.google/conduct/).
diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..7a4a3ea --- /dev/null +++ b/LICENSE
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diff --git a/README.md b/README.md new file mode 100644 index 0000000..cc6106b --- /dev/null +++ b/README.md
@@ -0,0 +1,11 @@ +# Simulation Configuration + +This project hosts the [Renode](https://github.com/renode/renode) simulation +description, platform definition, and simulation models for customized +components. + +## Project structure + +- *platforms*: renode platform definitions +- *shodan_infrastructure*: customized component model used in + Renode's runtime compilation
diff --git a/hps.resc b/hps.resc deleted file mode 100644 index b3e9e2c..0000000 --- a/hps.resc +++ /dev/null
@@ -1,74 +0,0 @@ -:name: HPS -:description: This script runs the HPS Demo - -$name?="matcha" - -using sysbus -mach create $name -EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.RiscV32" -include @sim/config/shodan_infrastructure/SpringbokRiscV32.cs -EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.SpringbokRiscV32" -EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.SpringbokRiscV32_ControlBlock" -include @sim/config/shodan_infrastructure/SmcRiscV32.cs -include @sim/config/shodan_infrastructure/Mailbox.cs -include @sim/config/shodan_infrastructure/AddressRangeStub.cs -include @sim/config/shodan_infrastructure/CamCtrl.cs -include @sim/config/shodan_infrastructure/DoubleBufferDMA.cs - -machine LoadPlatformDescription @sim/config/platforms/hps.repl - -cam_i2c.camera AddFrame @out/springbok_iree/quant_models/hps_0_quant_input -cam_i2c.camera AddFrame @out/springbok_iree/quant_models/hps_1_quant_input -cam_i2c.camera AddFrame @out/springbok_iree/quant_models/hps_2_quant_input -cam_i2c.camera AddFrame @out/springbok_iree/quant_models/hps_3_quant_input -cam_i2c.camera AddFrame @out/springbok_iree/quant_models/hps_4_quant_input -cam_i2c.camera AddFrame @out/springbok_iree/quant_models/hps_5_quant_input - -$term_port?=3456 -emulation CreateServerSocketTerminal $term_port "term" false -connector Connect uart5 term -# for a client, bash users may consider this inline script: -# -# stty sane -echo -icanon; socat TCP:localhost:$term_port -; stty sane -# -# tmux users may consider adding a binding to ~/.tmux.conf -# -# bind-key k split-window "stty -echo -icanon; socat TCP:localhost:$term_port -" - -# Hook up the analyzers to the uarts so we can see their output in the main -# Renode log -showAnalyzer "uart0-analyzer" sysbus.uart0 Antmicro.Renode.Analyzers.LoggingUartAnalyzer -showAnalyzer "uart5-analyzer" sysbus.uart5 Antmicro.Renode.Analyzers.LoggingUartAnalyzer - -# Set the uarts host/virt timestamp format. Options: None, Virtual, Host, Full. -uart0-analyzer TimestampFormat None -uart5-analyzer TimestampFormat None - -# Load the bootrom into the 32k rom at 0x8000 (useVirtualAddress = false, allowLoadsOnlyToMemory = true) -sysbus LoadELF @out/shodan_boot_rom/multihart_boot_rom.elf false true cpu0 - -# Load the tarball of Tock on SEC, Tock on SMC, and HPS model. -$tar ?= @out/hps_ext_flash_release.tar -sysbus LoadBinary $tar 0x44000000 - -# Start cpu0 at the bootrom reset vector, which is stored immediately after the -# bootrom interrupt vector table at 0x8080. -# (see https://ibex-core.readthedocs.io/en/latest/03_reference/exception_interrupts.html for details) -sysbus.cpu0 PC 0x8080 - -# Start the vector core at address 0 of its instruction TCM. -sysbus.cpu2 PC 0x34000000 -# Set the vector core to be less interactive to IO for faster execution -$vector_core_mips ?= 1000 -sysbus.cpu2 PerformanceInMips $vector_core_mips - -# Start GDB and halt both cores so we can connect GDB before the bootrom has -# started. -$gdb_port?=3333 -machine StartGdbServer $gdb_port false cpu0 -machine StartGdbServer $gdb_port false cpu1 -machine StartGdbServer $gdb_port false cpu2 - -cpu0 IsHalted true -cpu1 IsHalted true -cpu2 IsHalted true
diff --git a/platforms/hps.repl b/platforms/hps.repl index a902f72..8df26e9 100644 --- a/platforms/hps.repl +++ b/platforms/hps.repl
@@ -1,3 +1,18 @@ +// +// Copyright (c) 2023 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + using "sim/config/platforms/shodan.repl" cam_ctrl: Sensors.CamCtrl @ sysbus 0x54050000
diff --git a/platforms/nexus-debug.repl b/platforms/nexus-debug.repl index 6428069..537cc64 100644 --- a/platforms/nexus-debug.repl +++ b/platforms/nexus-debug.repl
@@ -1,3 +1,18 @@ +// +// Copyright (c) 2023 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + // A renode platform file used by debug config using "sim/config/platforms/nexus.repl"
diff --git a/platforms/nexus.repl b/platforms/nexus.repl index 0a32c88..c65e57c 100644 --- a/platforms/nexus.repl +++ b/platforms/nexus.repl
@@ -1,3 +1,18 @@ +// +// Copyright (c) 2023 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + using "sim/config/platforms/nexus_smc.repl" using "sim/config/platforms/secure.repl" using "sim/config/platforms/kelvin.repl"
diff --git a/platforms/nexus_smc.repl b/platforms/nexus_smc.repl index 65fd3d5..307f4ec 100644 --- a/platforms/nexus_smc.repl +++ b/platforms/nexus_smc.repl
@@ -1,3 +1,18 @@ +// +// Copyright (c) 2023 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + // *************************************************** // Nexus-specific SMC // ***************************************************
diff --git a/platforms/opentitan-earlgrey-cw310.repl b/platforms/opentitan-earlgrey-cw310.repl index 8de9818..e6944e4 100644 --- a/platforms/opentitan-earlgrey-cw310.repl +++ b/platforms/opentitan-earlgrey-cw310.repl
@@ -1,3 +1,18 @@ +// +// Copyright (c) 2023 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + // fpga_cw310 target uses different clock frequencies // https://github.com/lowRISC/opentitan/blob/2fb276797e0dcda96195b1e4617f2aac82a925f0/sw/device/lib/arch/device_fpga_cw310.c using "sim/renode/platforms/cpus/opentitan-earlgrey.repl"
diff --git a/platforms/opentitan-earlgrey-gen.repl b/platforms/opentitan-earlgrey-gen.repl deleted file mode 100644 index 2f1fdf2..0000000 --- a/platforms/opentitan-earlgrey-gen.repl +++ /dev/null
@@ -1,234 +0,0 @@ -// OpenTitan variant Earlgrey - -// CPUs -// Platform has 1 core -// By default the OT design assumes secure core is hart_id == 0 -cpu0: CPU.IbexRiscV32 @ sysbus - hartId: 0 - cpuType: "rv32imac" - timeProvider: empty - allowUnalignedAccesses: true - -// Memory configuration -ram_ret_aon: Memory.MappedMemory @ sysbus 0x40600000 - size: 0x1000 - -eflash: Memory.MappedMemory @ { - sysbus 0x20000000; - sysbus 0x80000000 // virtual translation base - } - size: 0x100000 - -ram_main: Memory.MappedMemory @ sysbus 0x10000000 - size: 0x20000 - -rom: Memory.MappedMemory @ sysbus 0x00008000 - size: 0x8000 - - -// PinMux -// As there is no OpenTitan PinMux support in Renode just configure some memory. -pinmux_aon: Memory.MappedMemory @ sysbus 0x40460000 - size: 0x1000 - - -// GPIOs -gpio: GPIOPort.OpenTitan_GPIO @ sysbus 0x40040000 - - -// Power Manager -pwrmgr_aon: Miscellaneous.OpenTitan_PowerManager @ sysbus 0x40400000 - - -// UARTs -uart0: UART.OpenTitan_UART @ sysbus 0x40000000 - TxWatermarkIRQ -> rv_plic@1 - RxWatermarkIRQ -> rv_plic@2 - TxEmptyIRQ -> rv_plic@3 - RxOverflowIRQ -> rv_plic@4 - RxFrameErrorIRQ -> rv_plic@5 - RxBreakErrorIRQ -> rv_plic@6 - RxTimeoutIRQ -> rv_plic@7 - RxParityErrorIRQ -> rv_plic@8 - -uart1: UART.OpenTitan_UART @ sysbus 0x40010000 - TxWatermarkIRQ -> rv_plic@9 - RxWatermarkIRQ -> rv_plic@10 - TxEmptyIRQ -> rv_plic@11 - RxOverflowIRQ -> rv_plic@12 - RxFrameErrorIRQ -> rv_plic@13 - RxBreakErrorIRQ -> rv_plic@14 - RxTimeoutIRQ -> rv_plic@15 - RxParityErrorIRQ -> rv_plic@16 - -uart2: UART.OpenTitan_UART @ sysbus 0x40020000 - TxWatermarkIRQ -> rv_plic@17 - RxWatermarkIRQ -> rv_plic@18 - TxEmptyIRQ -> rv_plic@19 - RxOverflowIRQ -> rv_plic@20 - RxFrameErrorIRQ -> rv_plic@21 - RxBreakErrorIRQ -> rv_plic@22 - RxTimeoutIRQ -> rv_plic@23 - RxParityErrorIRQ -> rv_plic@24 - -uart3: UART.OpenTitan_UART @ sysbus 0x40030000 - TxWatermarkIRQ -> rv_plic@25 - RxWatermarkIRQ -> rv_plic@26 - TxEmptyIRQ -> rv_plic@27 - RxOverflowIRQ -> rv_plic@28 - RxFrameErrorIRQ -> rv_plic@29 - RxBreakErrorIRQ -> rv_plic@30 - RxTimeoutIRQ -> rv_plic@31 - RxParityErrorIRQ -> rv_plic@32 - - -// HMAC -hmac: Miscellaneous.OpenTitan_HMAC @ sysbus 0x41110000 - - -// Flash Controller -flash_ctrl: MTD.OpenTitan_FlashController @ sysbus 0x41000000 - flash: eflash - ProgramEmptyIRQ -> rv_plic@155 - ProgramLevelIRQ -> rv_plic@156 - ReadFullIRQ -> rv_plic@157 - ReadLevelIRQ -> rv_plic@158 - OperationDoneIRQ -> rv_plic@159 - CorrectableErrorIRQ -> rv_plic@160 - - -// Timers -// TODO(julianmb): The timer interrupt is both connected to the PLIC and the CPU in RTL. Figure out how to do that in renode. -rv_timer: Timers.OpenTitan_Timer @ sysbus 0x40100000 - // MachineTimerInterrupt = 7 - IRQ -> cpu0@7 - -// Simulated SRAM used to indicate test status to simulator -swteststatus: Miscellaneous.OpenTitan_VerilatorSwTestStatus @ sysbus 0x30000000 - -// PLIC -rv_plic: IRQControllers.PlatformLevelInterruptController @ sysbus 0x48000000 - // Bit 11 corresponds MEIP - 0 -> cpu0@11 - numberOfContexts: 1 - numberOfSources: 180 - -// ROM Controller -rom_ctrl: MemoryControllers.OpenTitan_ROMController @ sysbus 0x411e0000 - rom: rom - nonce: 0xfbd120f152a9ef95 - keyHigh: 0x18d5a1fe3b04ff0 - keyLow: 0x9932a2605b23cb7a - -// AES -aes: Miscellaneous.OpenTitan_AES @ sysbus 0x41100000 - -// Key Manager -// TODO(julianmb): deviceId/rootKey/creatorKey/ownerKey. These values need to be retrieved from their origin source. -keymgr: Miscellaneous.OpenTitan_KeyManager @ sysbus 0x41140000 - OperationDoneIRQ -> rv_plic@168 - aes: aes - kmac: kmac - romController: rom_ctrl - deviceId: "0xfa53b8058e157cb69f1f413e87242971b6b52a656a1cab7febf21e5bf1f45edd" - lifeCycleDiversificationConstant: "0x6faf88f22bccd612d1c09f5c02b2c8d1" - creatorKey: "0x9152e32c9380a4bcc3e0ab263581e6b0e8825186e1e445631646e8bef8c45d47" - ownerKey: "0xfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78" - rootKey: "0xefb7ea7ee90093cf4affd9aaa2d6c0ec446cfdf5f2d5a0bfd7e2d93edc63a10256d24a00181de99e0f690b447a8dde2a1ffb8bc306707107aa6e2410f15cfc37" - softOutputSeed: "0x8db302ed56b78538c92ba96fe7ba5d882e53c3844212490ced20e7e16f71067e" - hardOutputSeed: "0xb00fe9a3a2be362bc57ce4588424f90946b441fa5e08b2317fb3e9032db9eddf" - destinationAesSeed: "0xd05781d31c4b4dab379c12b6681950e6d52654489a981b7bdc91865141701fd5" - destinationKmacSeed: "0x1aeca9607328c3621ee7fd88c63032eb50ee437eeda142fce033c343e179c299" - destinationOtbnSeed: "0x45a488652c63c1f68cecf9596cda21a8d5398ced8676e230226a9635bea51c6e" - destinationNoneSeed: "0x4dfb68eaea920c1e6c7b2dc4b639ba1ae564b19dd8235c2f90c064c4849172a2" - revisionSeed: "0xbfafcbebd7c3361357bee83e46164c82a0c86b9c1ef6117215c2e6fcb683d3a9" - creatorIdentitySeed: "0xdf2a87abf7c57a6d06f2e1721e3a5f3b217d62acf1c966c712691421cef76350" - ownerIntermediateIdentitySeed: "0x5910642e0f9946cb60f5f7d233a13b89bfc3162d205b4d60c9b16a8eb0aa75fa" - ownerIdentitySeed: "0x30ac79eec48e320bdcfa32f724f82840fdaced02da0253d803d1cdf325afff8b" - -// KMAC -kmac: Miscellaneous.OpenTitan_KMAC @ sysbus 0x41120000 - KmacDoneIRQ -> rv_plic@164 - FifoEmptyIRQ -> rv_plic@165 - KmacErrorIRQ -> rv_plic@166 - -// Reset Manager -rstmgr_aon: Miscellaneous.OpenTitan_ResetManager @ sysbus 0x40410000 - resetPC: 0x00008084 - init: - MarkAsSkippedOnLifeCycleReset sysbus.rstmgr_aon - MarkAsSkippedOnLifeCycleReset sysbus.pwrmgr_aon - MarkAsSkippedOnSystemReset sysbus.rstmgr_aon - MarkAsSkippedOnSystemReset sysbus.pwrmgr_aon - MarkAsSkippedOnSystemReset sysbus.flash_ctrl - -// One Time Programmable Memory Controller -otp_ctrl: Miscellaneous.OpenTitan_OneTimeProgrammableMemoryController @ sysbus 0x40130000 - AValuesChain: "8638C62621EC19E8966416165252225F03B9C97821B7B107381030AB3D20AB124694BF85E417495A" - BValuesChain: "E679DF6E77EDDBECDE74B677DFF23AFFC3BFFB79B5FFFD87F930B4FB3F6BFF9A5F97BFD7FCBFE9FF" - CValuesChain: "0C1B73141BA20D421FD124302E8F443DE02C272E2CEEC1138DAD07CBD24A18F583A34D51A42A1E702A7E90F05A81D12E" - DValuesChain: "3E1FFB763FE3CDD61FF97735BEBF5CFDE5BDB7AFAEFEE19B9FBD9FCFD2EF3CF7CFEFFD53A7EE7FF36BFE92FDFA95F9AE" - -// Life Cycle Controller -lc_ctrl: Miscellaneous.OpenTitan_LifeCycleController @ sysbus 0x40140000 - resetManager: rstmgr_aon - otpController: otp_ctrl - DeviceId: "BF5EA92044DAC540CFD1A00105568DFA97D9C35EA0407D71320B5E0434DB637F" - TestExitToken: "000102030405060708090A0B0C0D0E0F" - TestUnlockToken: "79DEF38F41A9B895F6BDF341BEADA9B6" - RMAToken: "4D89B62D287CB957C2500042306DFD57" - -// Cryptographically Secure Random Number Generator -csrng: Miscellaneous.OpenTitan_CSRNG @ sysbus 0x41150000 - RequestCompletedIRQ -> rv_plic@169 - EntropyeRequestedIRQ -> rv_plic@170 - HardwareInstanceIRQ -> rv_plic@171 - FatalErrorIRQ -> rv_plic@172 - -// Tag memory for debugging -sysbus: - init: - Tag <0x40000000 0x1000> "OPENTITAN_EARLGREY_DEV_UART0" - Tag <0x40010000 0x1000> "OPENTITAN_EARLGREY_DEV_UART1" - Tag <0x40020000 0x1000> "OPENTITAN_EARLGREY_DEV_UART2" - Tag <0x40030000 0x1000> "OPENTITAN_EARLGREY_DEV_UART3" - Tag <0x40040000 0x1000> "OPENTITAN_EARLGREY_DEV_GPIO" - Tag <0x40050000 0x2000> "OPENTITAN_EARLGREY_DEV_SPI_DEVICE" - Tag <0x40060000 0x1000> "OPENTITAN_EARLGREY_DEV_SPI_HOST0" - Tag <0x40070000 0x1000> "OPENTITAN_EARLGREY_DEV_SPI_HOST1" - Tag <0x40080000 0x1000> "OPENTITAN_EARLGREY_DEV_I2C0" - Tag <0x40090000 0x1000> "OPENTITAN_EARLGREY_DEV_I2C1" - Tag <0x400A0000 0x1000> "OPENTITAN_EARLGREY_DEV_I2C2" - Tag <0x400E0000 0x1000> "OPENTITAN_EARLGREY_DEV_PATTGEN" - Tag <0x40100000 0x1000> "OPENTITAN_EARLGREY_DEV_RV_TIMER" - Tag <0x40110000 0x1000> "OPENTITAN_EARLGREY_DEV_USBDEV" - Tag <0x40130000 0x2000> "OPENTITAN_EARLGREY_DEV_OTP_CTRL" - Tag <0x40140000 0x1000> "OPENTITAN_EARLGREY_DEV_LC_CTRL" - Tag <0x40150000 0x1000> "OPENTITAN_EARLGREY_DEV_ALERT_HANDLER" - Tag <0x40400000 0x1000> "OPENTITAN_EARLGREY_DEV_PWRMGR_AON" - Tag <0x40410000 0x1000> "OPENTITAN_EARLGREY_DEV_RSTMGR_AON" - Tag <0x40420000 0x1000> "OPENTITAN_EARLGREY_DEV_CLKMGR_AON" - Tag <0x40430000 0x1000> "OPENTITAN_EARLGREY_DEV_SYSRST_CTRL_AON" - Tag <0x40440000 0x1000> "OPENTITAN_EARLGREY_DEV_ADC_CTRL_AON" - Tag <0x40450000 0x1000> "OPENTITAN_EARLGREY_DEV_PWM_AON" - Tag <0x40460000 0x1000> "OPENTITAN_EARLGREY_DEV_PINMUX_AON" - Tag <0x40470000 0x1000> "OPENTITAN_EARLGREY_DEV_AON_TIMER_AON" - Tag <0x40480000 0x1000> "OPENTITAN_EARLGREY_DEV_AST" - Tag <0x40490000 0x1000> "OPENTITAN_EARLGREY_DEV_SENSOR_CTRL" - Tag <0x40500000 0x1000> "OPENTITAN_EARLGREY_DEV_SRAM_CTRL_RET_AON" - Tag <0x41000000 0x1000> "OPENTITAN_EARLGREY_DEV_FLASH_CTRL" - Tag <0x41200000 0x1000> "OPENTITAN_EARLGREY_DEV_RV_DM" - Tag <0x48000000 0x8000000> "OPENTITAN_EARLGREY_DEV_RV_PLIC" - Tag <0x41100000 0x1000> "OPENTITAN_EARLGREY_DEV_AES" - Tag <0x41110000 0x1000> "OPENTITAN_EARLGREY_DEV_HMAC" - Tag <0x41120000 0x1000> "OPENTITAN_EARLGREY_DEV_KMAC" - Tag <0x41130000 0x10000> "OPENTITAN_EARLGREY_DEV_OTBN" - Tag <0x41140000 0x1000> "OPENTITAN_EARLGREY_DEV_KEYMGR" - Tag <0x41150000 0x1000> "OPENTITAN_EARLGREY_DEV_CSRNG" - Tag <0x41160000 0x1000> "OPENTITAN_EARLGREY_DEV_ENTROPY_SRC" - Tag <0x41170000 0x1000> "OPENTITAN_EARLGREY_DEV_EDN0" - Tag <0x41180000 0x1000> "OPENTITAN_EARLGREY_DEV_EDN1" - Tag <0x411C0000 0x1000> "OPENTITAN_EARLGREY_DEV_SRAM_CTRL_MAIN" - Tag <0x411e0000 0x1000> "OPENTITAN_EARLGREY_DEV_ROM_CTRL" - Tag <0x411F0000 0x1000> "OPENTITAN_EARLGREY_DEV_RV_CORE_IBEX" -
diff --git a/platforms/secure.repl b/platforms/secure.repl index e180afb..ae1fca7 100644 --- a/platforms/secure.repl +++ b/platforms/secure.repl
@@ -1,3 +1,18 @@ +// +// Copyright (c) 2023 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + // *************************************************** // Secure // ***************************************************
diff --git a/platforms/shodan-debug.repl b/platforms/shodan-debug.repl index 0a5bf30..00e4ed7 100644 --- a/platforms/shodan-debug.repl +++ b/platforms/shodan-debug.repl
@@ -1,3 +1,18 @@ +// +// Copyright (c) 2023 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + // A renode platform file used by debug config using "sim/config/platforms/shodan.repl"
diff --git a/platforms/smc.repl b/platforms/smc.repl index 7095cef..ce84374 100644 --- a/platforms/smc.repl +++ b/platforms/smc.repl
@@ -1,3 +1,18 @@ +// +// Copyright (c) 2023 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + // *************************************************** // SMC // ***************************************************
diff --git a/shodan.resc b/shodan.resc index 4892d82..ce5bc77 100644 --- a/shodan.resc +++ b/shodan.resc
@@ -1,3 +1,17 @@ +# Copyright 2022 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + :name: Shodan :description: This script runs Tock & seL4 on Shodan matcha
diff --git a/shodan_infrastructure/AddressRangeStub.cs b/shodan_infrastructure/AddressRangeStub.cs index db112f1..b132ea6 100644 --- a/shodan_infrastructure/AddressRangeStub.cs +++ b/shodan_infrastructure/AddressRangeStub.cs
@@ -1,3 +1,17 @@ +// Copyright 2023 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + using Antmicro.Renode.Core; using Antmicro.Renode.Logging; using Antmicro.Renode.Peripherals.Bus;
diff --git a/shodan_infrastructure/CamCtrl.cs b/shodan_infrastructure/CamCtrl.cs index 384265e..09f8398 100644 --- a/shodan_infrastructure/CamCtrl.cs +++ b/shodan_infrastructure/CamCtrl.cs
@@ -1,9 +1,17 @@ // -// Copyright (c) 2022 Google LLC +// Copyright (c) 2023 Google LLC // -// This file is licensed under the MIT License. -// Full license text is available in 'licenses/MIT.txt'. +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at // +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. using Antmicro.Renode.Core; using Antmicro.Renode.Core.Structure;
diff --git a/shodan_infrastructure/DoubleBufferDMA.cs b/shodan_infrastructure/DoubleBufferDMA.cs index 8f41019..0d42cd9 100644 --- a/shodan_infrastructure/DoubleBufferDMA.cs +++ b/shodan_infrastructure/DoubleBufferDMA.cs
@@ -1,9 +1,17 @@ // -// Copyright (c) 2022 Google LLC +// Copyright (c) 2023 Google LLC // -// This file is licensed under the MIT License. -// Full license text is available in 'licenses/MIT.txt'. +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at // +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. using Antmicro.Renode.Core; using Antmicro.Renode.Core.Structure;
diff --git a/shodan_infrastructure/KelvinRiscV32.cs b/shodan_infrastructure/KelvinRiscV32.cs deleted file mode 100644 index 1aa77c6..0000000 --- a/shodan_infrastructure/KelvinRiscV32.cs +++ /dev/null
@@ -1,486 +0,0 @@ -// -// Copyright (c) 2021 Google LLC -// -// This file is licensed under the MIT License. -// Full license text is available in 'licenses/MIT.txt'. -// -using System; -using System.Linq; -using System.Text; - -using Antmicro.Renode.Core; -using Antmicro.Renode.Core.Structure.Registers; -using Antmicro.Renode.Exceptions; -using Antmicro.Renode.Logging; -using Antmicro.Renode.Peripherals.Miscellaneous; -using Antmicro.Renode.Peripherals.Bus; -using Antmicro.Renode.Utilities; -using Antmicro.Renode.Debugging; - -using Endianess = ELFSharp.ELF.Endianess; - -namespace Antmicro.Renode.Peripherals.CPU -{ - public class KelvinRiscV32 : RiscV32 - { - public KelvinRiscV32(Core.Machine machine, - uint hartId = 0, - PrivilegeArchitecture privilegeArchitecture = PrivilegeArchitecture.Priv1_11, - Endianess endianness = Endianess.LittleEndian, - string cpuType = "rv32im") - : base(null, cpuType, machine, hartId, privilegeArchitecture, endianness) - { - InstallCustomInstruction(pattern: "00000000000100000000000001110011", handler: HandleKelvinEBreak); // Kelvin doesn't implement rv32i ebreak correctly - InstallCustomInstruction(pattern: "00000010000000000000000001110011", handler: HandleKelvinEExit); - InstallCustomInstruction(pattern: "00000100000000000000000001110011", handler: HandleKelvinEYield); - InstallCustomInstruction(pattern: "00000110000000000000000001110011", handler: HandleKelvinECtxSw); - InstallCustomInstruction(pattern: "00001000000000000000000001110011", handler: HandleKelvinMPause); - InstallCustomInstruction(pattern: "011110000000-----000000001110111", handler: HandleKelvinFLog); - InstallCustomInstruction(pattern: "011110000000-----001000001110111", handler: HandleKelvinSLog); - InstallCustomInstruction(pattern: "011110000000-----010000001110111", handler: HandleKelvinCLog); - InstallCustomInstruction(pattern: "011110000000-----011000001110111", handler: HandleKelvinKLog); - InstallCustomInstruction(pattern: "00100110000000000000000001110111", handler: HandleKelvinFlushAll); - InstallCustomInstruction(pattern: "001001100000-----000000001110111", handler: HandleKelvinFlushAt); - - Reset(); - } - - public override void Reset() - { - base.Reset(); - - // This core comes out of reset paused. - this.IsHalted = true; - - if(ControlBlockRegistered) - { - ControlBlock.Reset(); - } - } - - public void RegisterControlBlock(KelvinRiscV32_ControlBlock controlBlock) - { - ControlBlock = controlBlock; - ControlBlockRegistered = true; - } - - // A no-op API to match the KelvinCPU interface - public string CpuLibraryPath { get; set; } - - private KelvinRiscV32_ControlBlock ControlBlock; - private bool ControlBlockRegistered = false; - - private void HandleKelvinEBreak(UInt64 opcode) - { - ControlBlock.ExecEBreak(); - } - - private void HandleKelvinEExit(UInt64 opcode) - { - ControlBlock.ExecEBreak(); - } - - private void HandleKelvinEYield(UInt64 opcode) - { - // To be implemented - ControlBlock.ExecEBreak(); - } - - private void HandleKelvinECtxSw(UInt64 opcode) - { - // To be implemented - ControlBlock.ExecEBreak(); - } - - private void HandleKelvinMPause(UInt64 opcode) - { - ControlBlock.ExecMPause(); - } - - private void HandleKelvinFLog(UInt64 opcode) - { - this.Log(LogLevel.Noisy, "FLog dropped (unimplemented)"); - // To be implemented - } - - private void HandleKelvinSLog(UInt64 opcode) - { - this.Log(LogLevel.Noisy, "SLog dropped (unimplemented)"); - // To be implemented - } - - private void HandleKelvinCLog(UInt64 opcode) - { - this.Log(LogLevel.Noisy, "CLog dropped (unimplemented)"); - // To be implemented - } - - private void HandleKelvinKLog(UInt64 opcode) - { - this.Log(LogLevel.Noisy, "KLog dropped (unimplemented)"); - // To be implemented - } - - private void HandleKelvinFlushAll(UInt64 opcode) - { - // No-op in simulator - } - - private void HandleKelvinFlushAt(UInt64 opcode) - { - // No-op in simulator - } - } - - public class KelvinRiscV32_ControlBlock : - IDoubleWordPeripheral, - IProvidesRegisterCollection<DoubleWordRegisterCollection>, - IKnownSize - { - - public KelvinRiscV32_ControlBlock(Machine machine, - KelvinRiscV32 core, - ulong tcmSize, - ulong tcmRangeStart) - { - Machine = machine; - Core = core; - - this.tcmRangeStart = tcmRangeStart; - this.tcmSize = tcmSize; - - Mmu = InitMmu(tcmRangeStart, tcmSize); - - HostReqIRQ = new GPIO(); - FinishIRQ = new GPIO(); - InstructionFaultIRQ = new GPIO(); - DataFaultIRQ = new GPIO(); - - Core.RegisterControlBlock(this); - - RegistersCollection = new DoubleWordRegisterCollection(this); - DefineRegisters(); - - Core.AddHookOnMmuFault(HandleFault); - - Reset(); - } - - public void Reset() - { - mode = Mode.Freeze | Mode.SwReset; - RegistersCollection.Reset(); - } - - private ExternalMmuBase InitMmu(ulong rangeStart, ulong tcmSize) - { - var mmu = new ExternalMmuBase(this.Core, 1); - - mmu.SetWindowStart(0, 0); - mmu.SetWindowEnd(0, tcmSize); - mmu.SetWindowAddend(0, tcmRangeStart); - mmu.SetWindowPrivileges(0, 7); // Read / write / execute - - return mmu; - } - - private void DefineRegisters() - { - Registers.IntrState.Define32(this) - .WithValueField(0, 4, - writeCallback: (_, value) => - { - this.Log(LogLevel.Noisy, "Got {0} to clear IRQ pending bits", value); - irqsPending = irqsPending & ~(InterruptBits)value; - IrqUpdate(); - }, - valueProviderCallback: (_) => - { - return (uint)irqsPending; - }) - ; - - Registers.IntrEnable.Define32(this) - .WithValueField(0, 4, - writeCallback: (_, value) => - { - this.Log(LogLevel.Noisy, "Got {0} to write IRQ enable bits", value); - irqsEnabled = (InterruptBits)value & InterruptBits.Mask; - IrqUpdate(); - }, - valueProviderCallback: (_) => - { - return (uint)irqsEnabled; - }) - ; - - Registers.IntrTest.Define32(this) - .WithValueField(0, 4, - writeCallback: (_, value) => - { - this.Log(LogLevel.Noisy, "Got {0} to set IRQ pending bits", value); - irqsPending = irqsPending | ((InterruptBits)value & InterruptBits.Mask); - IrqUpdate(); - }) - ; - - Registers.Control.Define32(this, resetValue: 0x00000002) - .WithValueField(0, 24, name: "FREEZE_VC_RESET_PC_START", - writeCallback: (_, val) => - { - Mode newMode = (Mode)val & Mode.Mask; - - // Pause the core when either freeze or swreset is asserted. - if ((mode == Mode.Run) && (newMode != Mode.Run)) - { - this.Log(LogLevel.Noisy, "Pausing core."); - Core.IsHalted = true; - } - - // Trigger the core's reset when SwReset is deasserted. - if (((mode & Mode.SwReset) != 0) && ((newMode & Mode.SwReset) == 0)) - { - this.Log(LogLevel.Noisy, "Resetting core."); - Core.Reset(); - } - - if ((mode & Mode.SwReset) != 0) - { - // Always set the PC on assignment to help with GDB. - ulong startAddress = (val >> (int)Mode.NumBits); - if ((Core.PC != startAddress)) - { - this.Log(LogLevel.Noisy, "Setting PC to 0x{0:X}.", startAddress); - Core.PC = startAddress; - } - } - - // Unpause the core when both freeze and SwReset are deasserted. - if ((mode != Mode.Run) && (newMode == Mode.Run)) - { - this.Log(LogLevel.Noisy, "Resuming core."); - Core.IsHalted = false; - - Core.Resume(); - } - - this.mode = newMode; - }) - .WithIgnoredBits(24, 32 - 24) - ; - - // To-do: Not sure how to implement disablable memory banks. - Registers.MemoryBankControl.Define32(this) - .WithValueField(0, 4, out MemoryEnable, name: "MEM_ENABLE") - .WithIgnoredBits(16, 32 - 16) - ; - - // To-do: Not sure how to implement memory access range checks. - Registers.ErrorStatus.Define32(this) - .WithFlag(0, name: "MEM_OUT_OF_RANGE") - .WithValueField(2, 4, out MemoryDisableAccess, name: "MEM_DISABLE_ACCESS") - .WithIgnoredBits(16, 32 - 16) - ; - - Registers.InitStart.Define32(this) - .WithValueField(0, 22, out InitStartAddress, name: "ADDRESS") - .WithIgnoredBits(24, 32 - 24) - ; - - Registers.InitEnd.Define32(this) - .WithValueField(0, 22, out InitEndAddress, name: "ADDRESS") - .WithFlag(22, name: "VALID", mode: FieldMode.Read | FieldMode.Write, - writeCallback: (_, val) => - { - // If valid, do the memory clear. - if (val) - { - var dataPageMask = ~((ulong)(DataPageSize - 1)); - InitStatusPending.Value = true; - InitStatusDone.Value = false; - Machine.LocalTimeSource.ExecuteInNearestSyncedState( __ => - { - for(ulong writeAddress = InitStartAddress.Value & dataPageMask; - writeAddress < ((InitEndAddress.Value + DataPageSize - 1) & dataPageMask); - writeAddress += DataPageSize) - { - Machine.SystemBus.WriteBytes(DataErasePattern, - (ulong)writeAddress, - (uint)DataPageSize, true); - } - InitStatusPending.Value = false; - InitStatusDone.Value = true; - }); - } - }) - .WithIgnoredBits(23, 32 - 23) - ; - - Registers.InitStatus.Define32(this) - .WithFlag(0, out InitStatusPending, name: "INIT_PENDING") - .WithFlag(1, out InitStatusDone, name: "INIT_DONE") - .WithIgnoredBits(2, 32 - 2) - ; - - } - - public virtual uint ReadDoubleWord(long offset) - { - return RegistersCollection.Read(offset); - } - - public virtual void WriteDoubleWord(long offset, uint value) - { - RegistersCollection.Write(offset, value); - } - - public void ExecMPause() - { - // Pause, reset the core (actual reset occurs when SwReset is cleared) and trigger a host interrupt indicating completion - if (mode == Mode.Run) - { - this.Log(LogLevel.Noisy, "Pausing and resetting core for host completion notification."); - } - else - { - this.Log(LogLevel.Error, "Pausing and resetting core for host completion notification, but core was not expected to be running. Did you clear IsHalted manually?"); - } - Core.IsHalted = true; - mode = Mode.Freeze | Mode.SwReset; - irqsPending |= InterruptBits.Finish; - IrqUpdate(); - } - - public void ExecEBreak() - { - // Pause and trigger a host interrupt indicating completion with fault - if (mode == Mode.Run) - { - this.Log(LogLevel.Noisy, "Core executed ebreak."); - } - else - { - this.Log(LogLevel.Error, "Core executed ebreak, but core was not expected to be running. Did you clear IsHalted manually?"); - } - Core.IsHalted = true; - mode = Mode.Freeze; - irqsPending |= InterruptBits.Finish | InterruptBits.InstructionFault; - IrqUpdate(); - } - - public DoubleWordRegisterCollection RegistersCollection { get; private set; } - - - private void HandleFault(ulong faultAddress, AccessType accessType, int windowIndex) - { - LogFaultType(Mmu, faultAddress, accessType); - ExecEBreak(); - } - - private void LogFaultType(ExternalMmuBase mmu, ulong faultAddress, AccessType accessType) - { - var mmuName = mmu.GetType().Name; - var virtualWindowIndex = (uint)(faultAddress / tcmSize); - - if(virtualWindowIndex >= 1) - { - this.Log(LogLevel.Error, "{0}: Translation request for {1} at 0x{2:X}: failure, no window at address", mmuName, accessType, faultAddress); - } - else - { - var windowEnd = mmu.GetWindowEnd(virtualWindowIndex); - var windowPrivilege = mmu.GetWindowPrivileges(virtualWindowIndex); - - if(faultAddress > windowEnd) - { - this.Log(LogLevel.Error, "{0}: Translation request for {1} at 0x{2:X}: failure on window {3}, out of range, window ends at 0x{4:X}", - mmuName, accessType, faultAddress, virtualWindowIndex, windowEnd); - } - else if((windowPrivilege & (uint)accessType) == 0) - { - this.Log(LogLevel.Error, "{0}: Translation request for {1} at 0x{2:X}: failure on window {3}, no permission, window permissions are 0x{4:X}", - mmuName, accessType, faultAddress, virtualWindowIndex, windowPrivilege); - } - else - { - this.Log(LogLevel.Error, "{0}: Translation request for {1} at 0x{2:X}: failed for unknown reason. This should not occur", - mmuName, accessType, faultAddress); - } - } - } - - public GPIO HostReqIRQ { get; } - public GPIO FinishIRQ { get; } - public GPIO InstructionFaultIRQ { get; } - public GPIO DataFaultIRQ { get; } - - private InterruptBits irqsEnabled; - private InterruptBits irqsPending; - - private void IrqUpdate() - { - InterruptBits irqsPassed = irqsEnabled & irqsPending; - HostReqIRQ.Set((irqsPassed & InterruptBits.HostReq) != 0); - FinishIRQ.Set((irqsPassed & InterruptBits.Finish) != 0); - InstructionFaultIRQ.Set((irqsPassed & InterruptBits.InstructionFault) != 0); - DataFaultIRQ.Set((irqsPassed & InterruptBits.DataFault) != 0); - } - - // To-do: Set the erase pattern to what the hardware actually does. 0x5A is - // only for debugging purposes. - private const int DataPageSize = 64; - private readonly byte[] DataErasePattern = (byte[])Enumerable.Repeat((byte)0x5A, DataPageSize).ToArray(); - - // Disable unused variable warnings. These warnings will go away on their - // their own when each register's behavior is implemented. -#pragma warning disable 414 - private IValueRegisterField MemoryEnable; - private IValueRegisterField MemoryDisableAccess; - private IValueRegisterField InitStartAddress; - private IValueRegisterField InitEndAddress; - private IFlagRegisterField InitStatusPending; - private IFlagRegisterField InitStatusDone; -#pragma warning restore 414 - - private Mode mode; - private readonly Machine Machine; - private readonly KelvinRiscV32 Core; - private readonly ExternalMmuBase Mmu; - private readonly ulong tcmSize; - private readonly ulong tcmRangeStart; - - // Length of register space. - public long Size => 0x1000; - private enum Registers - { - IntrState = 0x00, - IntrEnable = 0x04, - IntrTest = 0x08, - Control = 0x0C, - MemoryBankControl = 0x10, - ErrorStatus = 0x14, - InitStart = 0x18, - InitEnd = 0x1C, - InitStatus = 0x20, - }; - [Flags] - private enum Mode - { - Run = 0x00, - Freeze = 0x01, - SwReset = 0x02, - Mask = 0x03, - NumBits = 2, - }; - [Flags] - private enum InterruptBits - { - HostReq = 1, - Finish = 2, - InstructionFault = 4, - DataFault = 8, - Mask = 15, - }; - } - -}
diff --git a/shodan_infrastructure/Mailbox.cs b/shodan_infrastructure/Mailbox.cs index 4e74358..a63cfab 100644 --- a/shodan_infrastructure/Mailbox.cs +++ b/shodan_infrastructure/Mailbox.cs
@@ -1,3 +1,17 @@ +// Copyright 2023 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + using Antmicro.Renode.Core; using Antmicro.Renode.Logging; using Antmicro.Renode.Peripherals.Bus;
diff --git a/shodan_infrastructure/MatchaI2S.cs b/shodan_infrastructure/MatchaI2S.cs index 56def9d..292f659 100644 --- a/shodan_infrastructure/MatchaI2S.cs +++ b/shodan_infrastructure/MatchaI2S.cs
@@ -1,9 +1,18 @@ // -// Copyright (c) 2010-2023 Google +// Copyright (c) 2023 Google LLC // -// This file is licensed under the MIT License. -// Full license text is available in 'licenses/MIT.txt'. +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at // +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + using System; using System.Collections.Generic; using System.Collections.ObjectModel;
diff --git a/shodan_infrastructure/NetUart.cs b/shodan_infrastructure/NetUart.cs deleted file mode 100644 index d557345..0000000 --- a/shodan_infrastructure/NetUart.cs +++ /dev/null
@@ -1,115 +0,0 @@ -// -// Copyright (c) 2021 Google LLC -// -// This file is licensed under the MIT License. -// Full license text is available in 'licenses/MIT.txt'. -// -using Antmicro.Renode.Core; -using Antmicro.Renode.Logging; -using Antmicro.Renode.Peripherals.Bus; - -using System; -using System.IO; -using System.Net; -using System.Net.Sockets; -using System.Threading; -using System.Collections.Concurrent; - -// This is a very simple Renode periperal that provides a byte-oriented -// communication port to the simulated SOC that's backed by a network port on -// the host workstation. The port is intended for debugging only - it has no -// real flow control, no interrupts, no error checking - but it should be around -// 5x faster than using a real UART model to communicate with your SOC. -// -// Add this to your SOC .repl file: -// -// net_uart: NetUart @ sysbus <base_address> -// name: "NetUart" -// port: <network_port> -// -// Communicate with the port in your firmware like this: -// -// struct NetUart { -// uint32_t avail; -// uint32_t read; -// uint32_t write; -// }; -// volatile NetUart* net_uart = reinterpret_cast<NetUart*>(base_address); -// -// uint8_t get_byte() { -// while (!net_uart->avail) {} -// return net_uart->read; -// }; -// -// void set_byte(uint8_t b) { -// net_uart->write = b; -// }; -// -// And then you can run "telnet localhost <network_port>" on your workstation to -// communicate with your SOC. -namespace Antmicro.Renode.Peripherals -{ - public class NetUart : IDoubleWordPeripheral, IKnownSize - { - public long Size => 0x12; - - TcpListener listener = null; - Socket client = null; - byte[] buffer = null; - Thread accept_thread; - string name; - - public NetUart(string name, int port) { - this.name = name; - - listener = new TcpListener(port); - listener.Start(); - - this.Log(LogLevel.Info, "NetUart '{0}' starting at {1}", name, listener.LocalEndpoint); - - buffer = new byte[4096]; - accept_thread = new Thread(Accept); - accept_thread.Start(); - } - - public void Accept() { - while(true) { - Socket new_client = listener.AcceptSocket(); - this.Log(LogLevel.Info, "NetUart '{0}' got connection from {1}", name, new_client.RemoteEndPoint); - lock (this) { - client = new_client; - } - } - } - - public void Reset() { - } - - public uint ReadDoubleWord(long offset) { - lock(this) { - if (client == null) { - return 0; - } - else if (offset == 0) { - return (uint)client.Available; - } - else if (offset == 4 && client.Available > 0) { - client.Receive(buffer, 1, 0); - return buffer[0]; - } - else { - return 0; - } - } - } - - public void WriteDoubleWord(long offset, uint value) { - lock(this) { - if (client != null && offset == 8) { - buffer[0] = (byte)value; - client.Send(buffer, 1, 0); - } - } - } - } -}
diff --git a/shodan_infrastructure/SmcRiscV32.cs b/shodan_infrastructure/SmcRiscV32.cs index 9e7c8b1..c62c68d 100644 --- a/shodan_infrastructure/SmcRiscV32.cs +++ b/shodan_infrastructure/SmcRiscV32.cs
@@ -1,9 +1,18 @@ // -// Copyright (c) 2021 Google LLC +// Copyright (c) 2023 Google LLC // -// This file is licensed under the MIT License. -// Full license text is available in 'licenses/MIT.txt'. +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at // +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + using Antmicro.Renode.Core; using Antmicro.Renode.Logging; using Antmicro.Renode.Peripherals.Bus;
diff --git a/shodan_infrastructure/SpringbokRiscV32.cs b/shodan_infrastructure/SpringbokRiscV32.cs index 2deebde..7687ea0 100644 --- a/shodan_infrastructure/SpringbokRiscV32.cs +++ b/shodan_infrastructure/SpringbokRiscV32.cs
@@ -1,9 +1,18 @@ // -// Copyright (c) 2021 Google LLC +// Copyright (c) 2023 Google LLC // -// This file is licensed under the MIT License. -// Full license text is available in 'licenses/MIT.txt'. +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at // +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + using System; using System.Linq; using System.Text;