| // *************************************************** | |
| // Vector | |
| // *************************************************** | |
| cpu2: CPU.SpringbokRiscV32 @ sysbus | |
| hartId: 2 | |
| // TODO(b/214092253): IMEM size blow-up needs to be addressed. | |
| //RAM_VEC_IMEM [‘h3200_0000 - ‘h320F_FFFF) 1MB RAM for Vector core Instruction | |
| // Remember to update hart_is_vc in rom_crt.S if this changes. | |
| ram_vec_imem: Memory.MappedMemory @ sysbus 0x32000000 | |
| size: 0x00100000 | |
| // TODO(b/196910893): Revert the temporary change on DMEM memory later | |
| //RAM_VEC_DMEM [‘h3400_0000 - ‘h34FF_FFFF) 16MB RAM for Vector core Data | |
| ram_vec_dmem: Memory.MappedMemory @ sysbus 0x34000000 | |
| size: 0x01000000 | |
| //RAM_VEC_CSR [‘h3800_0000 - ‘h3800_0FFF) 4KB RAM for SMC core data storage | |
| ram_vec_csr: Memory.MappedMemory @ sysbus 0x38000000 | |
| size: 0x00001000 | |
| // TODO(jonathantate): The addresses for these WindowMMUs are not final while we | |
| // figure out how to have different memory maps for vector core / SMC with | |
| // Renode. From the vector core's point of view, the WindowMMUs should be at | |
| // 0x30000000/0x34000000 for IMMU/DMMU respectively, but from the SMC's point of | |
| // view that should be where the instruction/data TCMs are. | |
| vec_immu : CPU.SpringbokRiscV32_WindowMMU @ sysbus 0x33000000 | |
| tcm: ram_vec_imem | |
| windowSize: 0x10000 | |
| tcmSize: 0x10000 | |
| pageSize: 0x400 | |
| numWindows: 2 | |
| vec_dmmu : CPU.SpringbokRiscV32_WindowMMU @ sysbus 0x35000000 | |
| tcm: ram_vec_dmem | |
| windowSize: 0x400000 | |
| tcmSize: 0x400000 | |
| pageSize: 0x400 | |
| numWindows: 4 | |
| vec_controlblock : CPU.SpringbokRiscV32_ControlBlock @ sysbus 0x47000000 | |
| core: cpu2 | |
| imem: ram_vec_imem | |
| dmem: ram_vec_dmem | |
| immu: vec_immu | |
| dmmu: vec_dmmu |