Initial bancha support. Bancha is reduction of sencha by combining the SEC+SMC and pruning some peripherals. Kelvin remains unchanged. Bypass-Presubmit-Reason: verified as part of topic Change-Id: I69cc78b502033eba3b02d69f19606b6533d4b7a6
diff --git a/bancha.resc b/bancha.resc new file mode 100644 index 0000000..09e14ad --- /dev/null +++ b/bancha.resc
@@ -0,0 +1,112 @@ +# Copyright 2024 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http:#www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Renode script for testing the 2-core version of the Sencha platform + +$name?="bancha" + +using sysbus +mach create $name + +include @sim/config/shodan_infrastructure/MpactCPU.cs +EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.MpactCPU.MpactBaseCPU" +EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.MpactCPU.MpactPeripheral" +include @sim/config/shodan_infrastructure/MpactCheriotCPU.cs +EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.MpactCPU.MpactCheriotCPU" +EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.RiscV32" +include @sim/config/shodan_infrastructure/KelvinCPU.cs +EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.KelvinCPU" +EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.MlTopControlBlock" +#include @sim/config/shodan_infrastructure/SmcCheriotCPU.cs +#include @sim/config/shodan_infrastructure/Mailbox.cs +include @sim/config/shodan_infrastructure/AddressRangeStub.cs +include @sim/config/shodan_infrastructure/MatchaI2S.cs +EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.Sound.MatchaI2S" + +$repl_file ?= @sim/config/platforms/bancha.repl + +machine LoadPlatformDescription $repl_file + +$term_port?=3456 +emulation CreateServerSocketTerminal $term_port "term" false +connector Connect uart5 term + +showAnalyzer "uart0-analyzer" sysbus.uart0 Antmicro.Renode.Analyzers.LoggingUartAnalyzer +showAnalyzer "uart5-analyzer" sysbus.uart5 Antmicro.Renode.Analyzers.LoggingUartAnalyzer + +# Set the uarts host/virt timestamp format. Options: None, Virtual, Host, Full. +uart0-analyzer TimestampFormat None +uart5-analyzer TimestampFormat None + +cpu0 IsHalted true +$cheriotLibrary ?= @out/cheriot/sim/librenode_mpact_cheriot.so +sysbus.cpu0 CpuLibraryPath $cheriotLibrary + +# Load the boot rom into the 32k rom at 0x8000 (useVirtualAddress = false, allowLoadsOnlyToMemory = false) +# Unlike the OT boot rom where cpu0 starts at the reset vecitor (@0x8080) +# the PC is initialized to the ELF entry point. +sysbus LoadELF @out/cheriot/bancha/boot_rom.elf false false cpu0 + +# Override cli_port to enable the command line interface on the specified port. +$cli_port?= 0 +$wait_for_cli ?= false +sysbus.cpu0 CLIPort $cli_port +sysbus.cpu0 WaitForCLI $wait_for_cli + +$tar ?= @out/cheriot/bancha/release/ext_flash.tar +$spi_flash_load_address ?= 0x44000000 +$sc_bin ?= @out/cheriot/bancha/release/tmp/cheriot-firmware.bin +$eflash_address ?= 0x20000000 +sysbus LoadBinary $sc_bin $eflash_address +sysbus LoadBinary $tar $spi_flash_load_address +#sysbus LoadSymbolsFrom $cheriot_elf + +# If we have a I2S peripheral, setup an audio file that we can use +# for sampling data. Note that the format for these files is raw +# sample data, left channel followed by right. +$i2s_mic_audio_file ?= @sim/config/shodan_infrastructure/test.raw +$i2s_speaker_audio_file ?= @/tmp/speaker.raw + +# Uncomment these lines to enable audio +i2s0 InputFile $i2s_mic_audio_file +#i2s0 OutputFile $i2s_speaker_audio_file + +$kelvinLibrary ?= @out/kelvin/sim/librenode_kelvin.so +sysbus.cpu2 CpuLibraryPath $kelvinLibrary +# Start the vector core at address 0 of its instruction TCM. +sysbus.cpu2 PC 0x80000000 +# Set the vector core to be less interactive to IO for faster execution +$vector_core_mips ?= 1000 +sysbus.cpu2 PerformanceInMips $vector_core_mips + +# TOOD: enable for soundstream until model is properly packaged +#$kelvin_bin?=@out/cheriot/sim/kelvin.bin +#sysbus LoadBinary $kelvin_bin 0x5A000000 + +# Start GDB and halt both cores so we can connect GDB before the bootrom has +# started. +# cpu2 does not support GDB. Please follow docs/KelvinIssDebugging.md to debug +# Kelvin programs. +$gdb_port?=3333 +#machine StartGdbServer $gdb_port false cpu0 + +cpu0 IsHalted true +cpu2 IsHalted true + +# Enable for instruction & memory profiling. Data are written to +# $ROOTDIR/cache/renode/mpact_cheriot_renode* (to be fixed). +cpu0 SymbolFile @out/cheriot/bancha/boot_rom.elf +#cpu0 SymbolFile $cheriot_elf +#cpu0 InstProfile true +#cpu0 MemProfile true
diff --git a/platforms/bancha.repl b/platforms/bancha.repl new file mode 100644 index 0000000..bc5e5e3 --- /dev/null +++ b/platforms/bancha.repl
@@ -0,0 +1,429 @@ +// +// Copyright (c) 2024 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Bancha is derived from Sencha by combining the SEC+SMC +// and pruning some peripherals. Kelvin remains unchanged. + +// NB: beware the OpenTitan boot_rom has the memory configuration built-in +// NB: uart5 is a temporary hack until we switch the cheriot-rtos firmware +// to support OpenTitanUart + +using "sim/config/platforms/kelvin.repl" + +cpu0: MpactCPU.MpactCheriotCPU @ sysbus + id: 1 + cpuType: "Mpact.Cheriot" + endianness: Endianess.LittleEndian + memoryBase: 0x10000000 + memorySize: 0x400000 + revocationMemoryBase: 0x10370000 + +// TODO(sleffler): trim memory config +ram_smc : MpactCPU.MpactPeripheral @ sysbus 0x10000000 + size: 0x400000 + baseAddress: 0x10000000 + mpactCpu: cpu0 + +// XXX temp 'cuz default uart in cheriot-rtos is not OT +uart5: Antmicro.Renode.Peripherals.UART.TrivialUart @ sysbus 0x54000000 + +// RAM_RET [‘h4060_0000 - ‘h4060_0FFF) 4KB RAM for debug/retention +ram_ret_aon: Memory.MappedMemory @ sysbus 0x40600000 + size: 0x1000 + +// ROM [‘h0000_8000 - ‘h0000_FFFF) 32KB ROM for Security core secure boot code storage +// XXX temporarily bump to 48K for bloat/hacks +rom: Memory.MappedMemory @ sysbus 0x00008000 + size: 0x0000b000 + +// eFLASH [‘h2000_0000 - ‘h200F_FFFF) 1MB eFlash for Security Core +eflash: Memory.MappedMemory @ sysbus 0x20000000 + size: 0x100000 + +// UART0 [‘h4000_0000 - ‘h4000_0FFF) 4KB UART0 for Security Core +uart0: UART.OpenTitan_UART @ sysbus 0x40000000 + TxWatermarkIRQ -> plic@1 + RxWatermarkIRQ -> plic@2 + TxEmptyIRQ -> plic@3 + RxOverflowIRQ -> plic@4 + RxFrameErrorIRQ -> plic@5 + RxBreakErrorIRQ -> plic@6 + RxTimeoutIRQ -> plic@7 + RxParityErrorIRQ -> plic@8 + FatalAlert -> alert_handler@0 + +// UART1 [‘h4001_0000 - ‘h4001_0FFF) 4KB UART1 (Reserved) +uart1: UART.OpenTitan_UART @ sysbus 0x40010000 + TxWatermarkIRQ -> plic@9 + RxWatermarkIRQ -> plic@10 + TxEmptyIRQ -> plic@11 + RxOverflowIRQ -> plic@12 + RxFrameErrorIRQ -> plic@13 + RxBreakErrorIRQ -> plic@14 + RxTimeoutIRQ -> plic@15 + RxParityErrorIRQ -> plic@16 + FatalAlert -> alert_handler@1 + +// UART2 [‘h4002_0000 - ‘h4002_0FFF) 4KB UART2 for Vector Core +uart2: UART.OpenTitan_UART @ sysbus 0x40020000 + TxWatermarkIRQ -> plic@17 + RxWatermarkIRQ -> plic@18 + TxEmptyIRQ -> plic@19 + RxOverflowIRQ -> plic@20 + RxFrameErrorIRQ -> plic@21 + RxBreakErrorIRQ -> plic@22 + RxTimeoutIRQ -> plic@23 + RxParityErrorIRQ -> plic@24 + FatalAlert -> alert_handler@2 + +// UART3 [‘h4003_0000 - ‘h4003_0FFF) 4KB UART3 (Reserved) +uart3: UART.OpenTitan_UART @ sysbus 0x40030000 + TxWatermarkIRQ -> plic@25 + RxWatermarkIRQ -> plic@26 + TxEmptyIRQ -> plic@27 + RxOverflowIRQ -> plic@28 + RxFrameErrorIRQ -> plic@29 + RxBreakErrorIRQ -> plic@30 + RxTimeoutIRQ -> plic@31 + RxParityErrorIRQ -> plic@32 + FatalAlert -> alert_handler@3 + +// GPIO [‘h4004_0000 - ‘h4004_0FFF) 4KB GPIO +gpio: GPIOPort.OpenTitan_GPIO @ sysbus 0x40040000 + IRQ -> plic@33 + FatalAlert -> alert_handler@4 + +// SPI_DEVICE [‘h4005_0000 - ‘h4005_1FFF) 8KB SPI Device +spi_device: SPI.OpenTitan_SpiDevice @ sysbus 0x40050000 + FatalAlert -> alert_handler@5 + +// SPI_HOST0 [‘h4006_0000 - ‘h4006_0FFF) 4KB SPI HOST 0 +spi_host0: SPI.OpenTitan_SpiHost@ sysbus 0x40300000 + FatalAlert -> alert_handler@19 + Error -> plic@131 + SpiEvent -> plic@132 + numberOfCSLines: 32 + +extflash: SPI.Micron_MT25Q @ spi_host0 0 + underlyingMemory: extflash_mem + +// SPI_HOST1 [‘h4007_0000 - ‘h4007_0FFF) 4KB SPI HOST 1 +spi_host1: SPI.OpenTitan_SpiHost@ sysbus 0x40310000 + FatalAlert -> alert_handler@20 + Error -> plic@133 + SpiEvent -> plic@134 + numberOfCSLines: 32 + +// I2C0 [‘h4008_0000 - ‘h4008_0FFF) 4KB I2C0 +i2c0: I2C.OpenTitan_I2C @ sysbus 0x40080000 + FatalAlert -> alert_handler@6 + +// I2C1 [‘h4009_0000 - ‘h4009_0FFF) 4KB I2C1 +i2c1: I2C.OpenTitan_I2C @ sysbus 0x40090000 + FatalAlert -> alert_handler@7 + +// I2C2 [‘h400A_0000 - ‘h400A_0FFF) 4KB I2C2 +i2c2: I2C.OpenTitan_I2C @ sysbus 0x400A0000 + FatalAlert -> alert_handler@8 + +// PATGEN [‘h400E_0000 - ‘h400E_0FFF) 4KB PATGEN + +// RV_TIMER [‘h4010_0000 - ‘h4010_0FFF) 4KB RV Timer for Security Core +timer: Timers.OpenTitan_Timer@ sysbus 0x40100000 + frequency: 24000000 + IRQ -> cpu0@7 + FatalAlert -> alert_handler@10 + +// XXX combine w/ timer or re-think +clint: IRQControllers.CoreLevelInterruptor @ sysbus 0x02000000 + frequency: 2000 + [0, 1] ->cpu0@[3, 7] + +// USBDEV [‘h4011_0000 - ‘h4011_0FFF) 4KB USBDEV +// OTP_CTRL [‘h4013_0000 - ‘h4013_3FFF) 16KB OTP Ctrl +otp_ctrl: Miscellaneous.OpenTitan_OneTimeProgrammableMemoryController @ sysbus 0x40130000 + FatalMacroAlert -> alert_handler@11 + FatalCheckErrorAlert -> alert_handler@12 + FatalBusAlert -> alert_handler@13 + FatalPrimitiveOtpAlert -> alert_handler@14 + RecoverablePrimitiveOtpAlert -> alert_handler@15 + AValuesChain: "8638C62621EC19E8966416165252225F03B9C97821B7B107381030AB3D20AB124694BF85E417495A" + BValuesChain: "E679DF6E77EDDBECDE74B677DFF23AFFC3BFFB79B5FFFD87F930B4FB3F6BFF9A5F97BFD7FCBFE9FF" + CValuesChain: "0C1B73141BA20D421FD124302E8F443DE02C272E2CEEC1138DAD07CBD24A18F583A34D51A42A1E702A7E90F05A81D12E" + DValuesChain: "3E1FFB763FE3CDD61FF97735BEBF5CFDE5BDB7AFAEFEE19B9FBD9FCFD2EF3CF7CFEFFD53A7EE7FF36BFE92FDFA95F9AE" + +// LC_CTRL [‘h4014_0000 - ‘h4014_0FFF) 4KB Life Cycle Ctrl +lc_ctrl: Miscellaneous.OpenTitan_LifeCycleController @ sysbus 0x40140000 + resetManager: rstmgr_aon + otpController: otp_ctrl + FatalProgAlert -> alert_handler@16 + FatalStateAlert -> alert_handler@17 + FatalBusAlert -> alert_handler@18 + DeviceId: "BF5EA92044DAC540CFD1A00105568DFA97D9C35EA0407D71320B5E0434DB637F" + TestExitToken: "000102030405060708090A0B0C0D0E0F" + TestUnlockToken: "79DEF38F41A9B895F6BDF341BEADA9B6" + RMAToken: "4D89B62D287CB957C2500042306DFD57" + +// ALERT_HANDLER [‘h4015_0000 - ‘h4015_0FFF) 4KB Alert Handler Ctrl +alert_handler: Miscellaneous.OpenTitan_AlertHandler @ sysbus 0x40150000 + ClassAInterrupt -> plic@127 + ClassBInterrupt -> plic@128 + ClassCInterrupt -> plic@129 + ClassDInterrupt -> plic@130 + +// PWRMGR_AON [‘h4040_0000 - ‘h4040_0FFF) 4KB Power Manger Control +pwrmgr_aon: Miscellaneous.OpenTitan_PowerManager@ sysbus 0x40400000 + resetManager: rstmgr_aon + FatalAlert -> alert_handler@22 + +// RSTMGR_AON [‘h4041_0000 - ‘h4041_0FFF) 4KB Reset Manger Control +rstmgr_aon: Miscellaneous.OpenTitan_ResetManager @ sysbus 0x40410000 + resetPC: 0x00008084 + FatalAlert -> alert_handler@23 + FatalConsistencyAlert -> alert_handler@24 + init: + MarkAsSkippedOnLifeCycleReset sysbus.rstmgr_aon + MarkAsSkippedOnLifeCycleReset sysbus.pwrmgr_aon + MarkAsSkippedOnSystemReset sysbus.rstmgr_aon + MarkAsSkippedOnSystemReset sysbus.pwrmgr_aon + MarkAsSkippedOnSystemReset sysbus.flash_ctrl + MarkAsSkippedOnLowPowerExitReset sysbus.rstmgr_aon + MarkAsSkippedOnLowPowerExitReset sysbus.pwrmgr_aon + MarkAsSkippedOnLowPowerExitReset sysbus.timer_aon + MarkAsSkippedOnLowPowerExitReset sysbus.ram_ret_aon + +// CLKMGR_AON [‘h4042_0000 - ‘h4042_0FFF) 4KB Clock Manger Control +clock_manager: Miscellaneous.OpenTitan_ClockManager @ sysbus 0x40420000 + otbn: otbn + +// SYSRST ['h4043_0000 - 'h4043_0FFF] 4KB System Reset Control +sysrst_ctrl: Miscellaneous.OpenTitan_SystemResetControl @ sysbus 0x40430000 + resetManager: rstmgr_aon + FatalFault -> alert_handler@27 + +// ADCMGR_AON [‘h4044_0000 - ‘h4044_0FFF) 4KB ADC + +// The OpenTitan bootrom will error out if pinmux registers are locked, +// so we work around that by stubbing out the pinmux range to return +// 0xFFFFFFFF which means "unlocked" + +// PINMUX [‘h4046_0000 - ‘h4046_0FFF) 4KB PINMUX +pinmux_stub : AddressRangeStub @ sysbus 0x40460000 + size: 0x1000 + value: 0xFFFFFFFF + +// AON_TIMER [‘h4047_0000 - ‘h4047_0FFF) 4KB AON_TIMER +timer_aon: Timers.OpenTitan_AonTimer @ sysbus 0x40470000 + powerManager: pwrmgr_aon + resetManager: rstmgr_aon + FatalAlert -> alert_handler@31 + WakeupTimerExpired -> plic@155 + WatchdogTimerBark -> plic@156 + +// AST [‘h4048_0000 - ‘h4048_0FFF) 4KB AST +// SENSOR_CTRL [‘h4049_0000 - ‘h4049_0FFF) 4KB Sensor Ctrl (Details need to be added for mic/cam interface) +// SRAM_CTRL_RET_AON [‘h4050_0000 - ‘h4050_0FFF) 4KB AON RET_SRAM Ctrl + +// Simulated SRAM used to indicate test status to simulator +swteststatus: Miscellaneous.OpenTitan_VerilatorSwTestStatus @ sysbus 0x411f0080 + +// FLASH_CTRL_CORE [‘h4100_0000 - ‘h4100_0FFF) 4KB Flash Control +flash_ctrl: MTD.OpenTitan_FlashController @ sysbus 0x41000000 + flash: eflash + ProgramEmptyIRQ -> plic@159 + ProgramLevelIRQ -> plic@160 + ReadFullIRQ -> plic@161 + ReadLevelIRQ -> plic@162 + OperationDoneIRQ -> plic@163 + CorrectableErrorIRQ -> plic@164 + RecoverableAlert -> alert_handler@35 + FatalStandardAlert -> alert_handler@36 + FatalAlert -> alert_handler@37 + FatalPrimitiveFlashAlert -> alert_handler@38 + RecoverablePrimitiveFlashAlert -> alert_handler@39 + +// RV_PLIC [‘h4800_0000 - ‘h5000_0000) 128MB RV PLIC +// XXX requires OT plic driver? +plic: IRQControllers.OpenTitan_PlatformLevelInterruptController @ sysbus 0x48000000 + // Numbers on the left (0 ->) index PLIC GetGPIOs. + // + // Numbers on the right reference bits in the target MIP. + // Bit 11 corresponds MEIP and bit 9 to SEIP. + 0 -> cpu0@11 + FatalAlert -> alert_handler@41 + numberOfSources: 191 + numberOfContexts: 1 +// prioritiesEnabled: false // XXX + +// AES [‘h4110_0000 - ‘h4110_0FFF) 4KB AES Control +aes: Miscellaneous.OpenTitan_AES @ sysbus 0x41100000 + UpdateErrorAlert -> alert_handler@42 + FatalFaultAlert -> alert_handler@43 + +// HMAC [‘h4111_0000 - ‘h4111_0FFF) 4KB HMAC Control +hmac: Miscellaneous.OpenTitan_HMAC @ sysbus 0x41110000 + FatalAlert -> alert_handler@44 + +// KMAC [‘h4112_0000 - ‘h4112_0FFF) 4KB KMAC Control +kmac: Miscellaneous.OpenTitan_KMAC @ sysbus 0x41120000 + KmacDoneIRQ -> plic@168 + FifoEmptyIRQ -> plic@169 + KmacErrorIRQ -> plic@170 + RecoverableAlert -> alert_handler@45 + FatalAlert -> alert_handler@46 + +// OTBN ['h4113_0000 - 'h4113_FFFF) 64KB OTBN +otbn: Miscellaneous.OpenTitan_BigNumberAccelerator @ sysbus 0x41130000 + DoneIRQ -> plic@171 + FatalAlert -> alert_handler@47 + RecoverableAlert -> alert_handler@48 + +// KEYMGR [‘h4114_0000 - ‘h4114_0FFF) 4KB KEY Manager +keymgr: Miscellaneous.OpenTitan_KeyManager @ sysbus 0x41140000 + aes: aes + kmac: kmac + romController: rom_ctrl + deviceId: "BF5EA92044DAC540CFD1A00105568DFA97D9C35EA0407D71320B5E0434DB637F" + lifeCycleDiversificationConstant: "2F1A43C03DD4FF9B887AB7521CA6CBD8" + creatorKey: "9152E32C9380A4BCC3E0AB263581E6B0E8825186E1E445631646E8BEF8C45D47" + ownerKey: "FA365DF52DA48CD752FB3A026A8E608F0098CFE5FA9810494829D0CD9479EB78" + rootKey: "EFB7EA7EE90093CF4AFFD9AAA2D6C0EC446CFDF5F2D5A0BFD7E2D93EDC63A10256D24A00181DE99E0F690B447A8DDE2A1FFB8BC306707107AA6E2410F15CFC37" + softOutputSeed: "3DAAEF20E285FA658FDD1B426C037151B16C8D444C444F396F4479CB795CF94B" + hardOutputSeed: "9E409D18381BD5D56821E2985E47997105C4900F255574675985B210E1A968E4" + destinationAesSeed: "5E5B35E460FDAF1FF382AB0195E33689D99BCEBF2B79B6839264EDF4DE2B39F3" + destinationKmacSeed: "94059891A38BD1D16C763BBD90347E58152D7FCA9938036525AAA3F89E3DE8F1" + destinationOtbnSeed: "278645E11D7CAC76310205E19CD3F2ED294A279F3C6D0649A905CC9B10A67A16" + destinationNoneSeed: "7A9E0F6E3D591A7FD8C7BA264AF78F28AEE0D28E4D638D95D1806E870336CD96" + revisionSeed: "414C190AD0A09D144FFC0C0FEA081CEF945B641F096B9F3E9A494BA35FCFEF0D" + creatorIdentitySeed: "FB223E8AB704F249EE3FA822276C45E588ED40CF52C8FAE2D054A71149771822" + ownerIntermediateIdentitySeed: "2EC37360E23D4DDA559ADABCF099937FEBBF048FAC328BA1BDEE0CACA987BE4A" + ownerIdentitySeed: "4ABF486B16740B20BC32B13FF07A13FF21CE605E0AC019858F73D707CD0EC1D3" + OperationDoneIRQ -> plic@172 + RecoverableAlert -> alert_handler@49 + FatalAlert -> alert_handler@50 + +// CSRNG [‘h4115_0000 - ‘h4115_0FFF) 4KB CSRNG (Cryptographically Secure Random Number Generator) Control +csrng: Miscellaneous.OpenTitan_CSRNG @ sysbus 0x41150000 + entropySource: entropy_src + RequestCompletedIRQ -> plic@173 + EntropyeRequestedIRQ -> plic@174 + HardwareInstanceIRQ -> plic@175 + FatalErrorIRQ -> plic@176 + RecoverableAlert -> alert_handler@51 + FatalAlert -> alert_handler@52 + +// ENTROPY_SRC [‘h4116_0000 - ‘h4116_0FFF) 4KB ENTROPY SRC control +entropy_src: Miscellaneous.OpenTitan_EntropySource @ sysbus 0x41160000 + RecoverableAlert -> alert_handler@53 + FatalAlert -> alert_handler@54 + EsEntropyValidIRQ -> plic@177 + EsHealthTestFailedIRQ -> plic@178 + EsObserveFifoReadyIRQ -> plic@179 + EsFatalErrIRQ -> plic@180 + +// EDN0 [‘h4117_0000 - ‘h4117_0FFF) 4KB EDN0 +edn0: Miscellaneous.OpenTitan_EntropyDistributionNetwork @ sysbus 0x41170000 + cryptoRandomGenerator: csrng + RecoverableAlert -> alert_handler@55 + FatalAlert -> alert_handler@56 + CommandRequestDone -> plic@181 + FatalError -> plic@182 + +// EDN1 [‘h4118_0000 - ‘h4118_0FFF) 4KB EDN1 +edn1: Miscellaneous.OpenTitan_EntropyDistributionNetwork @ sysbus 0x41180000 + cryptoRandomGenerator: csrng + RecoverableAlert -> alert_handler@57 + FatalAlert -> alert_handler@58 + CommandRequestDone -> plic@183 + FatalError -> plic@184 + +// SRAM_CTRL_MAIN [‘h411C_0000 - ‘h411C_0FFF) 4KB SRAM Control +sram_ctrl: MemoryControllers.OpenTitan_SRAMController @ sysbus 0x411c0000 + FatalError -> alert_handler@59 + +// ROM_CTRL [‘h411E_0000 - ‘h411E_0FFF) 4KB ROM Control +rom_ctrl: MemoryControllers.OpenTitan_ROMController @ sysbus 0x411e0000 + rom: rom + nonce: "D7C90B2B3C3EF8B3" + key: "80C4E835FB113AAD6D7DCA2F2C7D9BF2" + FatalAlert -> alert_handler@60 + +// RV_CORE_IBEX [‘h411F_0000 - ‘h411F_0FFF) 4KB RV Core Ibex + +// Flash/MRAM [‘h4400_0000 - ‘h47FF_FFFF) 64MB External Non-Volatile Memory +extflash_mem: Memory.MappedMemory @ sysbus 0x44000000 + size: 0x04000000 + +// TOP_MATCHA_I2S0_BASE_ADDR @ top_matcha.h +// I2S0 ['h5410_0000 - 'h5410_0040) 64B registers +i2s0 : Sound.MatchaI2S @ sysbus 0x54100000 + TxWatermarkIRQ -> plic@39 // kTopMatchaPlicIrqIdI2s0TxWatermark @ top_matcha.h + RxWatermarkIRQ -> plic@40 // kTopMatchaPlicIrqIdI2s0RxWatermark @ top_matcha.h + TxEmptyIRQ -> plic@41 // kTopMatchaPlicIrqIdI2s0TxEmpty @ top_matcha.h + RxOverflowIRQ -> plic@42 // kTopMatchaPlicIrqIdI2s0RxOverflow @ top_matcha.h + +ml_top_controlblock : + HostReqIRQ -> plic@33 + FinishIRQ -> plic@34 + InstructionFaultIRQ -> plic@35 + +// ISP [‘h4200_0000 - ‘h4200_FFFF) 64KB ISP registers +// DMA Ctrl [‘h4201_0000 - ‘h4201_FFFF) 64KB DMA control interface +// DSP Ctrl [‘h4202_0000 - ‘h4202_FFFF) 64KB Audio DSP control interface + +// Tag memory for debugging +sysbus: + init: + Tag <0x40000000 0x1000> "OPENTITAN_EARLGREY_DEV_UART0" + Tag <0x40010000 0x1000> "OPENTITAN_EARLGREY_DEV_UART1" + Tag <0x40020000 0x1000> "OPENTITAN_EARLGREY_DEV_UART2" + Tag <0x40030000 0x1000> "OPENTITAN_EARLGREY_DEV_UART3" + Tag <0x40040000 0x1000> "OPENTITAN_EARLGREY_DEV_GPIO" + Tag <0x40050000 0x2000> "OPENTITAN_EARLGREY_DEV_SPI_DEVICE" + Tag <0x40060000 0x1000> "OPENTITAN_EARLGREY_DEV_SPI_HOST0" + Tag <0x40070000 0x1000> "OPENTITAN_EARLGREY_DEV_SPI_HOST1" + Tag <0x40080000 0x1000> "OPENTITAN_EARLGREY_DEV_I2C0" + Tag <0x40090000 0x1000> "OPENTITAN_EARLGREY_DEV_I2C1" + Tag <0x400A0000 0x1000> "OPENTITAN_EARLGREY_DEV_I2C2" + Tag <0x400E0000 0x1000> "OPENTITAN_EARLGREY_DEV_PATTGEN" + Tag <0x40100000 0x1000> "OPENTITAN_EARLGREY_DEV_RV_TIMER" + Tag <0x40110000 0x1000> "OPENTITAN_EARLGREY_DEV_USBDEV" + Tag <0x40130000 0x4000> "OPENTITAN_EARLGREY_DEV_OTP_CTRL" + Tag <0x40140000 0x1000> "OPENTITAN_EARLGREY_DEV_LC_CTRL" + Tag <0x40150000 0x1000> "OPENTITAN_EARLGREY_DEV_ALERT_HANDLER" + Tag <0x40400000 0x1000> "OPENTITAN_EARLGREY_DEV_PWRMGR_AON" + Tag <0x40410000 0x1000> "OPENTITAN_EARLGREY_DEV_RSTMGR_AON" + Tag <0x40420000 0x1000> "OPENTITAN_EARLGREY_DEV_CLKMGR_AON" + Tag <0x40440000 0x1000> "OPENTITAN_EARLGREY_DEV_ADC_CTRL_AON" + Tag <0x40460000 0x1000> "OPENTITAN_EARLGREY_DEV_PINMUX_AON" + Tag <0x40470000 0x1000> "OPENTITAN_EARLGREY_DEV_AON_TIMER_AON" + Tag <0x40480000 0x1000> "OPENTITAN_EARLGREY_DEV_AST" + Tag <0x40490000 0x1000> "OPENTITAN_EARLGREY_DEV_SENSOR_CTRL_AON" + Tag <0x40500000 0x1000> "OPENTITAN_EARLGREY_DEV_SRAM_CTRL_RET_AON" + Tag <0x41000000 0x1000> "OPENTITAN_EARLGREY_DEV_FLASH_CTRL" + Tag <0x41200000 0x1000> "OPENTITAN_EARLGREY_DEV_RV_DM" + Tag <0x48000000 0x8000000> "OPENTITAN_EARLGREY_DEV_RV_PLIC" + Tag <0x41100000 0x1000> "OPENTITAN_EARLGREY_DEV_AES" + Tag <0x41110000 0x1000> "OPENTITAN_EARLGREY_DEV_HMAC" + Tag <0x41120000 0x1000> "OPENTITAN_EARLGREY_DEV_KMAC" + Tag <0x41130000 0x10000> "OPENTITAN_EARLGREY_DEV_OTBN" + Tag <0x41140000 0x1000> "OPENTITAN_EARLGREY_DEV_KEYMGR" + Tag <0x41150000 0x1000> "OPENTITAN_EARLGREY_DEV_CSRNG" + Tag <0x41160000 0x1000> "OPENTITAN_EARLGREY_DEV_ENTROPY" + Tag <0x41170000 0x1000> "OPENTITAN_EARLGREY_DEV_EDN0" + Tag <0x41180000 0x1000> "OPENTITAN_EARLGREY_DEV_EDN1" + Tag <0x411C0000 0x1000> "OPENTITAN_EARLGREY_DEV_SRAM_CTRL" + Tag <0x411E0000 0x1000> "OPENTITAN_EARLGREY_DEV_ROM_CTRL" + Tag <0x411F0000 0x1000> "OPENTITAN_EARLGREY_DEV_RV_CORE_IBEX"