Add a renode platform for OpenTitan Earlgrey Change-Id: I6b9ef10a3ee0d387195ee9c2556584710dc6e3a9
diff --git a/opentitan-earlgrey-gen.repl b/opentitan-earlgrey-gen.repl new file mode 100644 index 0000000..26cc637 --- /dev/null +++ b/opentitan-earlgrey-gen.repl
@@ -0,0 +1,211 @@ +// OpenTitan variant Earlgrey + +// CPUs +// Platform has 1 core +// By default the OT design assumes secure core is hart_id == 0 +cpu0: CPU.IbexRiscV32 @ sysbus + hartId: 0 + cpuType: "rv32imac" + timeProvider: empty + allowUnalignedAccesses: true + +// Memory configuration +ram_ret_aon: Memory.MappedMemory @ sysbus 0x40600000 + size: 0x1000 + +eflash: Memory.MappedMemory @ { + sysbus 0x20000000; + sysbus 0x80000000 // virtual translation base + } + size: 0x100000 + +ram_main: Memory.MappedMemory @ sysbus 0x10000000 + size: 0x20000 + +rom: Memory.MappedMemory @ sysbus 0x00008000 + size: 0x8000 + + +// PinMux +// As there is no OpenTitan PinMux support in Renode just configure some memory. +pinmux_aon: Memory.MappedMemory @ sysbus 0x40460000 + size: 0x1000 + + +// GPIOs +gpio: GPIOPort.OpenTitan_GPIO @ sysbus 0x40040000 + + +// Power Manager +pwrmgr_aon: Miscellaneous.OpenTitan_PowerManager @ sysbus 0x40400000 + + +// UARTs +uart0: UART.OpenTitan_UART @ sysbus 0x40000000 + TxWatermarkIRQ -> rv_plic@1 + RxWatermarkIRQ -> rv_plic@2 + TxEmptyIRQ -> rv_plic@3 + RxOverflowIRQ -> rv_plic@4 + RxFrameErrorIRQ -> rv_plic@5 + RxBreakErrorIRQ -> rv_plic@6 + RxTimeoutIRQ -> rv_plic@7 + RxParityErrorIRQ -> rv_plic@8 + +uart1: UART.OpenTitan_UART @ sysbus 0x40010000 + TxWatermarkIRQ -> rv_plic@9 + RxWatermarkIRQ -> rv_plic@10 + TxEmptyIRQ -> rv_plic@11 + RxOverflowIRQ -> rv_plic@12 + RxFrameErrorIRQ -> rv_plic@13 + RxBreakErrorIRQ -> rv_plic@14 + RxTimeoutIRQ -> rv_plic@15 + RxParityErrorIRQ -> rv_plic@16 + +uart2: UART.OpenTitan_UART @ sysbus 0x40020000 + TxWatermarkIRQ -> rv_plic@17 + RxWatermarkIRQ -> rv_plic@18 + TxEmptyIRQ -> rv_plic@19 + RxOverflowIRQ -> rv_plic@20 + RxFrameErrorIRQ -> rv_plic@21 + RxBreakErrorIRQ -> rv_plic@22 + RxTimeoutIRQ -> rv_plic@23 + RxParityErrorIRQ -> rv_plic@24 + +uart3: UART.OpenTitan_UART @ sysbus 0x40030000 + TxWatermarkIRQ -> rv_plic@25 + RxWatermarkIRQ -> rv_plic@26 + TxEmptyIRQ -> rv_plic@27 + RxOverflowIRQ -> rv_plic@28 + RxFrameErrorIRQ -> rv_plic@29 + RxBreakErrorIRQ -> rv_plic@30 + RxTimeoutIRQ -> rv_plic@31 + RxParityErrorIRQ -> rv_plic@32 + + +// HMAC +hmac: Miscellaneous.OpenTitan_HMAC @ sysbus 0x41110000 + + +// Flash Controller +flash_ctrl: MTD.OpenTitan_FlashController @ sysbus 0x41000000 + flash: eflash + ProgramEmptyIRQ -> rv_plic@155 + ProgramLevelIRQ -> rv_plic@156 + ReadFullIRQ -> rv_plic@157 + ReadLevelIRQ -> rv_plic@158 + OperationDoneIRQ -> rv_plic@159 + CorrectableErrorIRQ -> rv_plic@160 + + +// Timers +// TODO(julianmb): The timer interrupt is both connected to the PLIC and the CPU in RTL. Figure out how to do that in renode. +rv_timer: Timers.OpenTitan_Timer @ sysbus 0x40100000 + // MachineTimerInterrupt = 7 + IRQ -> cpu0@7 + +// Simulated SRAM used to indicate test status to simulator +swteststatus: Miscellaneous.OpenTitan_VerilatorSwTestStatus @ sysbus 0x30000000 + +// PLIC +rv_plic: IRQControllers.PlatformLevelInterruptController @ sysbus 0x48000000 + // Bit 11 corresponds MEIP + 0 -> cpu0@11 + numberOfContexts: 1 + numberOfSources: 180 + +// ROM Controller +rom_ctrl: MemoryControllers.OpenTitan_ROMController @ sysbus 0x411e0000 + rom: rom + nonce: 0xfbd120f152a9ef95 + keyHigh: 0x18d5a1fe3b04ff0 + keyLow: 0x9932a2605b23cb7a + +// AES +aes: Miscellaneous.OpenTitan_AES @ sysbus 0x41100000 + +// Key Manager +// TODO(julianmb): deviceId/rootKey/creatorKey/ownerKey. These values need to be retrieved from their origin source. +keymgr: Miscellaneous.OpenTitan_KeyManager @ sysbus 0x41140000 + OperationDoneIRQ -> rv_plic@168 + aes: aes + kmac: kmac + romController: rom_ctrl + deviceId: "0xfa53b8058e157cb69f1f413e87242971b6b52a656a1cab7febf21e5bf1f45edd" + lifeCycleDiversificationConstant: "0x6faf88f22bccd612d1c09f5c02b2c8d1" + creatorKey: "0x9152e32c9380a4bcc3e0ab263581e6b0e8825186e1e445631646e8bef8c45d47" + ownerKey: "0xfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78" + rootKey: "0xefb7ea7ee90093cf4affd9aaa2d6c0ec446cfdf5f2d5a0bfd7e2d93edc63a10256d24a00181de99e0f690b447a8dde2a1ffb8bc306707107aa6e2410f15cfc37" + softOutputSeed: "0x8db302ed56b78538c92ba96fe7ba5d882e53c3844212490ced20e7e16f71067e" + hardOutputSeed: "0xb00fe9a3a2be362bc57ce4588424f90946b441fa5e08b2317fb3e9032db9eddf" + destinationAesSeed: "0xd05781d31c4b4dab379c12b6681950e6d52654489a981b7bdc91865141701fd5" + destinationKmacSeed: "0x1aeca9607328c3621ee7fd88c63032eb50ee437eeda142fce033c343e179c299" + destinationOtbnSeed: "0x45a488652c63c1f68cecf9596cda21a8d5398ced8676e230226a9635bea51c6e" + destinationNoneSeed: "0x4dfb68eaea920c1e6c7b2dc4b639ba1ae564b19dd8235c2f90c064c4849172a2" + revisionSeed: "0xbfafcbebd7c3361357bee83e46164c82a0c86b9c1ef6117215c2e6fcb683d3a9" + creatorIdentitySeed: "0xdf2a87abf7c57a6d06f2e1721e3a5f3b217d62acf1c966c712691421cef76350" + ownerIntermediateIdentitySeed: "0x5910642e0f9946cb60f5f7d233a13b89bfc3162d205b4d60c9b16a8eb0aa75fa" + ownerIdentitySeed: "0x30ac79eec48e320bdcfa32f724f82840fdaced02da0253d803d1cdf325afff8b" + +// KMAC +kmac: Miscellaneous.OpenTitan_KMAC @ sysbus 0x41120000 + KmacDoneIRQ -> rv_plic@164 + FifoEmptyIRQ -> rv_plic@165 + KmacErrorIRQ -> rv_plic@166 + +// Reset Manager +rstmgr_aon: Miscellaneous.OpenTitan_ResetManager @ sysbus 0x40410000 + resetPC: 0x00008084 + init: + MarkAsSkippedOnLifeCycleReset sysbus.rstmgr_aon + MarkAsSkippedOnLifeCycleReset sysbus.pwrmgr_aon + MarkAsSkippedOnSystemReset sysbus.rstmgr_aon + MarkAsSkippedOnSystemReset sysbus.pwrmgr_aon + MarkAsSkippedOnSystemReset sysbus.flash_ctrl + +// Tag memory for debugging +sysbus: + init: + Tag <0x40000000 0x1000> "OPENTITAN_EARLGREY_DEV_UART0" + Tag <0x40010000 0x1000> "OPENTITAN_EARLGREY_DEV_UART1" + Tag <0x40020000 0x1000> "OPENTITAN_EARLGREY_DEV_UART2" + Tag <0x40030000 0x1000> "OPENTITAN_EARLGREY_DEV_UART3" + Tag <0x40040000 0x1000> "OPENTITAN_EARLGREY_DEV_GPIO" + Tag <0x40050000 0x2000> "OPENTITAN_EARLGREY_DEV_SPI_DEVICE" + Tag <0x40060000 0x1000> "OPENTITAN_EARLGREY_DEV_SPI_HOST0" + Tag <0x40070000 0x1000> "OPENTITAN_EARLGREY_DEV_SPI_HOST1" + Tag <0x40080000 0x1000> "OPENTITAN_EARLGREY_DEV_I2C0" + Tag <0x40090000 0x1000> "OPENTITAN_EARLGREY_DEV_I2C1" + Tag <0x400A0000 0x1000> "OPENTITAN_EARLGREY_DEV_I2C2" + Tag <0x400E0000 0x1000> "OPENTITAN_EARLGREY_DEV_PATTGEN" + Tag <0x40100000 0x1000> "OPENTITAN_EARLGREY_DEV_RV_TIMER" + Tag <0x40110000 0x1000> "OPENTITAN_EARLGREY_DEV_USBDEV" + Tag <0x40130000 0x2000> "OPENTITAN_EARLGREY_DEV_OTP_CTRL" + Tag <0x40140000 0x1000> "OPENTITAN_EARLGREY_DEV_LC_CTRL" + Tag <0x40150000 0x1000> "OPENTITAN_EARLGREY_DEV_ALERT_HANDLER" + Tag <0x40400000 0x1000> "OPENTITAN_EARLGREY_DEV_PWRMGR_AON" + Tag <0x40410000 0x1000> "OPENTITAN_EARLGREY_DEV_RSTMGR_AON" + Tag <0x40420000 0x1000> "OPENTITAN_EARLGREY_DEV_CLKMGR_AON" + Tag <0x40430000 0x1000> "OPENTITAN_EARLGREY_DEV_SYSRST_CTRL_AON" + Tag <0x40440000 0x1000> "OPENTITAN_EARLGREY_DEV_ADC_CTRL_AON" + Tag <0x40450000 0x1000> "OPENTITAN_EARLGREY_DEV_PWM_AON" + Tag <0x40460000 0x1000> "OPENTITAN_EARLGREY_DEV_PINMUX_AON" + Tag <0x40470000 0x1000> "OPENTITAN_EARLGREY_DEV_AON_TIMER_AON" + Tag <0x40480000 0x1000> "OPENTITAN_EARLGREY_DEV_AST" + Tag <0x40490000 0x1000> "OPENTITAN_EARLGREY_DEV_SENSOR_CTRL" + Tag <0x40500000 0x1000> "OPENTITAN_EARLGREY_DEV_SRAM_CTRL_RET_AON" + Tag <0x41000000 0x1000> "OPENTITAN_EARLGREY_DEV_FLASH_CTRL" + Tag <0x41200000 0x1000> "OPENTITAN_EARLGREY_DEV_RV_DM" + Tag <0x48000000 0x8000000> "OPENTITAN_EARLGREY_DEV_RV_PLIC" + Tag <0x41100000 0x1000> "OPENTITAN_EARLGREY_DEV_AES" + Tag <0x41110000 0x1000> "OPENTITAN_EARLGREY_DEV_HMAC" + Tag <0x41120000 0x1000> "OPENTITAN_EARLGREY_DEV_KMAC" + Tag <0x41130000 0x10000> "OPENTITAN_EARLGREY_DEV_OTBN" + Tag <0x41140000 0x1000> "OPENTITAN_EARLGREY_DEV_KEYMGR" + Tag <0x41150000 0x1000> "OPENTITAN_EARLGREY_DEV_CSRNG" + Tag <0x41160000 0x1000> "OPENTITAN_EARLGREY_DEV_ENTROPY_SRC" + Tag <0x41170000 0x1000> "OPENTITAN_EARLGREY_DEV_EDN0" + Tag <0x41180000 0x1000> "OPENTITAN_EARLGREY_DEV_EDN1" + Tag <0x411C0000 0x1000> "OPENTITAN_EARLGREY_DEV_SRAM_CTRL_MAIN" + Tag <0x411e0000 0x1000> "OPENTITAN_EARLGREY_DEV_ROM_CTRL" + Tag <0x411F0000 0x1000> "OPENTITAN_EARLGREY_DEV_RV_CORE_IBEX" +