| # Copyright 2022 Google LLC |
| # |
| # Licensed under the Apache License, Version 2.0 (the "License"); |
| # you may not use this file except in compliance with the License. |
| # You may obtain a copy of the License at |
| # |
| # http:#www.apache.org/licenses/LICENSE-2.0 |
| # |
| # Unless required by applicable law or agreed to in writing, software |
| # distributed under the License is distributed on an "AS IS" BASIS, |
| # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| # See the License for the specific language governing permissions and |
| # limitations under the License. |
| |
| # Renode script for testing the Kelvin Vector Core |
| |
| mach create "kelvin" |
| |
| EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.RiscV32" |
| include @sim/config/shodan_infrastructure/KelvinRiscV32.cs |
| EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.KelvinRiscV32" |
| EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.KelvinRiscV32_ControlBlock" |
| $platformfile?=@sim/config/platforms/kelvin.repl |
| |
| machine LoadPlatformDescription $platformfile |
| |
| $bin?=@out/kelvin/sw/bazel_out/hello_world.bin |
| |
| sysbus.cpu2 EnableRiscvOpcodesCounting |
| |
| macro reset |
| """ |
| sysbus LoadBinary $bin 0x5A000000 |
| # Start the vector core at address 0 of its TCM and halt / reset it. |
| sysbus.vec_controlblock WriteDoubleWord 12 3 |
| """ |
| runMacro $reset |
| |
| # Note: GDB doesn't seem to like the way we're setting the program counter in |
| # the vec_controlblock. Breakpoints set to the exact reset address don't seem to |
| # get reliably triggered. We should probably root cause this later when we have |
| # time, but as a workaround setting the breakpoint to reset_addr+4 instead seems |
| # to work fine. |
| |
| # Enable vec_controlblock verbose logging |
| logLevel -1 sysbus.vec_controlblock |
