| // |
| // Copyright (c) 2023 Google LLC |
| // |
| // Licensed under the Apache License, Version 2.0 (the "License"); |
| // you may not use this file except in compliance with the License. |
| // You may obtain a copy of the License at |
| // |
| // https://www.apache.org/licenses/LICENSE-2.0 |
| // |
| // Unless required by applicable law or agreed to in writing, software |
| // distributed under the License is distributed on an "AS IS" BASIS, |
| // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| // See the License for the specific language governing permissions and |
| // limitations under the License. |
| |
| // *************************************************** |
| // Nexus-specific SMC |
| // *************************************************** |
| |
| using "sim/config/platforms/smc.repl" |
| |
| // Remember to update hart_is_mc in rom_crt.S if this changes. |
| ram_smc: @ sysbus 0x50000000 |
| size: 0x00400000 |
| |
| // SMC Specific Peripherals start at 0x54000000 |
| |
| // Control block for the SMC, lets us pause/restart the core at an arbitrary PC. |
| smc_control: @ sysbus 0x54020000 |
| cpu: cpu1 |
| pc: 0x50000000 |
| |
| smc_plic: |
| 0 -> cpu1@9 |
| 1 -> cpu1@11 |
| numberOfSources: 42 |
| |
| uart5: @ sysbus 0x54000000 |
| |
| // RV_TIMER_SMC, timer for Cantrip kernel. |
| timer_smc: @ sysbus 0x54010000 |
| frequency: 2500000 |
| IRQ -> cpu1@5 |
| |
| // Timer for Cantrip software timer service. |
| timer_smc_sw: @ sysbus 0x54011000 |
| frequency: 2500000 |
| IRQ -> smc_plic@38 |
| |
| sysbus: |
| init: |
| Tag <0x54010000 0x1000> "OPENTITAN_EARLGREY_DEV_RV_TIMER_SMC" |
| Tag <0x54030000 0x1000> "OPENTITAN_EARLGREY_DEV_RV_TIMER_SMC_SW" |
| |