sim:config: Fix springbok.resc

Match the resource file syntax after
https://spacebeaker-review.googlesource.com/c/shodan/sim-config/+/21660

Do not enable WMMU in the single-core test framework.

Change-Id: I61ef232454691895853d7d59031086dca52ec526

springbok.resc

diff --git a/springbok.resc b/springbok.resc
index 953141a..85b9881 100644
--- a/springbok.resc
+++ b/springbok.resc
@@ -17,16 +17,16 @@
 mach create "springbok"
 
 EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.RiscV32"
-include @sim/config/shodan_infrastructure/SpringbokRiscV32_WindowMMU.cs
-EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.SpringbokRiscV32_WindowMMU"
 include @sim/config/shodan_infrastructure/SpringbokRiscV32.cs
-
+EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.SpringbokRiscV32"
+EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.SpringbokRiscV32_ControlBlock"
 $platformfile?=@sim/config/platforms/springbok.repl
 
 machine LoadPlatformDescription $platformfile
 
 $bin?=@out/springbok/hello_vec/hello_vec.elf
 
+sysbus.cpu2 EnableExternalWindowMmu false
 sysbus.cpu2 EnableRiscvOpcodesCounting
 
 macro reset