sim: Adjust UART and timer addresses to match hardware

Change-Id: I27cce9b4aa38fa76d38aa9e9a108b6313d56cabd

platforms/nexus.repl

diff --git a/platforms/nexus.repl b/platforms/nexus.repl
index 5a26874..bb1386a 100644
--- a/platforms/nexus.repl
+++ b/platforms/nexus.repl
@@ -1,6 +1,6 @@
-using "sim/config/platforms/smc.repl"
+using "sim/config/platforms/nexus_smc.repl"
 using "sim/config/platforms/secure.repl"
-using "sim/config/platforms/nexus_ml_core.repl"
+using "sim/config/platforms/kelvin.repl"
 
 // To model the TLUL mailbox spec, we need a Renode peripheral that listens
 // to address ranges for both endpoints of the mailbox. This is the current
@@ -27,15 +27,6 @@
     rtirq_B -> smc_plic@11 // kTopMatchaPlicIrqIdMailboxSmcRtirq
     eirq_B  -> smc_plic@12 // kTopMatchaPlicIrqIdMailboxSmcEirq
 
-vec_controlblock : CPU.KelvinRiscV32_ControlBlock @ sysbus 0x5C000000
-    core: cpu2
-    tcmSize:       0x00400000
-    tcmRangeStart: 0x5A000000
-    HostReqIRQ -> smc_plic@13           // kTopMatchaPlicIrqIdVcTopHostReq @ top_matcha.h
-    FinishIRQ -> smc_plic@14            // kTopMatchaPlicIrqIdVcTopFinish @ top_matcha.h
-    InstructionFaultIRQ -> smc_plic@15  // kTopMatchaPlicIrqIdVcTopInstructionFault @ top_matcha.h
-    DataFaultIRQ -> smc_plic@16         // kTopMatchaPlicIrqIdVcTopDataFault @ top_matcha.h
-
 // ISP               [‘h4200_0000 - ‘h4200_FFFF)  64KB ISP registers
 // DMA Ctrl          [‘h4201_0000 - ‘h4201_FFFF)  64KB DMA control interface
 // DSP Ctrl          [‘h4202_0000 - ‘h4202_FFFF)  64KB Audio DSP control interface

platforms/nexus_smc.repl

diff --git a/platforms/nexus_smc.repl b/platforms/nexus_smc.repl
new file mode 100644
index 0000000..3a59e96
--- /dev/null
+++ b/platforms/nexus_smc.repl
@@ -0,0 +1,26 @@
+// ***************************************************
+// Nexus-specific SMC
+// ***************************************************
+
+using "sim/config/platforms/smc.repl"
+
+// Remember to update hart_is_mc in rom_crt.S if this changes.
+ram_smc: @ sysbus 0x50000000
+    size: 0x380000
+
+// SMC Specific Peripherals start at 0x54000000
+
+// Control block for the SMC, lets us pause/restart the core at an arbitrary PC.
+smc_control: @ sysbus 0x54020000
+    cpu: cpu1
+
+uart5: @ sysbus 0x54000000
+
+// RV_TIMER_SMC, timer for Cantrip kernel.
+timer_smc: @ sysbus 0x54010000
+    frequency: 2500000
+
+// Timer for Cantrip software timer service.
+timer_smc_sw: @ sysbus 0x54030000
+    frequency: 2500000
+