sim:config: Add configurable mips control at the springbok core

Can change the springbok core executation speed without affecting the
secure and SMC cores' IO.

Springbok core doen't have much IO communication (UART) so it can a
less interactive IO and faster translation process. It is the same
strategy applied by QEMU.

Set the springbok core MIPS default to be 1000 MIPS, 10x faster than the
Renode CPU default.

Change-Id: I63d6f2745b4d7e50ca41bd076b4a83b73c58b59c

shodan.resc

diff --git a/shodan.resc b/shodan.resc
index 78ea9c7..261d801 100644
--- a/shodan.resc
+++ b/shodan.resc
@@ -53,6 +53,9 @@
 
 # Start the vector core at address 0 of its instruction TCM.
 sysbus.cpu2 PC 0x30000000
+# Set the vector core to be less interactive to IO for faster execution
+$vector_core_mips ?= 1000
+sysbus.cpu2 PerformanceInMips $vector_core_mips
 
 # Start GDB and halt both cores so we can connect GDB before the bootrom has
 # started.