Add SPI flash to renode configs
b/299910690
Change-Id: I0b54cac3878a94ed35ef0187201f1c61cbae1dfe
diff --git a/platforms/nexus.repl b/platforms/nexus.repl
index c65e57c..8a33c92 100644
--- a/platforms/nexus.repl
+++ b/platforms/nexus.repl
@@ -50,3 +50,7 @@
HostReqIRQ -> smc_plic@33
FinishIRQ -> smc_plic@34
InstructionFaultIRQ -> smc_plic@35
+
+// Flash/MRAM [‘h4400_0000 - ‘h47FF_FFFF) 64MB External Non-Volatile Memory
+extflash_mem:
+ size: 0x04000000
diff --git a/platforms/nexus_smc.repl b/platforms/nexus_smc.repl
index 307f4ec..6ce590b 100644
--- a/platforms/nexus_smc.repl
+++ b/platforms/nexus_smc.repl
@@ -28,6 +28,7 @@
// Control block for the SMC, lets us pause/restart the core at an arbitrary PC.
smc_control: @ sysbus 0x54020000
cpu: cpu1
+ pc: 0x50000000
smc_plic:
0 -> cpu1@9
diff --git a/platforms/secure.repl b/platforms/secure.repl
index ae1fca7..53103a5 100644
--- a/platforms/secure.repl
+++ b/platforms/secure.repl
@@ -104,6 +104,9 @@
SpiEvent -> plic@132
numberOfCSLines: 32
+extflash: SPI.Micron_MT25Q @ spi_host0 0
+ underlyingMemory: extflash_mem
+
// SPI_HOST1 [‘h4007_0000 - ‘h4007_0FFF) 4KB SPI HOST 1
spi_host1: SPI.OpenTitan_SpiHost@ sysbus 0x40310000
FatalAlert -> alert_handler@20
@@ -340,11 +343,9 @@
// RV_CORE_IBEX [‘h411F_0000 - ‘h411F_0FFF) 4KB RV Core Ibex
-// Flash/MRAM [‘h4400_0000 - ‘h44FF_FFFF) 16MB External Non-Volatile Memory
-// TODO(b/197745020) - temporarily 36M for debug (non-LTO) rust component builds
-// NB: the last 4M are written with the ELF model
-extflash: Memory.MappedMemory @ sysbus 0x44000000
- size: 0x02400000
+// Flash/MRAM [‘h4400_0000 - ‘h45FF_FFFF) 32MB External Non-Volatile Memory
+extflash_mem: Memory.MappedMemory @ sysbus 0x44000000
+ size: 0x02000000
// Tag memory for debugging
sysbus:
diff --git a/platforms/shodan.repl b/platforms/shodan.repl
index b848959..49225c3 100644
--- a/platforms/shodan.repl
+++ b/platforms/shodan.repl
@@ -27,6 +27,9 @@
rtirq_B -> smc_plic@11 // kTopMatchaPlicIrqIdMailboxSmcRtirq
eirq_B -> smc_plic@12 // kTopMatchaPlicIrqIdMailboxSmcEirq
+cpio_mem: Memory.MappedMemory @ sysbus 0x46000000
+ size: 0x01000000
+
vec_controlblock : CPU.SpringbokRiscV32_ControlBlock @ sysbus 0x47000000
core: cpu2
mmuNumWindows: 6 // See: go/shodan-vc-memory
diff --git a/platforms/smc.repl b/platforms/smc.repl
index ce84374..596c563 100644
--- a/platforms/smc.repl
+++ b/platforms/smc.repl
@@ -49,6 +49,7 @@
// Control block for the SMC, lets us pause/restart the core at an arbitrary PC.
smc_control: CPU.SmcRiscV32_ControlBlock @ sysbus 0x54020000
cpu: cpu1
+ pc: 0x28000000
// SMC_PLIC
smc_plic: IRQControllers.PlatformLevelInterruptController @ sysbus 0x60000000 // TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR @ top_matcha.h
diff --git a/shodan_infrastructure/SmcRiscV32.cs b/shodan_infrastructure/SmcRiscV32.cs
index c62c68d..579ecfb 100644
--- a/shodan_infrastructure/SmcRiscV32.cs
+++ b/shodan_infrastructure/SmcRiscV32.cs
@@ -13,6 +13,9 @@
// See the License for the specific language governing permissions and
// limitations under the License.
+using System;
+using System.Collections.Generic;
+using Antmicro.Renode.Core.Structure.Registers;
using Antmicro.Renode.Core;
using Antmicro.Renode.Logging;
using Antmicro.Renode.Peripherals.Bus;
@@ -21,35 +24,56 @@
{
public class SmcRiscV32_ControlBlock : IDoubleWordPeripheral, IKnownSize
{
- public SmcRiscV32_ControlBlock(RiscV32 cpu)
+ public SmcRiscV32_ControlBlock(RiscV32 cpu, long pc)
{
this.cpu = cpu;
+ this.startPC = pc;
+ DefineRegisters();
+ Reset();
}
public void Reset() // IPeripheral
{
}
- public uint ReadDoubleWord(long offset) // IDoubleWordPeripheral
+ public uint ReadDoubleWord(long addr) // IDoubleWordPeripheral
{
- return cpu.PC;
+ return RegistersCollection.Read(addr);
}
- public void WriteDoubleWord(long offset, uint value) // IDoubleWordPeripheral
+ public void WriteDoubleWord(long addr, uint value) // IDoubleWordPeripheral
{
- if (value == 0) {
- this.Log(LogLevel.Noisy, "Stopping SMC");
- cpu.PC = 0;
- cpu.IsHalted = true;
- }
- else {
- this.Log(LogLevel.Noisy, "Starting SMC at 0x{0:X8}", value);
- cpu.PC = value;
- cpu.IsHalted = false;
- }
+ RegistersCollection.Write(addr, value);
}
- public long Size => 0x4;
+ public long Size => 0x8;
private RiscV32 cpu;
+ private long startPC;
+
+ public DoubleWordRegisterCollection RegistersCollection { get; private set; }
+ private void DefineRegisters() {
+ var registerDictionary = new Dictionary<long, DoubleWordRegister>
+ {{(long)Registers.BootEnRegwen, new DoubleWordRegister(this)
+ .WithReservedBits(0, 31)
+ },
+ {(long)Registers.BootEnCtrl, new DoubleWordRegister(this)
+ .WithFlag(0, FieldMode.Write, writeCallback: (_, val) => {
+ if (val) {
+ this.Log(LogLevel.Noisy, "Starting SMC at 0x{0:X}", this.startPC);
+ cpu.PC = this.startPC;
+ cpu.IsHalted = false;
+ } else {
+ this.Log(LogLevel.Noisy, "Stopping SMC");
+ cpu.PC = 0;
+ cpu.IsHalted = true;
+ }
+ })
+ }};
+ RegistersCollection = new DoubleWordRegisterCollection(this, registerDictionary);
+ }
+ public enum Registers {
+ BootEnRegwen = 0x0,
+ BootEnCtrl = 0x4,
+ }
}
}
