| // *************************************************** | |
| // Secure | |
| // *************************************************** | |
| cpu0: CPU.IbexRiscV32 @ sysbus | |
| hartId: 0 | |
| cpuType: "rv32imac" | |
| timeProvider: clint | |
| allowUnalignedAccesses: true | |
| // ORDER EVERY DEVICE BY ADDRESS FOR SANITY | |
| // ROM [‘h0000_8000 - ‘h0000_BFFF) 16KB ROM for Security core secure boot code storage | |
| rom: Memory.MappedMemory @ sysbus 0x00008000 | |
| size: 0x00004000 | |
| // CLINT ['h0200_0000 - 'h0200_0FFF) 4KB CLINT (not in design doc mem map) | |
| clint: IRQControllers.CoreLevelInterruptor @ sysbus 0x02000000 | |
| [0,1] -> cpu0@[3,7] | |
| numberOfTargets: 1 | |
| frequency: 24000000 | |
| // RAM_SEC [‘h1000_0000 - ‘h10FF_FFFF) 16M RAM for Security Core (debugging size) | |
| ram_sec: Memory.MappedMemory @ sysbus 0x10000000 | |
| size: 0x01000000 | |
| // RAM_RET [‘h1800_0000 - ‘h1800_0FFF) 4KB RAM for debug/retention | |
| ram_ret: Memory.MappedMemory @ sysbus 0x18000000 | |
| size: 0x00001000 | |
| // eFLASH [‘h2000_0000 - ‘h20FF_FFFF) 16M eFlash for Security Core (debugging size) | |
| eflash: Memory.MappedMemory @ sysbus 0x20000000 | |
| size: 0x01000000 | |
| // UART0 [‘h4000_0000 - ‘h4000_0FFF) 4KB UART0 for Security Core | |
| uart0: UART.OpenTitan2_UART @ sysbus 0x40000000 | |
| TxWatermarkIRQ -> plic@1 | |
| RxWatermarkIRQ -> plic@2 | |
| TxEmptyIRQ -> plic@3 | |
| RxOverflowIRQ -> plic@4 | |
| RxFrameErrorIRQ -> plic@5 | |
| RxBreakErrorIRQ -> plic@6 | |
| RxTimeoutIRQ -> plic@7 | |
| RxParityErrorIRQ -> plic@8 | |
| // UART1 [‘h4001_0000 - ‘h4001_0FFF) 4KB UART1 (Reserved) | |
| uart1: UART.OpenTitan2_UART @ sysbus 0x40010000 | |
| TxWatermarkIRQ -> plic@9 | |
| RxWatermarkIRQ -> plic@10 | |
| TxEmptyIRQ -> plic@11 | |
| RxOverflowIRQ -> plic@12 | |
| RxFrameErrorIRQ -> plic@13 | |
| RxBreakErrorIRQ -> plic@14 | |
| RxTimeoutIRQ -> plic@15 | |
| RxParityErrorIRQ -> plic@16 | |
| // UART2 [‘h4002_0000 - ‘h4002_0FFF) 4KB UART2 for Vector Core | |
| uart2: UART.OpenTitan2_UART @ sysbus 0x40020000 | |
| TxWatermarkIRQ -> plic@17 | |
| RxWatermarkIRQ -> plic@18 | |
| TxEmptyIRQ -> plic@19 | |
| RxOverflowIRQ -> plic@20 | |
| RxFrameErrorIRQ -> plic@21 | |
| RxBreakErrorIRQ -> plic@22 | |
| RxTimeoutIRQ -> plic@23 | |
| RxParityErrorIRQ -> plic@24 | |
| // UART3 [‘h4003_0000 - ‘h4003_0FFF) 4KB UART3 (Reserved) | |
| uart3: UART.OpenTitan2_UART @ sysbus 0x40030000 | |
| TxWatermarkIRQ -> plic@25 | |
| RxWatermarkIRQ -> plic@26 | |
| TxEmptyIRQ -> plic@27 | |
| RxOverflowIRQ -> plic@28 | |
| RxFrameErrorIRQ -> plic@29 | |
| RxBreakErrorIRQ -> plic@30 | |
| RxTimeoutIRQ -> plic@31 | |
| RxParityErrorIRQ -> plic@32 | |
| // GPIO [‘h4004_0000 - ‘h4004_0FFF) 4KB GPIO | |
| gpio: GPIOPort.OpenTitan_GPIO @ sysbus 0x40040000 | |
| IRQ -> plic@33 | |
| // SPI_Device [‘h4005_0000 - ‘h4005_1FFF) 8KB SPI Device | |
| // SPI_HOST0 [‘h4006_0000 - ‘h4006_0FFF) 4KB SPI HOST 0 | |
| // SPI_HOST1 [‘h4007_0000 - ‘h4007_0FFF) 4KB SPI HOST 1 | |
| // I2C0 [‘h4008_0000 - ‘h4008_0FFF) 4KB I2C0 | |
| // I2C1 [‘h4009_0000 - ‘h4009_0FFF) 4KB I2C1 | |
| // I2C2 [‘h400A_0000 - ‘h400A_0FFF) 4KB I2C2 | |
| // PATGEN [‘h400E_0000 - ‘h400E_0FFF) 4KB PATGEN | |
| // RV_TIMER [‘h4010_0000 - ‘h4010_0FFF) 4KB RV Timer for Security Core | |
| timer: Timers.OpenTitan_Timer@ sysbus 0x40100000 | |
| frequency: 24000000 | |
| -> cpu0@7 | |
| // USBDEV [‘h4011_0000 - ‘h4011_0FFF) 4KB USBDEV | |
| // OTP_CTRL [‘h4013_0000 - ‘h4013_3FFF) 16KB OTP Ctrl | |
| // LC_CTRL [‘h4014_0000 - ‘h4014_0FFF) 4KB Life Cycle Ctrl | |
| // ALERT_HANDLER [‘h4015_0000 - ‘h4015_0FFF) 4KB Alert Handler Ctrl | |
| // PWRMGR_AON [‘h4040_0000 - ‘h4040_0FFF) 4KB Power Manger Control | |
| pwrmgr: Miscellaneous.OpenTitan_PowerManager@ sysbus 0x40400000 | |
| // RSTMGR_AON [‘h4041_0000 - ‘h4041_0FFF) 4KB Reset Manger Control | |
| // CLKMGR_AON [‘h4042_0000 - ‘h4042_0FFF) 4KB Clock Manger Control | |
| // ADCMGR_AON [‘h4044_0000 - ‘h4044_0FFF) 4KB ADC | |
| // PINMUX [‘h4046_0000 - ‘h4046_0FFF) 4KB PINMUX | |
| // AON_TIMER [‘h4047_0000 - ‘h4047_0FFF) 4KB AON_TIMER | |
| // AST [‘h4048_0000 - ‘h4048_0FFF) 4KB AST | |
| // SENSOR_CTRL [‘h4049_0000 - ‘h4049_0FFF) 4KB Sensor Ctrl (Details need to be added for mic/cam interface) | |
| // SRAM_CTRL_RET_AON [‘h4050_0000 - ‘h4050_0FFF) 4KB AON RET_SRAM Ctrl | |
| // bangfei confirms this is the right addr for test reg | |
| swteststatus: Miscellaneous.OpenTitan_VerilatorSwTestStatus @ sysbus 0x40600000 | |
| // FLASH_CTRL [‘h4100_0000 - ‘h4100_0FFF) 4KB Flash Control | |
| // RV_PLIC [‘h4800_0000 - ‘h5000_0000) 128MB RV PLIC | |
| plic: IRQControllers.PlatformLevelInterruptController @ sysbus 0x48000000 | |
| // Numbers on the left (0 ->) index PLIC GetGPIOs. | |
| // | |
| // Numbers on the right reference bits in the target MIP. | |
| // Bit 11 corresponds MEIP and bit 9 to SEIP. | |
| 0 -> cpu0@11 | |
| numberOfSources: 186 | |
| numberOfContexts: 1 | |
| // AES [‘h4110_0000 - ‘h4110_0FFF) 4KB AES Control | |
| // HMAC [‘h4111_0000 - ‘h4111_0FFF) 4KB HMAC Control | |
| // KMAC [‘h4112_0000 - ‘h4112_0FFF) 4KB KMAC Control | |
| // KEYMGR [‘h4113_0000 - ‘h4113_0FFF) 4KB KEY Manager | |
| // CSRNG [‘h4115_0000 - ‘h4115_0FFF) 4KB CSRNG (Cryptographically Secure Random Number Generator) Control | |
| // ENTROPY_SRC [‘h4116_0000 - ‘h4116_0FFF) 4KB ENTROPY SRC control | |
| // EDN0 [‘h4117_0000 - ‘h4117_0FFF) 4KB EDN0 | |
| // EDN1 [‘h4118_0000 - ‘h4118_0FFF) 4KB EDN1 | |
| // SRAM_CTRL_MAIN [‘h411C_0000 - ‘h411C_0FFF) 4KB SRAM Control | |
| // OTBN [‘h411D_0000 - ‘h411D_0FFF) 4KB OTBN | |
| // ISP [‘h4200_0000 - ‘h4200_FFFF) 64KB ISP registers | |
| // DMA Ctrl [‘h4201_0000 - ‘h4201_FFFF) 64KB DMA control interface | |
| // DSP Ctrl [‘h4202_0000 - ‘h4202_FFFF) 64KB Audio DSP control interface | |
| // Flash/MRAM [‘h4400_0000 - ‘h44FF_FFFF) 16MB External Non-Volatile Memory | |
| // TODO(b/197745020) - temporarily 36M for debug (non-LTO) rust component builds | |
| // NB: the last 4M are written with the ELF model | |
| extflash: Memory.MappedMemory @ sysbus 0x44000000 | |
| size: 0x02400000 |