blob: f7715190e15471810fd8ad5dcbf31422587afd62 [file] [log] [blame]
//
// Copyright (c) 2024 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// ***************************************************
// Sencha SMC is a CHERIoT RISC-V CPU
// ***************************************************
cpu1: MpactCPU.MpactCheriotCPU @ sysbus
id: 1
cpuType: "Mpact.Cheriot"
endianness: Endianess.LittleEndian
memoryBase: 0x50000000
// Memory size includes 0x2000 for the shadow memory required for
// the software revoker. This assumes a max of 128KB is configured
// for the heap in the json board description.
memorySize: 0x82000
revocationMemoryBase: 0
// Use the built-in clint to avoid update latency
// NB: beware case, these are properties
// NB: clint irq's are preset
ClintMMRBase: 0x02000000
ClintPeriod: 2000
ram_smc : MpactCPU.MpactPeripheral @ sysbus 0x50000000
size: 0x80000
baseAddress: 0x50000000
mpactCpu: cpu1
smc_plic: IRQControllers.PlatformLevelInterruptController @sysbus 0x60000000
0 -> cpu1@11
numberOfSources: 42
numberOfContexts: 1
prioritiesEnabled: false
// Control block for the SMC, lets us pause/restart the core at an arbitrary PC.
smc_control: MpactCPU.SmcCheriot_ControlBlock @ sysbus 0x54020000
cpu: cpu1
pc: 0x50000000
uart5: UART.OpenTitan_UART @ sysbus 0x54000000
TxWatermarkIRQ -> smc_plic@1
RxWatermarkIRQ -> smc_plic@2
TxEmptyIRQ -> smc_plic@3
RxOverflowIRQ -> smc_plic@4
RxFrameErrorIRQ -> smc_plic@5
RxBreakErrorIRQ -> smc_plic@6
RxTimeoutIRQ -> smc_plic@7
RxParityErrorIRQ -> smc_plic@8