platforms/smc.repl

//
// Copyright (c) 2023 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

// ***************************************************
// SMC
// ***************************************************

// TODO(mattharvey): Switch cpu1 to IbexRiscV32. Currently that causes S-mode
// asynchronous interrupts to overshoot the seL4 trap_entry because, with Ibex,
// Renode "corrects" STVEC:
//
//     [WARNING] cpu1: STVEC value written to CSR corrected from 0xff803000
//     to 0xff803001 because of the selected interrupt mode and privilege
//     architecture
//
// For example, an S-mode external interrupt (9) will then jump immediately to
// 0xff803024, without having reloaded sp from sscratch, causing a page fault
// on the very next instruction.
//
// If Ibex cannot have a Vectored mtvec and a Direct stvec simulaneously, one
// of machine_isr.c (boot ROM) or seL4 stvec setting will have to change to
// match the mode of the other. machine_isr.c is probably the better choice
// because it has been Shodan-specific since its initial revision.
cpu1: CPU.RiscV32 @ sysbus
    hartId: 1
    cpuType: "rv32imac_zicsr_zifencei"
    timeProvider: timer_smc
    allowUnalignedAccesses: true

// TODO(b/197745020) - This currently has to be 64 megs until we get the sel4 kernel + rust components pared down
// Remember to update hart_is_mc in rom_crt.S if this changes.
ram_smc: Memory.MappedMemory @ sysbus 0x28000000
    size: 0x04000000

// SMC Specific Peripherals start at 0x50000000

// Control block for the SMC, lets us pause/restart the core at an arbitrary PC.
smc_control: CPU.SmcRiscV32_ControlBlock @ sysbus 0x54020000
    cpu: cpu1
    pc: 0x28000000

// SMC_PLIC
smc_plic: IRQControllers.PlatformLevelInterruptController @ sysbus 0x60000000 // TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR @ top_matcha.h
    // Numbers on the left (0 ->) index PLIC GetGPIOs.
    //
    // Numbers on the right reference bits in the target MIP.
    // Bit 11 corresponds MEIP and bit 9 to SEIP.
    0 -> cpu1@11
    1 -> cpu1@9
    // Must be kTopMatchaPlicIrqIdLastSmc + 1 from top_matcha.h
    numberOfSources: 43
    numberOfContexts: 2  // MEIP and SEIP

uart5: UART.OpenTitan_UART @ sysbus 0x50000000
    TxWatermarkIRQ -> smc_plic@1
    RxWatermarkIRQ -> smc_plic@2
    TxEmptyIRQ -> smc_plic@3
    RxOverflowIRQ -> smc_plic@4
    RxFrameErrorIRQ -> smc_plic@5
    RxBreakErrorIRQ -> smc_plic@6
    RxTimeoutIRQ -> smc_plic@7
    RxParityErrorIRQ -> smc_plic@8

// RV_TIMER_SMC, timer for Cantrip kernel.
// TODO(hcindyl): Use upstream OpenTitan_Timer model
timer_smc: Timers.OpenTitan_Timer@ sysbus 0x50010000
    frequency: 24000000
    IRQ -> cpu1@5

// Timer for Cantrip software timer service.
// TODO(hcindyl): Use upstream OpenTitan_Timer model
timer_smc_sw: Timers.OpenTitan_Timer@ sysbus 0x50030000
    frequency: 24000000
    IRQ -> smc_plic@31

// I2C host connection to camera
cam_i2c: I2C.OpenTitan_I2C @ sysbus 0x54040000

// I2C device connection to external host
ext_host_i2c: I2C.OpenTitan_I2C @ sysbus 0x54070000

// Tag memory for debugging
sysbus:
    init:
        Tag <0x50010000 0x1000> "OPENTITAN_EARLGREY_DEV_RV_TIMER_SMC"
        Tag <0x50030000 0x1000> "OPENTITAN_EARLGREY_DEV_RV_TIMER_SMC_SW"