| # Copyright 2022 Google LLC | |
| # | |
| # Licensed under the Apache License, Version 2.0 (the "License"); | |
| # you may not use this file except in compliance with the License. | |
| # You may obtain a copy of the License at | |
| # | |
| # http:#www.apache.org/licenses/LICENSE-2.0 | |
| # | |
| # Unless required by applicable law or agreed to in writing, software | |
| # distributed under the License is distributed on an "AS IS" BASIS, | |
| # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | |
| # See the License for the specific language governing permissions and | |
| # limitations under the License. | |
| # Renode script for testing the Springbok Vector Core | |
| mach create "springbok" | |
| EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.RiscV32" | |
| include @sim/config/shodan_infrastructure/SpringbokRiscV32.cs | |
| EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.SpringbokRiscV32" | |
| EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.SpringbokRiscV32_ControlBlock" | |
| $platformfile?=@sim/config/platforms/springbok.repl | |
| machine LoadPlatformDescription $platformfile | |
| $bin?=@out/springbok/hello_vec/hello_vec.elf | |
| sysbus.cpu2 EnableExternalWindowMmu false | |
| sysbus.cpu2 EnableRiscvOpcodesCounting | |
| macro reset | |
| """ | |
| sysbus LoadELF $bin | |
| # Start the vector core at address 0 of its TCM. | |
| sysbus.cpu2 IsHalted true | |
| sysbus.cpu2 PC 0x34000000 | |
| """ | |
| runMacro $reset |