| :name: OpenTitan | |
| :description: This script runs Tock & seL4 on OpenTitan matcha | |
| $name?="matcha" | |
| using sysbus | |
| mach create $name | |
| EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.RiscV32" | |
| include @sim/config/shodan_infrastructure/SpringbokRiscV32_WindowMMU.cs | |
| EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.SpringbokRiscV32_WindowMMU" | |
| include @sim/config/shodan_infrastructure/SpringbokRiscV32.cs | |
| include @sim/config/shodan_infrastructure/SmcRiscV32.cs | |
| include @sim/config/shodan_infrastructure/OpenTitan2_UART.cs | |
| include @sim/config/shodan_infrastructure/Mailbox.cs | |
| machine LoadPlatformDescription @sim/config/platforms/shodan.repl | |
| $term_port?="/tmp/term" | |
| emulation CreateUartPtyTerminal "term" $term_port true | |
| connector Connect uart5 term | |
| # for a client, bash users may consider this inline script: | |
| # | |
| # stty sane -echo -icanon; socat - /tmp/term,raw; stty sane | |
| # | |
| # tmux users may consider adding a binding to ~/.tmux.conf | |
| # | |
| # bind-key k split-window "stty -echo -icanon; socat - /tmp/term,raw" | |
| # Hook up the analyzers to the uarts so we can see their output in the main | |
| # Renode log | |
| showAnalyzer "uart0-analyzer" sysbus.uart0 Antmicro.Renode.Analyzers.LoggingUartAnalyzer | |
| showAnalyzer "uart5-analyzer" sysbus.uart5 Antmicro.Renode.Analyzers.LoggingUartAnalyzer | |
| # Set the uarts host/virt timestamp format. Options: None, Virtual, Host, Full. | |
| uart0-analyzer TimestampFormat None | |
| uart5-analyzer TimestampFormat None | |
| # Load the bootrom into the 16k rom at 0x8000 | |
| sysbus LoadELF @out/shodan_boot_rom/build-out/multihart_boot_rom/multihart_boot_rom_sim_verilator.elf | |
| # Load the system software tar and model ELF into external flash | |
| $tar ?= @out/ext_flash_release.tar | |
| sysbus LoadBinary $tar 0x44000000 | |
| sysbus LoadBinary @out/springbok_iree/samples/quant_model/person_detection_emitc_static 0x46000000 | |
| # Start both cores at the bootrom entry point. | |
| sysbus.cpu0 PC 0x8090 | |
| sysbus.cpu1 PC 0x8090 | |
| # Start the vector core at address 0 of its instruction TCM. | |
| sysbus.cpu2 PC 0x30000000 | |
| # Start GDB and halt both cores so we can connect GDB before the bootrom has | |
| # started. | |
| $gdb_port?=3333 | |
| machine StartGdbServer $gdb_port false cpu0 | |
| machine StartGdbServer $gdb_port false cpu1 | |
| cpu0 IsHalted true | |
| cpu1 IsHalted true | |
| cpu2 IsHalted true |