sim:config: Update secure and vector cores' memory map to match HW defs

Move swteststatus back to 0x3000_0000 to match top_matcha.hjson
Move vector core itcm to 0x3200_0000 to match
https://spacebeaker.git.corp.google.com/shodan/3p/lowrisc/opentitan/+/3d05e14abb23e275f68080b59c21e3d949176605/hw/top_matcha/data/top_matcha.hjson#749

Enable ram_ret_aon at 0x4060_0000

Change-Id: I150caa760ebe6abf6c9132ddaa7df2e48ef24eff

platforms/secure.repl

diff --git a/platforms/secure.repl b/platforms/secure.repl
index 1c548dd..7c0be01 100644
--- a/platforms/secure.repl
+++ b/platforms/secure.repl
@@ -25,8 +25,8 @@
     size: 0x01000000
 
 // RAM_RET           [‘h4060_0000 - ‘h4060_0FFF)   4KB RAM for debug/retention
-// ram_ret_aon: Memory.MappedMemory @ sysbus 0x40600000
-//    size: 0x1000
+ram_ret_aon: Memory.MappedMemory @ sysbus 0x40600000
+    size: 0x1000
 
 // eFLASH            [‘h2000_0000 - ‘h20FF_FFFF)  16M eFlash for Security Core (debugging size)
 eflash: Memory.MappedMemory @ sysbus 0x20000000
@@ -111,9 +111,7 @@
 // SRAM_CTRL_RET_AON [‘h4050_0000 - ‘h4050_0FFF)   4KB AON RET_SRAM Ctrl
 
 // Simulated SRAM used to indicate test status to simulator
-// Moved from the 0x30000000 defined in hw/top_matcha/dv/verilator/chip_sim.core
-// as it collides with Springbok TCM location
-swteststatus: Miscellaneous.OpenTitan_VerilatorSwTestStatus @ sysbus 0x40600000
+swteststatus: Miscellaneous.OpenTitan_VerilatorSwTestStatus @ sysbus 0x30000000
 
 // FLASH_CTRL        [‘h4100_0000 - ‘h4100_0FFF)   4KB Flash Control
 

platforms/vector.repl

diff --git a/platforms/vector.repl b/platforms/vector.repl
index 349dd8e..cd43ab8 100644
--- a/platforms/vector.repl
+++ b/platforms/vector.repl
@@ -6,9 +6,9 @@
     hartId: 2
 
 // TODO(b/214092253): IMEM size blow-up needs to be addressed.
-//RAM_VEC_IMEM      [‘h3000_0000 - ‘h300F_FFFF) 1MB RAM for Vector core Instruction
+//RAM_VEC_IMEM      [‘h3200_0000 - ‘h320F_FFFF) 1MB RAM for Vector core Instruction
 // Remember to update hart_is_vc in rom_crt.S if this changes.
-ram_vec_imem: Memory.MappedMemory @ sysbus 0x30000000
+ram_vec_imem: Memory.MappedMemory @ sysbus 0x32000000
     size: 0x00100000
 
 // TODO(b/196910893): Revert the temporary change on DMEM memory later
@@ -25,7 +25,7 @@
 // Renode. From the vector core's point of view, the WindowMMUs should be at
 // 0x30000000/0x34000000 for IMMU/DMMU respectively, but from the SMC's point of
 // view that should be where the instruction/data TCMs are.
-vec_immu : CPU.SpringbokRiscV32_WindowMMU @ sysbus 0x31000000
+vec_immu : CPU.SpringbokRiscV32_WindowMMU @ sysbus 0x33000000
     tcm: ram_vec_imem
     windowSize: 0x10000
     tcmSize: 0x10000

springbok.resc

diff --git a/springbok.resc b/springbok.resc
index 42b166b..1b8ea66 100644
--- a/springbok.resc
+++ b/springbok.resc
@@ -20,6 +20,6 @@
     sysbus LoadELF $bin
     # Start the vector core at address 0 of its instruction TCM.
     sysbus.cpu2 IsHalted true
-    sysbus.cpu2 PC 0x30000000
+    sysbus.cpu2 PC 0x32000000
 """
 runMacro $reset