Nexus: replace Springbok with Kelvin

Forking ml_core.repl to [springbok|kelvin]_ml_core.repl.

Change-Id: Icf4bb5277be7a671c14a8e6e05b72c7a41ffb8d3

platforms/kelvin.repl

diff --git a/platforms/kelvin.repl b/platforms/kelvin.repl
index 00469f3..4579a49 100644
--- a/platforms/kelvin.repl
+++ b/platforms/kelvin.repl
@@ -16,16 +16,7 @@
 // Kelvin single test core
 // ***************************************************
 
-// TODO(jonathantate): Move the cpu and dmem blocks back into ml_core.repl and
-// uncomment this 'using ".../ml_core.repl"' line.
-// using "sim/config/platforms/ml_core.repl"
-
-cpu2: CPU.KelvinRiscV32 @ sysbus
-    hartId: 2
-
-//RAM_VEC_MEM      [‘h5A00_0000 - ‘h5A3F_FFFF)   4MB RAM for Vector core
-ram_vec_dmem: Memory.MappedMemory @ sysbus 0x5A000000
-    size: 0x00400000
+using "sim/config/platforms/kelvin_ml_core.repl"
 
 vec_controlblock : CPU.KelvinRiscV32_ControlBlock @ sysbus 0x5C000000
     core: cpu2

platforms/kelvin_ml_core.repl

diff --git a/platforms/kelvin_ml_core.repl b/platforms/kelvin_ml_core.repl
new file mode 100644
index 0000000..ac91986
--- /dev/null
+++ b/platforms/kelvin_ml_core.repl
@@ -0,0 +1,24 @@
+// Copyright 2022 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// ***************************************************
+// ML Core
+// ***************************************************
+
+cpu2: CPU.KelvinRiscV32 @ sysbus
+    hartId: 2
+
+//RAM_VEC_MEM      [‘h5A00_0000 - ‘h5A3F_FFFF)   4MB RAM for Vector core
+ram_vec_dmem: Memory.MappedMemory @ sysbus 0x5A000000
+    size: 0x00400000

platforms/nexus.repl

diff --git a/platforms/nexus.repl b/platforms/nexus.repl
index 243d75f..5a26874 100644
--- a/platforms/nexus.repl
+++ b/platforms/nexus.repl
@@ -1,6 +1,6 @@
 using "sim/config/platforms/smc.repl"
 using "sim/config/platforms/secure.repl"
-using "sim/config/platforms/ml_core.repl"
+using "sim/config/platforms/nexus_ml_core.repl"
 
 // To model the TLUL mailbox spec, we need a Renode peripheral that listens
 // to address ranges for both endpoints of the mailbox. This is the current
@@ -27,12 +27,10 @@
     rtirq_B -> smc_plic@11 // kTopMatchaPlicIrqIdMailboxSmcRtirq
     eirq_B  -> smc_plic@12 // kTopMatchaPlicIrqIdMailboxSmcEirq
 
-vec_controlblock : CPU.SpringbokRiscV32_ControlBlock @ sysbus 0x47000000
+vec_controlblock : CPU.KelvinRiscV32_ControlBlock @ sysbus 0x5C000000
     core: cpu2
-    mmuNumWindows: 6 // See: go/shodan-vc-memory
-    mmuVirtualWindowSize: 0x1000000
-    mmuMemorySize: 0x1000000
-    mmuRangeStart: 0x80000000
+    tcmSize:       0x00400000
+    tcmRangeStart: 0x5A000000
     HostReqIRQ -> smc_plic@13           // kTopMatchaPlicIrqIdVcTopHostReq @ top_matcha.h
     FinishIRQ -> smc_plic@14            // kTopMatchaPlicIrqIdVcTopFinish @ top_matcha.h
     InstructionFaultIRQ -> smc_plic@15  // kTopMatchaPlicIrqIdVcTopInstructionFault @ top_matcha.h

platforms/shodan.repl

diff --git a/platforms/shodan.repl b/platforms/shodan.repl
index 243d75f..07c8135 100644
--- a/platforms/shodan.repl
+++ b/platforms/shodan.repl
@@ -1,6 +1,6 @@
 using "sim/config/platforms/smc.repl"
 using "sim/config/platforms/secure.repl"
-using "sim/config/platforms/ml_core.repl"
+using "sim/config/platforms/springbok_ml_core.repl"
 
 // To model the TLUL mailbox spec, we need a Renode peripheral that listens
 // to address ranges for both endpoints of the mailbox. This is the current

platforms/springbok.repl

diff --git a/platforms/springbok.repl b/platforms/springbok.repl
index 37fc388..bf69c4f 100644
--- a/platforms/springbok.repl
+++ b/platforms/springbok.repl
@@ -16,7 +16,7 @@
 // Springbok single test core (no mmu enabled)
 // ***************************************************
 
-using "sim/config/platforms/ml_core.repl"
+using "sim/config/platforms/springbok_ml_core.repl"
 
 vec_controlblock : CPU.SpringbokRiscV32_ControlBlock @ sysbus 0x47000000
     core: cpu2

platforms/springbok_ml_core.repl

diff --git a/platforms/ml_core.repl b/platforms/springbok_ml_core.repl
similarity index 100%
rename from platforms/ml_core.repl
rename to platforms/springbok_ml_core.repl