| using "sim/config/platforms/smc.repl" | |
| using "sim/config/platforms/secure.repl" | |
| using "sim/config/platforms/vector.repl" | |
| // Core 0 Mailbox [‘h400F_0000 - ‘h400F_0020) 32B | |
| mailbox0: Mailbox @ sysbus 0x400F0000 | |
| mailbox_hiwater -> plic@100 // TODO(aappleby) these plic lines are bogus, fix them | |
| mailbox_lowater -> plic@101 | |
| // Core 1 Mailbox [‘h400F_1000 - ‘h400F_1020) 32B | |
| mailbox1: Mailbox @ sysbus 0x400F1000 | |
| mailbox_hiwater -> smc_plic@9 // TODO(aappleby) these plic lines are bogus, fix them | |
| mailbox_lowater -> smc_plic@10 | |
| vec_controlblock : | |
| HostReqIRQ -> smc_plic@11 | |
| FinishIRQ -> smc_plic@12 | |
| InstructionFaultIRQ -> smc_plic@13 | |
| DataFaultIRQ -> smc_plic@14 | |
| // ISP [‘h4200_0000 - ‘h4200_FFFF) 64KB ISP registers | |
| // DMA Ctrl [‘h4201_0000 - ‘h4201_FFFF) 64KB DMA control interface | |
| // DSP Ctrl [‘h4202_0000 - ‘h4202_FFFF) 64KB Audio DSP control interface |