| // Copyright 2023 Google LLC |
| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| { |
| // Name of the sim cfg - typically same as the name of the DUT. |
| name: dma |
| |
| // Top level dut name (sv module). |
| dut: dma |
| |
| // Top level testbench name (sv module). |
| tb: tb |
| |
| // Simulator used to sign off this block |
| tool: vcs |
| |
| // Fusesoc core file used for building the file list. |
| fusesoc_core: lowrisc:dv:dma_sim:0.1 |
| |
| // Testplan hjson file. |
| testplan: "{proj_root}/hw/ip/dma/data/dma_testplan.hjson" |
| |
| // RAL spec - used to generate the RAL model. |
| ral_spec: "{proj_root}/hw/ip/dma/data/dma.hjson" |
| |
| // Import additional common sim cfg files. |
| // TODO: remove imported cfgs that do not apply. |
| import_cfgs: [// Project wide common sim cfg file |
| "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", |
| // Common CIP test lists |
| "{titan_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", |
| "{titan_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson", |
| "{titan_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson"] |
| |
| // Add additional tops for simulation. |
| sim_tops: ["dma_bind"] |
| |
| // Default iterations for all tests - each test entry can override this. |
| reseed: 32 |
| |
| // Default UVM test and seq class name. |
| uvm_test: dma_base_test |
| uvm_test_seq: dma_base_vseq |
| |
| // List of test specifications. |
| tests: [ |
| { |
| name: dma_smoke |
| uvm_test_seq: dma_smoke_vseq |
| } |
| |
| // TODO: add more tests here |
| ] |
| |
| // List of regressions. |
| regressions: [ |
| { |
| name: smoke |
| tests: ["dma_smoke"] |
| } |
| ] |
| } |