[ml_top/hw] Initialize several Kelvin regs to 0

-Enables kelvin_hello_world to pass in DV

HDL CL: https://spacebeaker-review.git.corp.google.com/c/shodan/experimental-kelvin/+/43730

Change-Id: I4ad6d2415d8b8548fd141e4806caf599343080ad

hw/top_matcha/ip/ml_top/rtl/kelvin.v

diff --git a/hw/top_matcha/ip/ml_top/rtl/kelvin.v b/hw/top_matcha/ip/ml_top/rtl/kelvin.v
index 5813913..0413998 100644
--- a/hw/top_matcha/ip/ml_top/rtl/kelvin.v
+++ b/hw/top_matcha/ip/ml_top/rtl/kelvin.v
@@ -1,4 +1,4 @@
-// SHA: 3feae402230086266a40d6d3c6a8280d34c898d3
+// SHA: 5a914477207ec5c965985e4e43269899de5e68eb
 module Regfile(
   input         clock,
   input         reset,
@@ -20849,7 +20849,7 @@
   reg  signed2d; // @[Dvu.scala 73:21]
   reg  signed2r; // @[Dvu.scala 74:21]
   reg  divide2; // @[Dvu.scala 75:21]
-  reg [5:0] count; // @[Dvu.scala 77:18]
+  reg [5:0] count; // @[Dvu.scala 77:23]
   reg [31:0] divide; // @[Dvu.scala 79:19]
   reg [31:0] remain; // @[Dvu.scala 80:19]
   reg [31:0] denom; // @[Dvu.scala 81:19]
@@ -20973,13 +20973,6 @@
     if (active & _io_req_ready_T_1) begin // @[Dvu.scala 109:29]
       divide2 <= divide1; // @[Dvu.scala 113:14]
     end
-    if (active & _io_req_ready_T_1) begin // @[Dvu.scala 109:29]
-      count <= {{1'd0}, clz}; // @[Dvu.scala 124:12]
-    end else if (compute & count < 6'h20) begin // @[Dvu.scala 125:41]
-      count <= _count_T_1; // @[Dvu.scala 129:11]
-    end else if (io_rd_valid & io_rd_ready) begin // @[Dvu.scala 130:44]
-      count <= 6'h0; // @[Dvu.scala 131:11]
-    end
     divide <= _GEN_16[31:0];
     if (active & _io_req_ready_T_1) begin // @[Dvu.scala 109:29]
       remain <= 32'h0; // @[Dvu.scala 123:12]
@@ -21012,6 +21005,17 @@
       compute <= active; // @[Dvu.scala 101:11]
     end
   end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin // @[Dvu.scala 109:29]
+      count <= 6'h0; // @[Dvu.scala 124:12]
+    end else if (active & _io_req_ready_T_1) begin // @[Dvu.scala 125:41]
+      count <= {{1'd0}, clz}; // @[Dvu.scala 129:11]
+    end else if (compute & count < 6'h20) begin // @[Dvu.scala 130:44]
+      count <= _count_T_1; // @[Dvu.scala 131:11]
+    end else if (io_rd_valid & io_rd_ready) begin // @[Dvu.scala 77:23]
+      count <= 6'h0;
+    end
+  end
 // Register and memory initialization
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
@@ -21081,6 +21085,9 @@
   if (reset) begin
     compute = 1'h0;
   end
+  if (reset) begin
+    count = 6'h0;
+  end
   `endif // RANDOMIZE
 end // initial
 `ifdef FIRRTL_AFTER_INITIAL
@@ -23841,10 +23848,10 @@
   reg [4:0] rdAddr_2; // @[VInst.scala 110:19]
   reg [4:0] rdAddr_3; // @[VInst.scala 110:19]
   reg  vvalid; // @[VInst.scala 120:23]
-  reg  vinstValid_0; // @[VInst.scala 121:23]
-  reg  vinstValid_1; // @[VInst.scala 121:23]
-  reg  vinstValid_2; // @[VInst.scala 121:23]
-  reg  vinstValid_3; // @[VInst.scala 121:23]
+  reg  vinstValid_0; // @[VInst.scala 121:27]
+  reg  vinstValid_1; // @[VInst.scala 121:27]
+  reg  vinstValid_2; // @[VInst.scala 121:27]
+  reg  vinstValid_3; // @[VInst.scala 121:27]
   reg [31:0] vinstInst_0; // @[VInst.scala 122:22]
   reg [31:0] vinstInst_1; // @[VInst.scala 122:22]
   reg [31:0] vinstInst_2; // @[VInst.scala 122:22]
@@ -24516,10 +24523,6 @@
     if (reqvalid_3) begin // @[VInst.scala 113:24]
       rdAddr_3 <= io_in_3_addr; // @[VInst.scala 114:17]
     end
-    vinstValid_0 <= reqvalid_0 & _nxtVinstValid_0_T_4; // @[VInst.scala 128:37]
-    vinstValid_1 <= reqvalid_1 & _nxtVinstValid_1_T_4; // @[VInst.scala 128:37]
-    vinstValid_2 <= reqvalid_2 & _nxtVinstValid_2_T_4; // @[VInst.scala 128:37]
-    vinstValid_3 <= reqvalid_3 & _nxtVinstValid_3_T_4; // @[VInst.scala 128:37]
     vinstInst_0 <= io_in_0_inst; // @[VInst.scala 132:18]
     vinstInst_1 <= io_in_1_inst; // @[VInst.scala 132:18]
     vinstInst_2 <= io_in_2_inst; // @[VInst.scala 132:18]
@@ -24814,6 +24817,34 @@
     end
   end
   always @(posedge clock or posedge reset) begin
+    if (reset) begin // @[VInst.scala 128:37]
+      vinstValid_0 <= 1'h0;
+    end else begin
+      vinstValid_0 <= reqvalid_0 & _nxtVinstValid_0_T_4;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin // @[VInst.scala 128:37]
+      vinstValid_1 <= 1'h0;
+    end else begin
+      vinstValid_1 <= reqvalid_1 & _nxtVinstValid_1_T_4;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin // @[VInst.scala 128:37]
+      vinstValid_2 <= 1'h0;
+    end else begin
+      vinstValid_2 <= reqvalid_2 & _nxtVinstValid_2_T_4;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin // @[VInst.scala 128:37]
+      vinstValid_3 <= 1'h0;
+    end else begin
+      vinstValid_3 <= reqvalid_3 & _nxtVinstValid_3_T_4;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
     if (reset) begin // @[VInst.scala 278:38]
       nempty <= 1'h0;
     end else begin
@@ -24989,6 +25020,18 @@
     vvalid = 1'h0;
   end
   if (reset) begin
+    vinstValid_0 = 1'h0;
+  end
+  if (reset) begin
+    vinstValid_1 = 1'h0;
+  end
+  if (reset) begin
+    vinstValid_2 = 1'h0;
+  end
+  if (reset) begin
+    vinstValid_3 = 1'h0;
+  end
+  if (reset) begin
     nempty = 1'h0;
   end
   `endif // RANDOMIZE