[smc/hw] Prevent LSU misalignment accesses on dPTW

-DMEM PTWs on a misaligned load/store previously had the LSU fsm waiting
on rvalid in addition to the MMU

Change-Id: Ib6601b3436d9d4d9bbcd8ae5ecbbc8ac089abf3c

hw/top_matcha/ip/smc/rtl/smc_core.sv

diff --git a/hw/top_matcha/ip/smc/rtl/smc_core.sv b/hw/top_matcha/ip/smc/rtl/smc_core.sv
index 0471728..43e5242 100644
--- a/hw/top_matcha/ip/smc/rtl/smc_core.sv
+++ b/hw/top_matcha/ip/smc/rtl/smc_core.sv
@@ -886,7 +886,8 @@
     .perf_store_o(perf_store),
 
     // mmu
-    .ptw_spec_iwalk_i(mmu_ptw_spec_iwalk)
+    .ptw_spec_iwalk_i(mmu_ptw_spec_iwalk),
+    .ptw_spec_walk_i(mmu_ptw_spec_walk)
   );
 
   ////////////////////////////

hw/top_matcha/ip/smc/rtl/smc_load_store_unit.sv

diff --git a/hw/top_matcha/ip/smc/rtl/smc_load_store_unit.sv b/hw/top_matcha/ip/smc/rtl/smc_load_store_unit.sv
index 8724991..cac7e89 100644
--- a/hw/top_matcha/ip/smc/rtl/smc_load_store_unit.sv
+++ b/hw/top_matcha/ip/smc/rtl/smc_load_store_unit.sv
@@ -70,7 +70,8 @@
   output logic                 perf_store_o,
 
   // MMU
-  input logic                  ptw_spec_iwalk_i
+  input logic                  ptw_spec_iwalk_i,
+  input logic                  ptw_spec_walk_i
 );
 
   logic [31:0]  data_addr;
@@ -369,7 +370,7 @@
   /////////////
 
   // check for misaligned accesses that need to be split into two word-aligned accesses
-  assign split_misaligned_access =
+  assign split_misaligned_access = ~ptw_spec_walk_i &
       ((lsu_type_i == 2'b00) && (data_offset != 2'b00)) || // misaligned word access
       ((lsu_type_i == 2'b01) && (data_offset == 2'b11));   // misaligned half-word access