[smc/hw] Allow misaligned mem requests after PTW

-After a PTW on a misaligned memory address, the LSU sends out two
consecutive aligned requests to fulfill the op. Previously, the MMU
masked the second data request.

Change-Id: Id2de5010759c7e67a4b695ef9de05fbc9f86d02b

hw/top_matcha/ip/smc/rtl/smc_core.sv

diff --git a/hw/top_matcha/ip/smc/rtl/smc_core.sv b/hw/top_matcha/ip/smc/rtl/smc_core.sv
index 43e5242..7748ffc 100644
--- a/hw/top_matcha/ip/smc/rtl/smc_core.sv
+++ b/hw/top_matcha/ip/smc/rtl/smc_core.sv
@@ -949,7 +949,6 @@
       .mmu_data_rdata_o      ( mmu_data_rdata     ),
 
       .lsu_req_i             ( lsu_req            ),
-      .lsu_req_done_i        ( lsu_req_done       ),
       .lsu_req_in_dec_i      ( lsu_req_in_dec     ),
 
       // General Control Signals

hw/top_matcha/ip/smc/rtl/smc_mmu.sv

diff --git a/hw/top_matcha/ip/smc/rtl/smc_mmu.sv b/hw/top_matcha/ip/smc/rtl/smc_mmu.sv
index ca56ac8..69880b4 100644
--- a/hw/top_matcha/ip/smc/rtl/smc_mmu.sv
+++ b/hw/top_matcha/ip/smc/rtl/smc_mmu.sv
@@ -49,7 +49,6 @@
     output logic [31:0]          mmu_data_rdata_o,
 
     input logic                  lsu_req_i,
-    input logic                  lsu_req_done_i, // used to ensure we don't store to dmem twice after a ptw finishes
     input logic                  lsu_req_in_dec_i,
 
     // General Control Signals
@@ -248,7 +247,7 @@
   assign paging_en_lsu  = satp_i.mode & (priv_lvl_lsu_i != PRIV_LVL_M);
 
   // Categorize atomic RMW ops and stores as writes for pte permissions
-  assign is_write     = (mmu_data_we_i != LOAD) ? 1'b1 : 1'b0;
+  assign is_write = mmu_data_we_i != LOAD;
 
   // Check page access errors based on privilege mode and mstatus bits only
   assign dmem_access_error =
@@ -367,7 +366,7 @@
       data_addr_o        = dtlb_superpage ? {dtlb_pte_content.ppn[19:10], mmu_data_addr_i[21:0]} :
                                             {dtlb_pte_content.ppn[19:0],  mmu_data_addr_i[11:0]};
       data_req_o         = mmu_data_req_i;
-      data_we            = is_write & (ptw_finish_lsu_dec_q | lsu_req_done_i);
+      data_we            = is_write;
       data_be_o          = mmu_data_be_i;
       data_wdata_o       = mmu_data_wdata_i;