hw/top_matcha/ip/tlul_mailbox/data/tlul_mailbox.hjson

// Copyright 2023 Google LLC
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

{ name: "tlul_mailbox",

  clocking: [
    {clock: "clk_i", reset: "rst_ni", primary: true},
  ],
  bus_interfaces: [

    { protocol: "tlul", direction: "device"},
  ],

  // As current opentitan build script, the registers set (state/enable/test) for each of interrupt
  // added in below interrupt_list will only be added in the first tlul device defined in
  // above bus_interface, i.e., "csr".

  interrupt_list: [
    {
      name: "wtirq"
      desc: "raised if the write fifo threshold exceed threshold."
    }
    {
      name: "rtirq"
      desc: "raised if the read fifo threshold exceed threshold."
    }
    {
      name: "eirq"
      desc: "raised if error on tlul_mailbox access."
    }
 ],


  param_list: [
  { name:    "MailboxDepth",
      type:    "int",
      default: "8",
      desc:    "Mailbox FIFO depth"
      local:   "false",
      expose:  "true"
    },
  ],


  regwidth: "32",

  registers: [

      { name: "mboxw",
        desc: "Mailbox write register address",
        swaccess: "rw",
        hwaccess: "hro",
        hwqe: "true",
        fields: [
          { bits: "31:0",
            name: "addr",
            resval: 0x0
            desc: "write register address"
          }
        ]
      },

      { name: "mboxr",
        desc: "Mailbox read register address",
        swaccess: "ro",
        hwaccess: "hrw",
        hwext:    "true"
        hwre:     "true"
        fields: [
          { bits: "31:0",
            name: "addr",
            resval: 0x0
            desc: "read register address"
          }
        ]
      },

      { name:     "STATUS"
        desc:     "Mailbox status register"
        swaccess: "ro"
        hwaccess: "hwo"
        hwext:    "true"
        fields: [
          { bits: "0"
            name: "empty"
            resval: 0x1
            desc: "Read FIFO is empty"
          }
          { bits: "1"
            name: "full"
            resval: 0x0
            desc: "Write FIFO is full and subsequent writes to tlul_mailbox are ignored"
          }
          { bits: "2"
            name: "WFIFOL"
            resval: 0x0
            desc: "Write FIFO level is higher than the threashold set in WIRQT"
          }
          { bits: "3"
            name: "RFIFOL"
            resval: 0x0
            desc: "Read FIFO level is higher than the threashold set in RIRQT"
          }
        ],
	tags: [ // Exclude from init or write-read check
	       "excl:CsrAllTests:CsrExclWriteCheck"],
      }

      { name: "ERROR",
        desc: "Mailbox error register",
        swaccess: "ro",
        hwaccess: "hwo",
        hwext:    "true"
        fields: [
          { bits: "0",
            name: "read_error",
            resval: 0x1
            desc: "Attempted read from an empty tlul_mailbox"
          }
          { bits: "1",
            name: "write_error",
            resval: 0x0
            desc: "Atempted write to a full tlul_mailbox"
          }
        ],
	tags: [ // Exclude from init or write-read check
	       "excl:CsrAllTests:CsrExclWriteCheck"],
      }

      { name: "WIRQT",
        desc: "Write interrupt request threshold register"
        swaccess: "rw",
        hwaccess: "hro",
        fields: [
          { bits: "2:0",
            name: "wr_irq_th",
            desc: "Write interrupt request threshold"
            resval: 0x0
          }
        ]
      }
     { name: "RIRQT",
        desc: "Read interrupt request threshold register.",
        swaccess: "rw",
        hwaccess: "hro",
        fields: [
          { bits: "2:0",
            name: "rd_irq_th",
            desc: "Read interrupt request threshold"
            resval: 0x0
          }
        ]
      }
      { name: "CTRL",
        desc: "Mailbox control register"
        swaccess: "rw",
        hwaccess: "hro",
        fields: [
          { bits: "0",
            name: "flush_rfifo",
            desc: "Flush the write FIFO for this port"
          }
          { bits: "1",
            name: "flush_wfifo"
            desc: "Flush the read FIFO for this port"
          }
        ]
      }
  ]
}