Merge "Add 2 alert tests in edacloud_nightly regression suite"
diff --git a/hw/BUILD b/hw/BUILD
index ef96f16..ff9c76c 100644
--- a/hw/BUILD
+++ b/hw/BUILD
@@ -8,7 +8,6 @@
package(default_visibility = ["//visibility:public"])
-
# This configuration exposes fusesoc's "make_options" to enable parallel
# compilation of the verilated model.
string_list_flag(
@@ -41,6 +40,12 @@
target = "sim",
)
+filegroup(
+ name = "verilator_bin",
+ srcs = [":verilator_real"],
+ output_group = "binary",
+)
+
# This is used in CI steps that do not want to run Verilator tests, and thus
# do not want to accidentally build the Verilator model. This causes the
# //hw:verilator target to not emit any files, which will break any tests that
@@ -67,7 +72,7 @@
name = "verilator",
actual = select({
":disable_verilator_build": ":verilator_stub",
- "//conditions:default": ":verilator_real",
+ "//conditions:default": ":verilator_bin",
}),
tags = ["verilator"],
visibility = ["//visibility:public"],
diff --git a/hw/top_matcha/data/chip_testplan.hjson b/hw/top_matcha/data/chip_testplan.hjson
index eaed0b7..69d9de3 100644
--- a/hw/top_matcha/data/chip_testplan.hjson
+++ b/hw/top_matcha/data/chip_testplan.hjson
@@ -726,6 +726,16 @@
tests: ["chip_sw_rv_timer_irq"]
}
{
+ name: chip_sw_smc_env_test
+ desc: '''Verify the timeout interrupt assertion.
+
+ - Bring up both secure core and SMC core.
+ - Verify SMC could be terminated by writing the status register.
+ '''
+ stage: V2
+ tests: ["chip_sw_smc_env_test"]
+ }
+ {
name: chip_sw_smc_timer
desc: '''Verify the timeout interrupt assertion.
@@ -3826,7 +3836,7 @@
- SW check back data and compare with the golden pattern.
'''
stage: V2
- tests: ["chip_sw_smc_isp_simple_test_data"]
+ tests: ["chip_sw_smc_isp_wrapper_tpg_64_64_test"]
}
{
name: chip_sw_smc_isp_dma_smoketest
diff --git a/hw/top_matcha/dv/chip_sim_cfg.hjson b/hw/top_matcha/dv/chip_sim_cfg.hjson
index d1ba784..f32f306 100644
--- a/hw/top_matcha/dv/chip_sim_cfg.hjson
+++ b/hw/top_matcha/dv/chip_sim_cfg.hjson
@@ -355,6 +355,33 @@
run_opts: ["+xbar_mode=1"]
reseed: 100
}
+ {
+ name: sw_test_mode_common_with_smc
+ run_opts: ["+sw_build_device={sw_build_device}",
+ // Format SW image names (which are Bazel labels concatenated with an index
+ // and/or flags, see below) into output file names separated by commas to feed into
+ // +sw_images plusarg. For example, if the input list of SW images is
+ // ["//sw/device/tests/sim_dv:uart_tx_rx_test:1",
+ // "//sw/device/lib/testing/test_rom:test_rom:0"], then the output of this eval_cmd
+ // will be: "uart_tx_rx_test:1,test_rom:0".
+ '''+sw_images={eval_cmd} \
+ reformatted_sw_images=; \
+ for image in {sw_images}; do \
+ reformatted_sw_images="$reformatted_sw_images `echo $image | cut -d: -f2-`"; \
+ done; \
+ echo $reformatted_sw_images | sed -E 's/\s+/,/g' ''']
+ en_run_modes: ["gen_otp_images_mode"]
+ }
+ {
+ name: sw_test_mode_test_rom_with_smc
+ sw_images: ["//sw/device/lib/testing/test_rom:test_rom:0"]
+ en_run_modes: ["sw_test_mode_common_with_smc"]
+ }
+ {
+ name: sw_test_mode_test_simple_sec
+ sw_images: ["//sw/device/tests:simple_sec:1:ot_flash_binary:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom_with_smc"]
+ }
]
// List of test specifications.
@@ -381,6 +408,20 @@
// 4 milliseconds of timeout.
tests: [
{
+ name: chip_sw_smc_isp_wrapper_tpg_64_64_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_isp_wrapper_tpg_64_64_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_env_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_env_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
// Reused from hw/dv/tools/dvsim/tests/csr_tests.hjson.
name: "chip_csr_bit_bash"
// Don't test over 200 randomly picked CSRs at a time.
@@ -1820,6 +1861,8 @@
"chip_sw_rstmgr_sw_rst",
"chip_sw_rv_plic_smoketest",
"chip_sw_rv_timer_irq",
+ "chip_sw_smc_env_test",
+ "chip_sw_smc_isp_wrapper_tpg_64_64_test",
"chip_sw_spi_device_tx_rx",
"chip_sw_sram_ctrl_smoketest",
"chip_sw_uart_smoketest",
@@ -1857,6 +1900,8 @@
"chip_sw_rstmgr_sw_rst",
"chip_sw_rv_plic_smoketest",
"chip_sw_rv_timer_irq",
+ "chip_sw_smc_env_test",
+ "chip_sw_smc_isp_wrapper_tpg_64_64_test",
"chip_sw_spi_device_tx_rx",
"chip_sw_sram_ctrl_smoketest",
"chip_sw_uart_smoketest",
@@ -1894,6 +1939,8 @@
"chip_sw_rstmgr_sw_rst",
"chip_sw_rv_plic_smoketest",
"chip_sw_rv_timer_irq",
+ "chip_sw_smc_env_test",
+ "chip_sw_smc_isp_wrapper_tpg_64_64_test",
"chip_sw_spi_device_tx_rx",
"chip_sw_sram_ctrl_smoketest",
"chip_sw_uart_smoketest",
diff --git a/hw/top_matcha/dv/env/chip_common_pkg.sv b/hw/top_matcha/dv/env/chip_common_pkg.sv
index 4a7198b..a444fae 100644
--- a/hw/top_matcha/dv/env/chip_common_pkg.sv
+++ b/hw/top_matcha/dv/env/chip_common_pkg.sv
@@ -21,9 +21,13 @@
// SW constants - use unmapped address space with at least 32 bytes.
parameter bit [top_pkg::TL_AW-1:0] SW_DV_START_ADDR = tl_main_pkg::ADDR_SPACE_RV_CORE_IBEX_SEC__CFG +
rv_core_ibex_reg_pkg::RV_CORE_IBEX_DV_SIM_WINDOW_OFFSET;
+ parameter bit [top_pkg::TL_AW-1:0] SW_DV_SMC_START_ADDR = tl_smc_pkg::ADDR_SPACE_RV_CORE_IBEX_SMC__CFG +
+ rv_core_ibex_reg_pkg::RV_CORE_IBEX_DV_SIM_WINDOW_OFFSET;
parameter bit [top_pkg::TL_AW-1:0] SW_DV_TEST_STATUS_ADDR = SW_DV_START_ADDR + 0;
parameter bit [top_pkg::TL_AW-1:0] SW_DV_LOG_ADDR = SW_DV_START_ADDR + 4;
+ parameter bit [top_pkg::TL_AW-1:0] SW_DV_SMC_TEST_STATUS_ADDR = SW_DV_SMC_START_ADDR + 0;
+ parameter bit [top_pkg::TL_AW-1:0] SW_DV_SMC_LOG_ADDR = SW_DV_SMC_START_ADDR + 4;
parameter uint ROM_CONSOLE_UART = 0;
diff --git a/hw/top_matcha/dv/env/chip_env.sv b/hw/top_matcha/dv/env/chip_env.sv
index df2b3f9..b3e787b 100644
--- a/hw/top_matcha/dv/env/chip_env.sv
+++ b/hw/top_matcha/dv/env/chip_env.sv
@@ -56,12 +56,20 @@
if (!uvm_config_db#(sw_logger_vif)::get(this, "", "sw_logger_vif", cfg.sw_logger_vif)) begin
`uvm_fatal(`gfn, "failed to get sw_logger_vif from uvm_config_db")
end
+ if (!uvm_config_db#(sw_logger_vif)::get(this, "", "sw_smc_logger_vif", cfg.sw_smc_logger_vif)) begin
+ `uvm_fatal(`gfn, "failed to get sw_smc_logger_vif from uvm_config_db")
+ end
if (!uvm_config_db#(virtual sw_test_status_if)::get(
this, "", "sw_test_status_vif", cfg.sw_test_status_vif
)) begin
`uvm_fatal(`gfn, "failed to get sw_test_status_vif from uvm_config_db")
end
+ if (!uvm_config_db#(virtual sw_test_status_if)::get(
+ this, "", "sw_smc_test_status_vif", cfg.sw_smc_test_status_vif
+ )) begin
+ `uvm_fatal(`gfn, "failed to get sw_smc_test_status_vif from uvm_config_db")
+ end
// get the handle to the ast supply interface.
if (!uvm_config_db#(virtual ast_supply_if)::get(
diff --git a/hw/top_matcha/dv/env/chip_env_cfg.sv b/hw/top_matcha/dv/env/chip_env_cfg.sv
index 12c947d..6f630a7 100644
--- a/hw/top_matcha/dv/env/chip_env_cfg.sv
+++ b/hw/top_matcha/dv/env/chip_env_cfg.sv
@@ -71,11 +71,13 @@
otp_type_e use_otp_image = OtpTypeLcStRma;
string otp_images[otp_type_e];
- uint sw_test_timeout_ns = 12_000_000; // 12ms
- sw_logger_vif sw_logger_vif;
- sw_test_status_vif sw_test_status_vif;
- ast_supply_vif ast_supply_vif;
- ast_ext_clk_vif ast_ext_clk_vif;
+ uint sw_test_timeout_ns = 12_000_000; // 12ms
+ sw_logger_vif sw_logger_vif;
+ sw_test_status_vif sw_test_status_vif;
+ sw_smc_logger_vif sw_smc_logger_vif;
+ sw_smc_test_status_vif sw_smc_test_status_vif;
+ ast_supply_vif ast_supply_vif;
+ ast_ext_clk_vif ast_ext_clk_vif;
// Number of RAM tiles for each RAM instance.
uint num_ram_main_tiles;
@@ -425,7 +427,7 @@
end
end else if (i == SwTypeOtp) begin
otp_images[OtpTypeCustom] = $sformatf("%0s.24.vmem", sw_images[i]);
- end else if (i == SwTypeDebug) begin
+ end else if (i == SwTypeDebug || i == SwTypeSmc) begin
sw_images[i] = $sformatf("%0s_%0s", sw_images[i], sw_build_device);
end
end
diff --git a/hw/top_matcha/dv/env/chip_env_pkg.sv b/hw/top_matcha/dv/env/chip_env_pkg.sv
index 6b361fd..874577e 100644
--- a/hw/top_matcha/dv/env/chip_env_pkg.sv
+++ b/hw/top_matcha/dv/env/chip_env_pkg.sv
@@ -47,6 +47,7 @@
import pwm_monitor_pkg::*;
import pwm_reg_pkg::NOutputs;
import tl_main_pkg::ADDR_SPACE_RV_CORE_IBEX_SEC__CFG;
+ import tl_smc_pkg::ADDR_SPACE_RV_CORE_IBEX_SMC__CFG;
import rv_core_ibex_reg_pkg::RV_CORE_IBEX_DV_SIM_WINDOW_OFFSET;
import i2c_agent_pkg::*;
import pattgen_agent_pkg::*;
@@ -67,6 +68,8 @@
typedef virtual sw_logger_if sw_logger_vif;
typedef virtual sw_test_status_if sw_test_status_vif;
+ typedef virtual sw_logger_if sw_smc_logger_vif;
+ typedef virtual sw_test_status_if sw_smc_test_status_vif;
typedef virtual ast_supply_if ast_supply_vif;
typedef virtual ast_ext_clk_if ast_ext_clk_vif;
@@ -88,7 +91,8 @@
Otp,
RamMain[16],
RamRet[16],
- Rom
+ Rom,
+ Smc_ram
} chip_mem_e;
// On OpenTitan, we deal with 4 types of SW - ROM, the main test, the OTBN test and the OTP image.
@@ -99,7 +103,8 @@
SwTypeTestSlotB = 2, // Ibex SW - test SW in (flash) slot B.
SwTypeOtbn = 3, // Otbn SW
SwTypeOtp = 4, // Customized OTP image
- SwTypeDebug = 5 // Debug SW - injected into SRAM.
+ SwTypeDebug = 5, // Debug SW - injected into SRAM.
+ SwTypeSmc = 6 // SMC SW
} sw_type_e;
// Our dvsim.py configuration always generates five base OTP images (in various lifecycle states)
diff --git a/hw/top_matcha/dv/env/seq_lib/chip_sw_base_vseq.sv b/hw/top_matcha/dv/env/seq_lib/chip_sw_base_vseq.sv
index ea12936..f2cc535 100644
--- a/hw/top_matcha/dv/env/seq_lib/chip_sw_base_vseq.sv
+++ b/hw/top_matcha/dv/env/seq_lib/chip_sw_base_vseq.sv
@@ -53,6 +53,7 @@
`uvm_info(`gfn, "Starting cpu_init", UVM_MEDIUM)
// Initialize the sw logger interface.
+ // SEC
foreach (cfg.sw_images[i]) begin
if (i inside {SwTypeRom, SwTypeDebug, SwTypeTestSlotA, SwTypeTestSlotB}) begin
cfg.sw_logger_vif.add_sw_log_db(cfg.sw_images[i]);
@@ -61,9 +62,19 @@
cfg.sw_logger_vif.sw_log_addr = SW_DV_LOG_ADDR;
cfg.sw_logger_vif.write_sw_logs_to_file = cfg.write_sw_logs_to_file;
cfg.sw_logger_vif.ready();
+ // SMC
+ foreach (cfg.sw_images[i]) begin
+ if (i inside {SwTypeSmc}) begin
+ cfg.sw_smc_logger_vif.add_sw_log_db(cfg.sw_images[i]);
+ end
+ end
+ cfg.sw_smc_logger_vif.sw_log_addr = SW_DV_SMC_LOG_ADDR;
+ cfg.sw_smc_logger_vif.write_sw_logs_to_file = cfg.write_sw_logs_to_file;
+ cfg.sw_smc_logger_vif.ready();
// Initialize the sw test status.
- cfg.sw_test_status_vif.sw_test_status_addr = SW_DV_TEST_STATUS_ADDR;
+ cfg.sw_test_status_vif.sw_test_status_addr = SW_DV_TEST_STATUS_ADDR;
+ cfg.sw_smc_test_status_vif.sw_test_status_addr = SW_DV_SMC_TEST_STATUS_ADDR;
`uvm_info(`gfn, "Initializing SRAMs", UVM_MEDIUM)
@@ -113,6 +124,11 @@
cfg.mem_bkdr_util_h[FlashBank1Data].load_mem_from_file(
{cfg.sw_images[SwTypeTestSlotB], ".64.scr.vmem"});
end
+ // SMC RAM sw imsage load
+ if (cfg.sw_images.exists(SwTypeSmc)) begin
+ cfg.mem_bkdr_util_h[Smc_ram].load_mem_from_file(
+ {cfg.sw_images[SwTypeSmc], ".32.vmem"});
+ end
config_jitter();
@@ -226,7 +242,7 @@
fork
begin: isolation_thread
fork
- wait (cfg.sw_test_status_vif.sw_test_done);
+ wait (cfg.sw_test_status_vif.sw_test_done || cfg.sw_smc_test_status_vif.sw_test_done);
#(cfg.sw_test_timeout_ns * 1ns);
join_any
disable fork;
@@ -237,15 +253,28 @@
// Print pass / fail message to the log.
virtual function void log_sw_test_status();
- case (cfg.sw_test_status_vif.sw_test_status)
- SwTestStatusPassed: `uvm_info(`gfn, "SW TEST PASSED!", UVM_LOW)
- SwTestStatusFailed: `uvm_error(`gfn, "SW TEST FAILED!")
- default: begin
- // If the SW test has not reached the passed / failed state, then it timed out.
- `uvm_error(`gfn, $sformatf("SW TEST TIMED OUT. STATE: %0s, TIMEOUT = %0d ns\n",
- cfg.sw_test_status_vif.sw_test_status.name(), cfg.sw_test_timeout_ns))
- end
- endcase
+ if(cfg.sw_test_status_vif.sw_test_done) begin
+ case (cfg.sw_test_status_vif.sw_test_status)
+ SwTestStatusPassed: `uvm_info(`gfn, "SW TEST PASSED!", UVM_LOW)
+ SwTestStatusFailed: `uvm_error(`gfn, "SW TEST FAILED!")
+ default: begin
+ // If the SW test has not reached the passed / failed state, then it timed out.
+ `uvm_error(`gfn, $sformatf("SW TEST TIMED OUT. STATE: %0s, TIMEOUT = %0d ns\n",
+ cfg.sw_test_status_vif.sw_test_status.name(), cfg.sw_test_timeout_ns))
+ end
+ endcase
+ end
+ if(cfg.sw_smc_test_status_vif.sw_test_done) begin
+ case (cfg.sw_smc_test_status_vif.sw_test_status)
+ SwTestStatusPassed: `uvm_info(`gfn, "SW TEST PASSED!", UVM_LOW)
+ SwTestStatusFailed: `uvm_error(`gfn, "SW TEST FAILED!")
+ default: begin
+ // If the SW test has not reached the passed / failed state, then it timed out.
+ `uvm_error(`gfn, $sformatf("SW TEST TIMED OUT. STATE: %0s, TIMEOUT = %0d ns\n",
+ cfg.sw_smc_test_status_vif.sw_test_status.name(), cfg.sw_test_timeout_ns))
+ end
+ endcase
+ end
endfunction
// Configure the provided spi_agent_cfg to use flash mode, and add the
diff --git a/hw/top_matcha/dv/tb/chip_hier_macros.svh b/hw/top_matcha/dv/tb/chip_hier_macros.svh
index 6265b5d..233bf05 100644
--- a/hw/top_matcha/dv/tb/chip_hier_macros.svh
+++ b/hw/top_matcha/dv/tb/chip_hier_macros.svh
@@ -64,3 +64,4 @@
`define OTP_MEM_HIER `OTP_GENERIC_HIER.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB
`define OTBN_IMEM_HIER `OTBN_HIER.u_imem.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB
`define OTBN_DMEM_HIER `OTBN_HIER.u_dmem.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB
+`define SMC_RAM_HIER `CHIP_HIER.u_ram1p_ram_smc.u_mem.`MEM_ARRAY_SUB
diff --git a/hw/top_matcha/dv/tb/tb.sv b/hw/top_matcha/dv/tb/tb.sv
index 539c2f7..77cb5c5 100644
--- a/hw/top_matcha/dv/tb/tb.sv
+++ b/hw/top_matcha/dv/tb/tb.sv
@@ -186,6 +186,50 @@
.*
);
+ // Connect the SMC SRAM directly inside rv_core_smc.
+ `define SIM_SMC_SRAM_IF u_sim_smc_sram.u_sim_sram_if
+ // Instantiate & connect the simulation SRAM inside the SMC CPU (rv_core_ibex) using forces.
+ bit stub_smc;
+ initial begin
+ void'($value$plusargs("stub_smc_core=%0b", stub_smc));
+ end
+
+ bit en_sim_smc_sram = 1'b1;
+ wire sel_sim_smc_sram = !stub_smc & en_sim_smc_sram;
+
+ sim_sram u_sim_smc_sram (
+ .clk_i (sel_sim_smc_sram ? `SMC_CPU_HIER.clk_i : 1'b0),
+ .rst_ni (`SMC_CPU_HIER.rst_ni),
+ .tl_in_i (tlul_pkg::tl_h2d_t'(`SMC_CPU_HIER.u_tlul_req_buf.out_o)),
+ .tl_in_o (),
+ .tl_out_o (),
+ .tl_out_i ()
+ );
+
+ initial begin
+ void'($value$plusargs("en_sim_smc_sram=%0b", en_sim_smc_sram));
+ if (!stub_smc && en_sim_smc_sram) begin
+ `SIM_SMC_SRAM_IF.start_addr = SW_DV_SMC_START_ADDR;
+ force `SMC_CPU_HIER.u_tlul_rsp_buf.in_i = u_sim_smc_sram.tl_in_o;
+ end
+ end
+
+ // Bind the SW test status interface directly to the sim SRAM interface.
+ bind `SIM_SMC_SRAM_IF sw_test_status_if u_sw_smc_test_status_if (
+ .addr (tl_h2d.a_address),
+ .data (tl_h2d.a_data[15:0]),
+ .fetch_en (dut.chip_if.pwrmgr_cpu_fetch_en),
+ .*
+ );
+
+ // Bind the SW logger interface directly to the sim SRAM interface.
+ bind `SIM_SMC_SRAM_IF sw_logger_if u_sw_smc_logger_if (
+ .addr (tl_h2d.a_address),
+ .data (tl_h2d.a_data),
+ .*
+ );
+
+
initial begin
// IO Interfaces
uvm_config_db#(virtual chip_if)::set(null, "*.env", "chip_vif", dut.chip_if);
@@ -193,8 +237,12 @@
// SW logger and test status interfaces.
uvm_config_db#(virtual sw_test_status_if)::set(
null, "*.env", "sw_test_status_vif", `SIM_SRAM_IF.u_sw_test_status_if);
+ uvm_config_db#(virtual sw_test_status_if)::set(
+ null, "*.env", "sw_smc_test_status_vif", `SIM_SMC_SRAM_IF.u_sw_smc_test_status_if);
uvm_config_db#(virtual sw_logger_if)::set(
null, "*.env", "sw_logger_vif", `SIM_SRAM_IF.u_sw_logger_if);
+ uvm_config_db#(virtual sw_logger_if)::set(
+ null, "*.env", "sw_smc_logger_vif", `SIM_SMC_SRAM_IF.u_sw_smc_logger_if);
// AST supply interface.
uvm_config_db#(virtual ast_supply_if)::set(
@@ -334,6 +382,16 @@
.system_base_addr (top_matcha_pkg::TOP_MATCHA_RAM_RET_AON_BASE_ADDR));
`MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[RamRet0], `RAM_RET_MEM_HIER)
+ `uvm_info("tb.sv", "Creating mem_bkdr_util instance for SMC_RAM", UVM_MEDIUM)
+ m_mem_bkdr_util[Smc_ram] = new(
+ .name ("mem_bkdr_util[Smc_ram]"),
+ .path (`DV_STRINGIFY(`SMC_RAM_HIER)),
+ .depth ($size(`SMC_RAM_HIER)),
+ .n_bits($bits(`SMC_RAM_HIER)),
+ .err_detection_scheme(mem_bkdr_util_pkg::ErrDetectionNone),
+ .system_base_addr (top_matcha_pkg::TOP_MATCHA_RAM_SMC_BASE_ADDR));
+ `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[Smc_ram], `SMC_RAM_HIER)
+
`uvm_info("tb.sv", "Creating mem_bkdr_util instance for ROM", UVM_MEDIUM)
m_mem_bkdr_util[Rom] = new(
.name ("mem_bkdr_util[Rom]"),
diff --git a/hw/top_matcha/ip/ml_top/rtl/kelvin.v b/hw/top_matcha/ip/ml_top/rtl/kelvin.v
index feb6d69..e9ef1b2 100644
--- a/hw/top_matcha/ip/ml_top/rtl/kelvin.v
+++ b/hw/top_matcha/ip/ml_top/rtl/kelvin.v
@@ -1,4 +1,4 @@
-// SHA: 79b26d29361bb7daee24abcee6493d05441b17ff
+// SHA: fb78d8ccc36939bd88c4d4f55185d283831d14a6
module Regfile(
input clock,
input reset,
@@ -4298,23 +4298,23 @@
wire [1:0] _opos_T_1 = opos + 2'h1; // @[Slice.scala 39:18]
wire full = ipos[0] == opos[0] & ipos[1] != opos[1]; // @[Slice.scala 47:36]
wire _io_in_ready_T = ~full; // @[Slice.scala 51:22]
- wire _T_3 = ivalid & ~ovalid; // @[Slice.scala 77:18]
- wire _T_5 = ivalid & ovalid; // @[Slice.scala 78:18]
- wire _T_7 = ivalid & ovalid & _io_in_ready_T; // @[Slice.scala 78:28]
- wire _T_8 = ivalid & ~ovalid & empty | _T_7; // @[Slice.scala 77:38]
- wire _T_14 = _T_5 & full; // @[Slice.scala 83:28]
- wire _T_15 = _T_3 & ~empty | _T_14; // @[Slice.scala 82:39]
+ wire _T_3 = ivalid & ~ovalid; // @[Slice.scala 58:18]
+ wire _T_5 = ivalid & ovalid; // @[Slice.scala 59:18]
+ wire _T_7 = ivalid & ovalid & _io_in_ready_T; // @[Slice.scala 59:28]
+ wire _T_8 = ivalid & ~ovalid & empty | _T_7; // @[Slice.scala 58:38]
+ wire _T_14 = _T_5 & full; // @[Slice.scala 64:28]
+ wire _T_15 = _T_3 & ~empty | _T_14; // @[Slice.scala 63:39]
assign io_in_ready = ~full; // @[Slice.scala 51:22]
- assign io_out_valid = ~empty; // @[Slice.scala 107:21]
- assign io_out_bits = mem_0; // @[Slice.scala 108:18]
+ assign io_out_valid = ~empty; // @[Slice.scala 88:21]
+ assign io_out_bits = mem_0; // @[Slice.scala 89:18]
always @(posedge clock) begin
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0 <= io_in_bits; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0 <= mem_1; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0 <= io_in_bits; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0 <= mem_1; // @[Slice.scala 55:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1 <= io_in_bits; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1 <= io_in_bits; // @[Slice.scala 65:14]
end
end
always @(posedge clock or posedge reset) begin
@@ -15045,68 +15045,68 @@
wire empty = ipos == opos; // @[Slice.scala 29:20]
wire ivalid = io_in_valid & io_in_ready; // @[Slice.scala 31:28]
wire ovalid = io_out_valid & io_out_ready; // @[Slice.scala 32:29]
- assign io_in_ready = empty | io_out_ready; // @[Slice.scala 93:28]
- assign io_out_valid = ~empty; // @[Slice.scala 107:21]
- assign io_out_bits_addr = mem_0_addr; // @[Slice.scala 108:18]
- assign io_out_bits_adrx = mem_0_adrx; // @[Slice.scala 108:18]
- assign io_out_bits_data = mem_0_data; // @[Slice.scala 108:18]
- assign io_out_bits_index = mem_0_index; // @[Slice.scala 108:18]
- assign io_out_bits_size = mem_0_size; // @[Slice.scala 108:18]
- assign io_out_bits_write = mem_0_write; // @[Slice.scala 108:18]
- assign io_out_bits_sext = mem_0_sext; // @[Slice.scala 108:18]
- assign io_out_bits_fload = mem_0_fload; // @[Slice.scala 108:18]
- assign io_out_bits_iload = mem_0_iload; // @[Slice.scala 108:18]
- assign io_out_bits_fencei = mem_0_fencei; // @[Slice.scala 108:18]
- assign io_out_bits_flushat = mem_0_flushat; // @[Slice.scala 108:18]
- assign io_out_bits_flushall = mem_0_flushall; // @[Slice.scala 108:18]
- assign io_out_bits_sldst = mem_0_sldst; // @[Slice.scala 108:18]
- assign io_out_bits_vldst = mem_0_vldst; // @[Slice.scala 108:18]
- assign io_out_bits_suncd = mem_0_suncd; // @[Slice.scala 108:18]
+ assign io_in_ready = empty | io_out_ready; // @[Slice.scala 74:28]
+ assign io_out_valid = ~empty; // @[Slice.scala 88:21]
+ assign io_out_bits_addr = mem_0_addr; // @[Slice.scala 89:18]
+ assign io_out_bits_adrx = mem_0_adrx; // @[Slice.scala 89:18]
+ assign io_out_bits_data = mem_0_data; // @[Slice.scala 89:18]
+ assign io_out_bits_index = mem_0_index; // @[Slice.scala 89:18]
+ assign io_out_bits_size = mem_0_size; // @[Slice.scala 89:18]
+ assign io_out_bits_write = mem_0_write; // @[Slice.scala 89:18]
+ assign io_out_bits_sext = mem_0_sext; // @[Slice.scala 89:18]
+ assign io_out_bits_fload = mem_0_fload; // @[Slice.scala 89:18]
+ assign io_out_bits_iload = mem_0_iload; // @[Slice.scala 89:18]
+ assign io_out_bits_fencei = mem_0_fencei; // @[Slice.scala 89:18]
+ assign io_out_bits_flushat = mem_0_flushat; // @[Slice.scala 89:18]
+ assign io_out_bits_flushall = mem_0_flushall; // @[Slice.scala 89:18]
+ assign io_out_bits_sldst = mem_0_sldst; // @[Slice.scala 89:18]
+ assign io_out_bits_vldst = mem_0_vldst; // @[Slice.scala 89:18]
+ assign io_out_bits_suncd = mem_0_suncd; // @[Slice.scala 89:18]
always @(posedge clock) begin
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0_addr <= io_in_bits_addr; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0_addr <= io_in_bits_addr; // @[Slice.scala 80:14]
end
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0_adrx <= io_in_bits_adrx; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0_adrx <= io_in_bits_adrx; // @[Slice.scala 80:14]
end
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0_data <= io_in_bits_data; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0_data <= io_in_bits_data; // @[Slice.scala 80:14]
end
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0_index <= io_in_bits_index; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0_index <= io_in_bits_index; // @[Slice.scala 80:14]
end
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0_size <= io_in_bits_size; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0_size <= io_in_bits_size; // @[Slice.scala 80:14]
end
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0_write <= io_in_bits_write; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0_write <= io_in_bits_write; // @[Slice.scala 80:14]
end
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0_sext <= io_in_bits_sext; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0_sext <= io_in_bits_sext; // @[Slice.scala 80:14]
end
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0_fload <= io_in_bits_fload; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0_fload <= io_in_bits_fload; // @[Slice.scala 80:14]
end
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0_iload <= io_in_bits_iload; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0_iload <= io_in_bits_iload; // @[Slice.scala 80:14]
end
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0_fencei <= io_in_bits_fencei; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0_fencei <= io_in_bits_fencei; // @[Slice.scala 80:14]
end
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0_flushat <= io_in_bits_flushat; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0_flushat <= io_in_bits_flushat; // @[Slice.scala 80:14]
end
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0_flushall <= io_in_bits_flushall; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0_flushall <= io_in_bits_flushall; // @[Slice.scala 80:14]
end
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0_sldst <= io_in_bits_sldst; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0_sldst <= io_in_bits_sldst; // @[Slice.scala 80:14]
end
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0_vldst <= io_in_bits_vldst; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0_vldst <= io_in_bits_vldst; // @[Slice.scala 80:14]
end
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0_suncd <= io_in_bits_suncd; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0_suncd <= io_in_bits_suncd; // @[Slice.scala 80:14]
end
end
always @(posedge clock or posedge reset) begin
@@ -20821,86 +20821,86 @@
wire [1:0] _opos_T_1 = opos + 2'h1; // @[Slice.scala 39:18]
wire full = ipos[0] == opos[0] & ipos[1] != opos[1]; // @[Slice.scala 47:36]
wire _io_in_ready_T = ~full; // @[Slice.scala 49:22]
- wire _T_3 = ivalid & ~io_out_valid; // @[Slice.scala 77:18]
- wire _T_5 = ivalid & io_out_valid; // @[Slice.scala 78:18]
- wire _T_7 = ivalid & io_out_valid & _io_in_ready_T; // @[Slice.scala 78:28]
- wire _T_8 = ivalid & ~io_out_valid & empty | _T_7; // @[Slice.scala 77:38]
- wire _T_14 = _T_5 & full; // @[Slice.scala 83:28]
- wire _T_15 = _T_3 & ~empty | _T_14; // @[Slice.scala 82:39]
+ wire _T_3 = ivalid & ~io_out_valid; // @[Slice.scala 58:18]
+ wire _T_5 = ivalid & io_out_valid; // @[Slice.scala 59:18]
+ wire _T_7 = ivalid & io_out_valid & _io_in_ready_T; // @[Slice.scala 59:28]
+ wire _T_8 = ivalid & ~io_out_valid & empty | _T_7; // @[Slice.scala 58:38]
+ wire _T_14 = _T_5 & full; // @[Slice.scala 64:28]
+ wire _T_15 = _T_3 & ~empty | _T_14; // @[Slice.scala 63:39]
assign io_in_ready = 1'h1; // @[Slice.scala 49:28]
- assign io_out_valid = ~empty; // @[Slice.scala 107:21]
- assign io_out_bits_addr = mem_0_addr; // @[Slice.scala 108:18]
- assign io_out_bits_index = mem_0_index; // @[Slice.scala 108:18]
- assign io_out_bits_size = mem_0_size; // @[Slice.scala 108:18]
- assign io_out_bits_sext = mem_0_sext; // @[Slice.scala 108:18]
- assign io_out_bits_fload = mem_0_fload; // @[Slice.scala 108:18]
- assign io_out_bits_iload = mem_0_iload; // @[Slice.scala 108:18]
- assign io_out_bits_sldst = mem_0_sldst; // @[Slice.scala 108:18]
- assign io_out_bits_suncd = mem_0_suncd; // @[Slice.scala 108:18]
+ assign io_out_valid = ~empty; // @[Slice.scala 88:21]
+ assign io_out_bits_addr = mem_0_addr; // @[Slice.scala 89:18]
+ assign io_out_bits_index = mem_0_index; // @[Slice.scala 89:18]
+ assign io_out_bits_size = mem_0_size; // @[Slice.scala 89:18]
+ assign io_out_bits_sext = mem_0_sext; // @[Slice.scala 89:18]
+ assign io_out_bits_fload = mem_0_fload; // @[Slice.scala 89:18]
+ assign io_out_bits_iload = mem_0_iload; // @[Slice.scala 89:18]
+ assign io_out_bits_sldst = mem_0_sldst; // @[Slice.scala 89:18]
+ assign io_out_bits_suncd = mem_0_suncd; // @[Slice.scala 89:18]
always @(posedge clock) begin
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_addr <= io_in_bits_addr; // @[Slice.scala 79:14]
- end else if (io_out_valid & full) begin // @[Slice.scala 73:27]
- mem_0_addr <= mem_1_addr; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_addr <= io_in_bits_addr; // @[Slice.scala 60:14]
+ end else if (io_out_valid & full) begin // @[Slice.scala 54:27]
+ mem_0_addr <= mem_1_addr; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_index <= io_in_bits_index; // @[Slice.scala 79:14]
- end else if (io_out_valid & full) begin // @[Slice.scala 73:27]
- mem_0_index <= mem_1_index; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_index <= io_in_bits_index; // @[Slice.scala 60:14]
+ end else if (io_out_valid & full) begin // @[Slice.scala 54:27]
+ mem_0_index <= mem_1_index; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_size <= io_in_bits_size; // @[Slice.scala 79:14]
- end else if (io_out_valid & full) begin // @[Slice.scala 73:27]
- mem_0_size <= mem_1_size; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_size <= io_in_bits_size; // @[Slice.scala 60:14]
+ end else if (io_out_valid & full) begin // @[Slice.scala 54:27]
+ mem_0_size <= mem_1_size; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_sext <= io_in_bits_sext; // @[Slice.scala 79:14]
- end else if (io_out_valid & full) begin // @[Slice.scala 73:27]
- mem_0_sext <= mem_1_sext; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_sext <= io_in_bits_sext; // @[Slice.scala 60:14]
+ end else if (io_out_valid & full) begin // @[Slice.scala 54:27]
+ mem_0_sext <= mem_1_sext; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_fload <= io_in_bits_fload; // @[Slice.scala 79:14]
- end else if (io_out_valid & full) begin // @[Slice.scala 73:27]
- mem_0_fload <= mem_1_fload; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_fload <= io_in_bits_fload; // @[Slice.scala 60:14]
+ end else if (io_out_valid & full) begin // @[Slice.scala 54:27]
+ mem_0_fload <= mem_1_fload; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_iload <= io_in_bits_iload; // @[Slice.scala 79:14]
- end else if (io_out_valid & full) begin // @[Slice.scala 73:27]
- mem_0_iload <= mem_1_iload; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_iload <= io_in_bits_iload; // @[Slice.scala 60:14]
+ end else if (io_out_valid & full) begin // @[Slice.scala 54:27]
+ mem_0_iload <= mem_1_iload; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_sldst <= io_in_bits_sldst; // @[Slice.scala 79:14]
- end else if (io_out_valid & full) begin // @[Slice.scala 73:27]
- mem_0_sldst <= mem_1_sldst; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_sldst <= io_in_bits_sldst; // @[Slice.scala 60:14]
+ end else if (io_out_valid & full) begin // @[Slice.scala 54:27]
+ mem_0_sldst <= mem_1_sldst; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_suncd <= io_in_bits_suncd; // @[Slice.scala 79:14]
- end else if (io_out_valid & full) begin // @[Slice.scala 73:27]
- mem_0_suncd <= mem_1_suncd; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_suncd <= io_in_bits_suncd; // @[Slice.scala 60:14]
+ end else if (io_out_valid & full) begin // @[Slice.scala 54:27]
+ mem_0_suncd <= mem_1_suncd; // @[Slice.scala 55:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_addr <= io_in_bits_addr; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_addr <= io_in_bits_addr; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_index <= io_in_bits_index; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_index <= io_in_bits_index; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_size <= io_in_bits_size; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_size <= io_in_bits_size; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_sext <= io_in_bits_sext; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_sext <= io_in_bits_sext; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_fload <= io_in_bits_fload; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_fload <= io_in_bits_fload; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_iload <= io_in_bits_iload; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_iload <= io_in_bits_iload; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_sldst <= io_in_bits_sldst; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_sldst <= io_in_bits_sldst; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_suncd <= io_in_bits_suncd; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_suncd <= io_in_bits_suncd; // @[Slice.scala 65:14]
end
end
always @(posedge clock or posedge reset) begin
@@ -26629,7 +26629,7 @@
input clock,
input reset,
input io_op_valid,
- input [4:0] io_op_bits,
+ input [3:0] io_op_bits,
output io_ina_ready,
input io_ina_valid,
input [31:0] io_ina_bits_0,
@@ -26665,42 +26665,38 @@
reg [31:0] _RAND_19;
reg [31:0] _RAND_20;
`endif // RANDOMIZE_REG_INIT
- reg active1; // @[FMAdd.scala 33:24]
- reg active2; // @[FMAdd.scala 34:24]
- reg active3; // @[FMAdd.scala 35:24]
- reg [4:0] op1; // @[FMAdd.scala 36:16]
- reg state1__0_sign; // @[FMAdd.scala 38:19]
- reg [9:0] state1__0_exp; // @[FMAdd.scala 38:19]
- reg [47:0] state1__0_mul; // @[FMAdd.scala 38:19]
- reg state1__0_zero; // @[FMAdd.scala 38:19]
- reg state1__0_inf_a; // @[FMAdd.scala 38:19]
- reg state1__0_inf_b; // @[FMAdd.scala 38:19]
- reg state1__0_nan; // @[FMAdd.scala 38:19]
- reg state2_0_sign; // @[FMAdd.scala 39:19]
- reg [9:0] state2_0_exp; // @[FMAdd.scala 39:19]
- reg [48:0] state2_0_ain; // @[FMAdd.scala 39:19]
- reg [48:0] state2_0_bin; // @[FMAdd.scala 39:19]
- reg state2_0_sel; // @[FMAdd.scala 39:19]
- reg state2_0_add; // @[FMAdd.scala 39:19]
- reg state2_0_sub; // @[FMAdd.scala 39:19]
- reg state3_0_sign; // @[FMAdd.scala 40:19]
- reg [7:0] state3_0_exp; // @[FMAdd.scala 40:19]
- reg [22:0] state3_0_man; // @[FMAdd.scala 40:19]
- wire _update1_T_3 = ~active1; // @[FMAdd.scala 42:98]
- wire update1 = io_ina_valid & io_inb_valid & io_ina_ready & io_inb_ready & (io_inc_ready | ~active1); // @[FMAdd.scala 42:78]
- wire update2 = active1 & io_inc_valid & io_inc_ready; // @[FMAdd.scala 43:41]
- wire isMul = io_op_valid & ~io_op_bits[4]; // @[FMAdd.scala 66:27]
- wire isDot = io_op_valid & io_op_bits[4]; // @[FMAdd.scala 67:27]
- wire isSub = io_op_bits[2] | io_op_bits[3]; // @[FMAdd.scala 68:42]
- wire [31:0] mul_ina = isMul ? io_ina_bits_0 : 32'h0; // @[FMAdd.scala 76:22]
- wire [31:0] mul_inb = isMul ? io_inb_bits_0 : 32'h0; // @[FMAdd.scala 77:22]
- wire [31:0] dot_ina = isDot ? io_ina_bits_0 : 32'h0; // @[FMAdd.scala 78:22]
- wire [31:0] dot_inb = isDot ? io_inb_bits_0 : 32'h0; // @[FMAdd.scala 79:22]
- wire _mul_sina_T_3 = isSub ? ~mul_ina[31] : mul_ina[31]; // @[FMAdd.scala 84:29]
+ reg active1; // @[FMAdd.scala 32:24]
+ reg active2; // @[FMAdd.scala 33:24]
+ reg active3; // @[FMAdd.scala 34:24]
+ reg [3:0] op1; // @[FMAdd.scala 35:16]
+ reg state1__0_sign; // @[FMAdd.scala 37:19]
+ reg [9:0] state1__0_exp; // @[FMAdd.scala 37:19]
+ reg [47:0] state1__0_mul; // @[FMAdd.scala 37:19]
+ reg state1__0_zero; // @[FMAdd.scala 37:19]
+ reg state1__0_inf_a; // @[FMAdd.scala 37:19]
+ reg state1__0_inf_b; // @[FMAdd.scala 37:19]
+ reg state1__0_nan; // @[FMAdd.scala 37:19]
+ reg state2_0_sign; // @[FMAdd.scala 38:19]
+ reg [9:0] state2_0_exp; // @[FMAdd.scala 38:19]
+ reg [48:0] state2_0_ain; // @[FMAdd.scala 38:19]
+ reg [48:0] state2_0_bin; // @[FMAdd.scala 38:19]
+ reg state2_0_sel; // @[FMAdd.scala 38:19]
+ reg state2_0_add; // @[FMAdd.scala 38:19]
+ reg state2_0_sub; // @[FMAdd.scala 38:19]
+ reg state3_0_sign; // @[FMAdd.scala 39:19]
+ reg [7:0] state3_0_exp; // @[FMAdd.scala 39:19]
+ reg [22:0] state3_0_man; // @[FMAdd.scala 39:19]
+ wire _update1_T_3 = ~active1; // @[FMAdd.scala 41:98]
+ wire update1 = io_ina_valid & io_inb_valid & io_ina_ready & io_inb_ready & (io_inc_ready | ~active1); // @[FMAdd.scala 41:78]
+ wire update2 = active1 & io_inc_valid & io_inc_ready; // @[FMAdd.scala 42:41]
+ wire isSub = io_op_bits[2] | io_op_bits[3]; // @[FMAdd.scala 66:42]
+ wire [31:0] mul_ina = io_op_valid ? io_ina_bits_0 : 32'h0; // @[FMAdd.scala 74:22]
+ wire [31:0] mul_inb = io_op_valid ? io_inb_bits_0 : 32'h0; // @[FMAdd.scala 75:22]
+ wire _mul_sina_T_3 = isSub ? ~mul_ina[31] : mul_ina[31]; // @[FMAdd.scala 80:29]
wire [31:0] mul_sina = {_mul_sina_T_3,mul_ina[30:0]}; // @[Cat.scala 31:58]
wire _state1_0_zero_T_1 = mul_sina[30:0] == 31'h0; // @[FBase.scala 76:18]
wire _state1_0_zero_T_3 = mul_inb[30:0] == 31'h0; // @[FBase.scala 76:18]
- wire state1_0_zero = _state1_0_zero_T_1 | _state1_0_zero_T_3; // @[FMAdd.scala 173:33]
+ wire state1_0_zero = _state1_0_zero_T_1 | _state1_0_zero_T_3; // @[FMAdd.scala 157:33]
wire _state1_0_inf_a_T_1 = mul_sina[30:23] == 8'hff; // @[FBase.scala 64:19]
wire state1_0_inf_a = mul_sina[30:23] == 8'hff & mul_sina[22:0] == 23'h0; // @[FBase.scala 64:37]
wire _state1_0_inf_b_T_1 = mul_inb[30:23] == 8'hff; // @[FBase.scala 64:19]
@@ -26713,195 +26709,65 @@
wire state1_0_subn_b = mul_inb[30:23] == 8'h0 & _state1_0_nan_b_T_3; // @[FBase.scala 72:27]
wire state1_0_sign_a = mul_sina[31]; // @[FBase.scala 28:14]
wire state1_0_sign_b = mul_inb[31]; // @[FBase.scala 28:14]
- wire [7:0] state1_0_iexp_a = state1_0_subn_a ? 8'h1 : mul_sina[30:23]; // @[FMAdd.scala 188:21]
- wire [7:0] state1_0_iexp_b = state1_0_subn_b ? 8'h1 : mul_inb[30:23]; // @[FMAdd.scala 189:21]
- wire _state1_0_iman_a_T = state1_0_subn_a ? 1'h0 : 1'h1; // @[FMAdd.scala 190:25]
+ wire [7:0] state1_0_iexp_a = state1_0_subn_a ? 8'h1 : mul_sina[30:23]; // @[FMAdd.scala 172:21]
+ wire [7:0] state1_0_iexp_b = state1_0_subn_b ? 8'h1 : mul_inb[30:23]; // @[FMAdd.scala 173:21]
+ wire _state1_0_iman_a_T = state1_0_subn_a ? 1'h0 : 1'h1; // @[FMAdd.scala 174:25]
wire [23:0] state1_0_iman_a = {_state1_0_iman_a_T,mul_sina[22:0]}; // @[Cat.scala 31:58]
- wire _state1_0_iman_b_T = state1_0_subn_b ? 1'h0 : 1'h1; // @[FMAdd.scala 191:25]
+ wire _state1_0_iman_b_T = state1_0_subn_b ? 1'h0 : 1'h1; // @[FMAdd.scala 175:25]
wire [23:0] state1_0_iman_b = {_state1_0_iman_b_T,mul_inb[22:0]}; // @[Cat.scala 31:58]
- wire [9:0] state1_0_nbias = 10'h0 - 10'h7f; // @[FMAdd.scala 221:17]
- wire state1_0_sign = state1_0_sign_a ^ state1_0_sign_b; // @[FMAdd.scala 223:23]
- wire [8:0] _state1_0_exp_T = state1_0_iexp_a + state1_0_iexp_b; // @[FMAdd.scala 224:22]
- wire [9:0] _GEN_54 = {{1'd0}, _state1_0_exp_T}; // @[FMAdd.scala 224:31]
- wire [9:0] state1_0_exp = _GEN_54 + state1_0_nbias; // @[FMAdd.scala 224:31]
- wire [47:0] state1_0_mul = state1_0_iman_a * state1_0_iman_b; // @[FMAdd.scala 225:22]
- wire _state1_0_exp_z_T = ~state1_0_zero; // @[FMAdd.scala 197:21]
- wire [9:0] state1_0_exp_z = ~state1_0_zero ? state1_0_exp : 10'h0; // @[FMAdd.scala 197:20]
- wire [47:0] state1_0_mul_z = _state1_0_exp_z_T ? state1_0_mul : 48'h0; // @[FMAdd.scala 198:20]
- wire state1_0_state1_nan = state1_0_nan_a | state1_0_nan_b; // @[FMAdd.scala 209:27]
- wire bfst_sign_a = dot_ina[15]; // @[FBase.scala 212:14]
- wire bfst_sign_b = dot_inb[15]; // @[FBase.scala 212:14]
- wire [7:0] bfst_exp_a = dot_ina[14:7]; // @[FBase.scala 198:14]
- wire [7:0] bfst_exp_b = dot_inb[14:7]; // @[FBase.scala 198:14]
- wire [6:0] bfst_man_a_m = dot_ina[6:0]; // @[FBase.scala 205:14]
- wire [7:0] bfst_man_a = {1'h1,bfst_man_a_m}; // @[Cat.scala 31:58]
- wire [6:0] bfst_man_b_m = dot_inb[6:0]; // @[FBase.scala 205:14]
- wire [7:0] bfst_man_b = {1'h1,bfst_man_b_m}; // @[Cat.scala 31:58]
- wire bfst_sign0 = bfst_sign_a ^ bfst_sign_b; // @[BFDot.scala 155:23]
- wire [8:0] _bfst_exp_T = bfst_exp_a + bfst_exp_b; // @[BFDot.scala 156:22]
- wire [9:0] _GEN_55 = {{1'd0}, _bfst_exp_T}; // @[BFDot.scala 156:31]
- wire [9:0] bfst_exp = _GEN_55 + state1_0_nbias; // @[BFDot.scala 156:31]
- wire [15:0] bfst_mul = bfst_man_a * bfst_man_b; // @[BFDot.scala 157:22]
- wire bfst_infM = bfst_mul[15] & bfst_exp == 10'hfe; // @[BFDot.scala 163:26]
- wire _bfst_zeroM_T_1 = ~bfst_mul[15]; // @[BFDot.scala 164:17]
- wire bfst_zeroM = ~bfst_mul[15] & bfst_exp[7:0] == 8'h0; // @[BFDot.scala 164:26]
- wire _bfst_inf_T = bfst_exp_a == 8'hff; // @[BFDot.scala 166:21]
- wire _bfst_inf_T_1 = bfst_exp_b == 8'hff; // @[BFDot.scala 166:40]
- wire bfst_inf0 = bfst_exp_a == 8'hff | bfst_exp_b == 8'hff | bfst_exp == 10'hff | bfst_exp[9:8] == 2'h1 | bfst_infM; // @[BFDot.scala 166:92]
- wire bfst_zero0 = bfst_exp_a == 8'h0 | bfst_exp_b == 8'h0 | bfst_exp[9] | bfst_zeroM | bfst_inf0; // @[BFDot.scala 167:66]
- wire [9:0] _bfst_shfexp_T_3 = bfst_exp + 10'h1; // @[BFDot.scala 170:41]
- wire [9:0] bfst_exp0 = _bfst_zeroM_T_1 ? bfst_exp : _bfst_shfexp_T_3; // @[BFDot.scala 170:21]
- wire [16:0] _bfst_shfmul_T_2 = {bfst_mul,1'h0}; // @[Cat.scala 31:58]
- wire [16:0] _bfst_shfmul_T_3 = {1'h0,bfst_mul}; // @[Cat.scala 31:58]
- wire [16:0] bfst_mul0 = _bfst_zeroM_T_1 ? _bfst_shfmul_T_2 : _bfst_shfmul_T_3; // @[BFDot.scala 171:21]
- wire bfst_sign_a_1 = dot_ina[31]; // @[FBase.scala 212:14]
- wire bfst_sign_b_1 = dot_inb[31]; // @[FBase.scala 212:14]
- wire [7:0] bfst_exp_a_1 = dot_ina[30:23]; // @[FBase.scala 198:14]
- wire [7:0] bfst_exp_b_1 = dot_inb[30:23]; // @[FBase.scala 198:14]
- wire [6:0] bfst_man_a_m_1 = dot_ina[22:16]; // @[FBase.scala 205:14]
- wire [7:0] bfst_man_a_1 = {1'h1,bfst_man_a_m_1}; // @[Cat.scala 31:58]
- wire [6:0] bfst_man_b_m_1 = dot_inb[22:16]; // @[FBase.scala 205:14]
- wire [7:0] bfst_man_b_1 = {1'h1,bfst_man_b_m_1}; // @[Cat.scala 31:58]
- wire bfst_sign1 = bfst_sign_a_1 ^ bfst_sign_b_1; // @[BFDot.scala 155:23]
- wire [8:0] _bfst_exp_T_2 = bfst_exp_a_1 + bfst_exp_b_1; // @[BFDot.scala 156:22]
- wire [9:0] _GEN_56 = {{1'd0}, _bfst_exp_T_2}; // @[BFDot.scala 156:31]
- wire [9:0] bfst_exp_1 = _GEN_56 + state1_0_nbias; // @[BFDot.scala 156:31]
- wire [15:0] bfst_mul_1 = bfst_man_a_1 * bfst_man_b_1; // @[BFDot.scala 157:22]
- wire bfst_infM_1 = bfst_mul_1[15] & bfst_exp_1 == 10'hfe; // @[BFDot.scala 163:26]
- wire _bfst_zeroM_T_5 = ~bfst_mul_1[15]; // @[BFDot.scala 164:17]
- wire bfst_zeroM_1 = ~bfst_mul_1[15] & bfst_exp_1[7:0] == 8'h0; // @[BFDot.scala 164:26]
- wire _bfst_inf_T_9 = bfst_exp_a_1 == 8'hff; // @[BFDot.scala 166:21]
- wire _bfst_inf_T_10 = bfst_exp_b_1 == 8'hff; // @[BFDot.scala 166:40]
- wire bfst_inf1 = bfst_exp_a_1 == 8'hff | bfst_exp_b_1 == 8'hff | bfst_exp_1 == 10'hff | bfst_exp_1[9:8] == 2'h1 |
- bfst_infM_1; // @[BFDot.scala 166:92]
- wire bfst_zero1 = bfst_exp_a_1 == 8'h0 | bfst_exp_b_1 == 8'h0 | bfst_exp_1[9] | bfst_zeroM_1 | bfst_inf1; // @[BFDot.scala 167:66]
- wire [9:0] _bfst_shfexp_T_7 = bfst_exp_1 + 10'h1; // @[BFDot.scala 170:41]
- wire [9:0] bfst_exp1 = _bfst_zeroM_T_5 ? bfst_exp_1 : _bfst_shfexp_T_7; // @[BFDot.scala 170:21]
- wire [16:0] _bfst_shfmul_T_6 = {bfst_mul_1,1'h0}; // @[Cat.scala 31:58]
- wire [16:0] _bfst_shfmul_T_7 = {1'h0,bfst_mul_1}; // @[Cat.scala 31:58]
- wire [16:0] bfst_mul1 = _bfst_zeroM_T_5 ? _bfst_shfmul_T_6 : _bfst_shfmul_T_7; // @[BFDot.scala 171:21]
- wire _bfst_select_0_T_4 = _bfst_inf_T & bfst_man_a_m == 7'h0; // @[FBase.scala 223:37]
- wire _bfst_select_0_T_9 = _bfst_inf_T_1 & bfst_man_b_m == 7'h0; // @[FBase.scala 223:37]
- wire _bfst_select_0_T_16 = _bfst_inf_T_9 & bfst_man_a_m_1 == 7'h0; // @[FBase.scala 223:37]
- wire _bfst_select_0_T_17 = _bfst_select_0_T_4 | _bfst_select_0_T_9 | bfst_inf0 | _bfst_select_0_T_16; // @[BFDot.scala 90:59]
- wire _bfst_select_0_T_22 = _bfst_inf_T_10 & bfst_man_b_m_1 == 7'h0; // @[FBase.scala 223:37]
- wire bfst_select_0 = _bfst_select_0_T_17 | _bfst_select_0_T_22 | bfst_inf1; // @[BFDot.scala 91:51]
- wire _bfst_select_1_T = ~bfst_select_0; // @[BFDot.scala 94:18]
- wire _bfst_select_1_T_4 = bfst_sign0 != bfst_sign1; // @[BFDot.scala 95:38]
- wire _bfst_select_1_T_9 = _bfst_select_1_T & bfst_sign0 != bfst_sign1 & bfst_exp0 == bfst_exp1 & bfst_mul0 ==
- bfst_mul1; // @[BFDot.scala 95:65]
- wire bfst_select_1 = ~bfst_select_0 & bfst_zero0 & bfst_zero1 | _bfst_select_1_T_9; // @[BFDot.scala 94:47]
- wire _bfst_select_3_T_2 = _bfst_select_1_T & ~bfst_select_1; // @[BFDot.scala 101:29]
- wire _bfst_select_3_T_6 = _bfst_select_1_T & ~bfst_select_1 & ~bfst_zero0 & ~bfst_zero1; // @[BFDot.scala 101:53]
- wire _bfst_abgecd_T_7 = bfst_exp0[7:0] == bfst_exp1[7:0] & bfst_mul0 >= bfst_mul1; // @[BFDot.scala 74:42]
- wire bfst_abgecd = bfst_exp0[7:0] > bfst_exp1[7:0] | _bfst_abgecd_T_7; // @[BFDot.scala 73:40]
- wire _bfst_select_3_T_7 = _bfst_select_1_T & ~bfst_select_1 & ~bfst_zero0 & ~bfst_zero1 & bfst_abgecd; // @[BFDot.scala 101:63]
- wire _bfst_select_3_T_8 = bfst_sign0 == bfst_sign1; // @[BFDot.scala 101:82]
- wire bfst_select_3 = _bfst_select_1_T & ~bfst_select_1 & ~bfst_zero0 & ~bfst_zero1 & bfst_abgecd & bfst_sign0 ==
- bfst_sign1; // @[BFDot.scala 101:73]
- wire bfst_select_2 = _bfst_select_3_T_2 & bfst_zero1; // @[BFDot.scala 98:43]
- wire bfst_select_5 = _bfst_select_3_T_2 & bfst_zero0; // @[BFDot.scala 107:43]
- wire bfst_select_4 = _bfst_select_3_T_7 & _bfst_select_1_T_4; // @[BFDot.scala 104:73]
- wire _bfst_select_7_T_8 = _bfst_select_3_T_6 & ~bfst_abgecd; // @[BFDot.scala 113:63]
- wire bfst_select_7 = _bfst_select_3_T_6 & ~bfst_abgecd & _bfst_select_1_T_4; // @[BFDot.scala 113:74]
- wire bfst_select_6 = _bfst_select_7_T_8 & _bfst_select_3_T_8; // @[BFDot.scala 110:74]
- wire [7:0] _bfst_T_4 = {bfst_select_7,bfst_select_6,bfst_select_5,bfst_select_4,bfst_select_3,bfst_select_2,
- bfst_select_1,bfst_select_0}; // @[BFDot.scala 61:27]
- wire [1:0] _bfst_T_13 = _bfst_T_4[0] + _bfst_T_4[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _bfst_T_15 = _bfst_T_4[2] + _bfst_T_4[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _bfst_T_17 = _bfst_T_13 + _bfst_T_15; // @[Bitwise.scala 48:55]
- wire [1:0] _bfst_T_19 = _bfst_T_4[4] + _bfst_T_4[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _bfst_T_21 = _bfst_T_4[6] + _bfst_T_4[7]; // @[Bitwise.scala 48:55]
- wire [2:0] _bfst_T_23 = _bfst_T_19 + _bfst_T_21; // @[Bitwise.scala 48:55]
- wire [3:0] _bfst_T_25 = _bfst_T_17 + _bfst_T_23; // @[Bitwise.scala 48:55]
- wire _bfst_T_27 = _bfst_T_25 != 4'h1; // @[BFDot.scala 61:35]
- wire _bfst_T_30 = ~reset; // @[BFDot.scala 62:13]
- wire [47:0] bfst_pmul0 = {bfst_mul0,31'h0}; // @[Cat.scala 31:58]
- wire [47:0] bfst_pmul1 = {bfst_mul1,31'h0}; // @[Cat.scala 31:58]
- wire [7:0] bfst_shamt0 = bfst_exp1[7:0] - bfst_exp0[7:0]; // @[BFDot.scala 76:28]
- wire [7:0] bfst_shamt1 = bfst_exp0[7:0] - bfst_exp1[7:0]; // @[BFDot.scala 77:28]
- wire [47:0] bfst_shf0 = bfst_pmul0 >> bfst_shamt0; // @[BFDot.scala 78:22]
- wire [47:0] bfst_shf1 = bfst_pmul1 >> bfst_shamt1; // @[BFDot.scala 79:22]
- wire [47:0] bfst_abcd = bfst_pmul0 + bfst_shf1; // @[BFDot.scala 81:23]
- wire [47:0] bfst_cdab = bfst_pmul1 + bfst_shf0; // @[BFDot.scala 82:23]
- wire [47:0] bfst_abncd = bfst_pmul0 - bfst_shf1; // @[BFDot.scala 83:23]
- wire [47:0] bfst_cdnab = bfst_pmul1 - bfst_shf0; // @[BFDot.scala 84:23]
- wire _bfst_state_sign_T_1 = bfst_select_2 | bfst_select_3 | bfst_select_4; // @[BFDot.scala 119:48]
- wire _bfst_state_sign_T_2 = _bfst_state_sign_T_1 & bfst_sign0; // @[BFDot.scala 116:10]
- wire _bfst_state_sign_T_4 = bfst_select_5 | bfst_select_6 | bfst_select_7; // @[BFDot.scala 120:48]
- wire _bfst_state_sign_T_5 = _bfst_state_sign_T_4 & bfst_sign1; // @[BFDot.scala 116:10]
- wire bfst__sign = _bfst_state_sign_T_2 | _bfst_state_sign_T_5; // @[BFDot.scala 119:69]
- wire [7:0] _bfst_state_exp_T = bfst_select_0 ? 8'hff : 8'h0; // @[BFDot.scala 116:10]
- wire [9:0] _bfst_state_exp_T_1 = bfst_select_2 ? bfst_exp0 : 10'h0; // @[BFDot.scala 116:10]
- wire [9:0] _GEN_57 = {{2'd0}, _bfst_state_exp_T}; // @[BFDot.scala 122:42]
- wire [9:0] _bfst_state_exp_T_2 = _GEN_57 | _bfst_state_exp_T_1; // @[BFDot.scala 122:42]
- wire [9:0] _bfst_state_exp_T_3 = bfst_select_3 ? bfst_exp0 : 10'h0; // @[BFDot.scala 116:10]
- wire [9:0] _bfst_state_exp_T_4 = _bfst_state_exp_T_2 | _bfst_state_exp_T_3; // @[BFDot.scala 123:41]
- wire [9:0] _bfst_state_exp_T_5 = bfst_select_4 ? bfst_exp0 : 10'h0; // @[BFDot.scala 116:10]
- wire [9:0] _bfst_state_exp_T_6 = _bfst_state_exp_T_4 | _bfst_state_exp_T_5; // @[BFDot.scala 124:41]
- wire [9:0] _bfst_state_exp_T_7 = bfst_select_5 ? bfst_exp1 : 10'h0; // @[BFDot.scala 116:10]
- wire [9:0] _bfst_state_exp_T_8 = _bfst_state_exp_T_6 | _bfst_state_exp_T_7; // @[BFDot.scala 125:41]
- wire [9:0] _bfst_state_exp_T_9 = bfst_select_6 ? bfst_exp1 : 10'h0; // @[BFDot.scala 116:10]
- wire [9:0] _bfst_state_exp_T_10 = _bfst_state_exp_T_8 | _bfst_state_exp_T_9; // @[BFDot.scala 126:41]
- wire [9:0] _bfst_state_exp_T_11 = bfst_select_7 ? bfst_exp1 : 10'h0; // @[BFDot.scala 116:10]
- wire [9:0] _bfst_state_exp_T_12 = _bfst_state_exp_T_10 | _bfst_state_exp_T_11; // @[BFDot.scala 127:41]
- wire [47:0] _bfst_state_mul_T = bfst_select_2 ? bfst_pmul0 : 48'h0; // @[BFDot.scala 116:10]
- wire [47:0] _bfst_state_mul_T_1 = bfst_select_3 ? bfst_abcd : 48'h0; // @[BFDot.scala 116:10]
- wire [47:0] _bfst_state_mul_T_2 = _bfst_state_mul_T | _bfst_state_mul_T_1; // @[BFDot.scala 130:42]
- wire [47:0] _bfst_state_mul_T_3 = bfst_select_4 ? bfst_abncd : 48'h0; // @[BFDot.scala 116:10]
- wire [47:0] _bfst_state_mul_T_4 = _bfst_state_mul_T_2 | _bfst_state_mul_T_3; // @[BFDot.scala 131:41]
- wire [47:0] _bfst_state_mul_T_5 = bfst_select_5 ? bfst_pmul1 : 48'h0; // @[BFDot.scala 116:10]
- wire [47:0] _bfst_state_mul_T_6 = _bfst_state_mul_T_4 | _bfst_state_mul_T_5; // @[BFDot.scala 132:42]
- wire [47:0] _bfst_state_mul_T_7 = bfst_select_6 ? bfst_cdab : 48'h0; // @[BFDot.scala 116:10]
- wire [47:0] _bfst_state_mul_T_8 = _bfst_state_mul_T_6 | _bfst_state_mul_T_7; // @[BFDot.scala 133:42]
- wire [47:0] _bfst_state_mul_T_9 = bfst_select_7 ? bfst_cdnab : 48'h0; // @[BFDot.scala 116:10]
- wire [47:0] bfst__mul = _bfst_state_mul_T_8 | _bfst_state_mul_T_9; // @[BFDot.scala 134:41]
- wire [7:0] bfst__exp = _bfst_state_exp_T_12[7:0]; // @[BFDot.scala 122:15 58:21]
- wire csub = op1[1] | op1[3]; // @[FMAdd.scala 101:37]
- wire _cm_T_3 = csub ? ~io_inc_bits_0[31] : io_inc_bits_0[31]; // @[FMAdd.scala 102:23]
+ wire [9:0] state1_0_nbias = 10'h0 - 10'h7f; // @[FMAdd.scala 205:17]
+ wire state1_0_sign = state1_0_sign_a ^ state1_0_sign_b; // @[FMAdd.scala 207:23]
+ wire [8:0] _state1_0_exp_T = state1_0_iexp_a + state1_0_iexp_b; // @[FMAdd.scala 208:22]
+ wire [9:0] _GEN_46 = {{1'd0}, _state1_0_exp_T}; // @[FMAdd.scala 208:31]
+ wire [9:0] state1_0_exp = _GEN_46 + state1_0_nbias; // @[FMAdd.scala 208:31]
+ wire [47:0] state1_0_mul = state1_0_iman_a * state1_0_iman_b; // @[FMAdd.scala 209:22]
+ wire _state1_0_exp_z_T = ~state1_0_zero; // @[FMAdd.scala 181:21]
+ wire state1_0_state1_nan = state1_0_nan_a | state1_0_nan_b; // @[FMAdd.scala 193:27]
+ wire csub = op1[1] | op1[3]; // @[FMAdd.scala 85:37]
+ wire _cm_T_3 = csub ? ~io_inc_bits_0[31] : io_inc_bits_0[31]; // @[FMAdd.scala 86:23]
wire [31:0] cm = {_cm_T_3,io_inc_bits_0[30:0]}; // @[Cat.scala 31:58]
- wire [31:0] _GEN_58 = {{16'd0}, state1__0_mul[31:16]}; // @[Bitwise.scala 105:31]
- wire [31:0] _state2_0_a_clz_T_4 = _GEN_58 & 32'hffff; // @[Bitwise.scala 105:31]
+ wire [31:0] _GEN_47 = {{16'd0}, state1__0_mul[31:16]}; // @[Bitwise.scala 105:31]
+ wire [31:0] _state2_0_a_clz_T_4 = _GEN_47 & 32'hffff; // @[Bitwise.scala 105:31]
wire [31:0] _state2_0_a_clz_T_6 = {state1__0_mul[15:0], 16'h0}; // @[Bitwise.scala 105:70]
wire [31:0] _state2_0_a_clz_T_8 = _state2_0_a_clz_T_6 & 32'hffff0000; // @[Bitwise.scala 105:80]
wire [31:0] _state2_0_a_clz_T_9 = _state2_0_a_clz_T_4 | _state2_0_a_clz_T_8; // @[Bitwise.scala 105:39]
- wire [31:0] _GEN_59 = {{8'd0}, _state2_0_a_clz_T_9[31:8]}; // @[Bitwise.scala 105:31]
- wire [31:0] _state2_0_a_clz_T_14 = _GEN_59 & 32'hff00ff; // @[Bitwise.scala 105:31]
+ wire [31:0] _GEN_48 = {{8'd0}, _state2_0_a_clz_T_9[31:8]}; // @[Bitwise.scala 105:31]
+ wire [31:0] _state2_0_a_clz_T_14 = _GEN_48 & 32'hff00ff; // @[Bitwise.scala 105:31]
wire [31:0] _state2_0_a_clz_T_16 = {_state2_0_a_clz_T_9[23:0], 8'h0}; // @[Bitwise.scala 105:70]
wire [31:0] _state2_0_a_clz_T_18 = _state2_0_a_clz_T_16 & 32'hff00ff00; // @[Bitwise.scala 105:80]
wire [31:0] _state2_0_a_clz_T_19 = _state2_0_a_clz_T_14 | _state2_0_a_clz_T_18; // @[Bitwise.scala 105:39]
- wire [31:0] _GEN_60 = {{4'd0}, _state2_0_a_clz_T_19[31:4]}; // @[Bitwise.scala 105:31]
- wire [31:0] _state2_0_a_clz_T_24 = _GEN_60 & 32'hf0f0f0f; // @[Bitwise.scala 105:31]
+ wire [31:0] _GEN_49 = {{4'd0}, _state2_0_a_clz_T_19[31:4]}; // @[Bitwise.scala 105:31]
+ wire [31:0] _state2_0_a_clz_T_24 = _GEN_49 & 32'hf0f0f0f; // @[Bitwise.scala 105:31]
wire [31:0] _state2_0_a_clz_T_26 = {_state2_0_a_clz_T_19[27:0], 4'h0}; // @[Bitwise.scala 105:70]
wire [31:0] _state2_0_a_clz_T_28 = _state2_0_a_clz_T_26 & 32'hf0f0f0f0; // @[Bitwise.scala 105:80]
wire [31:0] _state2_0_a_clz_T_29 = _state2_0_a_clz_T_24 | _state2_0_a_clz_T_28; // @[Bitwise.scala 105:39]
- wire [31:0] _GEN_61 = {{2'd0}, _state2_0_a_clz_T_29[31:2]}; // @[Bitwise.scala 105:31]
- wire [31:0] _state2_0_a_clz_T_34 = _GEN_61 & 32'h33333333; // @[Bitwise.scala 105:31]
+ wire [31:0] _GEN_50 = {{2'd0}, _state2_0_a_clz_T_29[31:2]}; // @[Bitwise.scala 105:31]
+ wire [31:0] _state2_0_a_clz_T_34 = _GEN_50 & 32'h33333333; // @[Bitwise.scala 105:31]
wire [31:0] _state2_0_a_clz_T_36 = {_state2_0_a_clz_T_29[29:0], 2'h0}; // @[Bitwise.scala 105:70]
wire [31:0] _state2_0_a_clz_T_38 = _state2_0_a_clz_T_36 & 32'hcccccccc; // @[Bitwise.scala 105:80]
wire [31:0] _state2_0_a_clz_T_39 = _state2_0_a_clz_T_34 | _state2_0_a_clz_T_38; // @[Bitwise.scala 105:39]
- wire [31:0] _GEN_62 = {{1'd0}, _state2_0_a_clz_T_39[31:1]}; // @[Bitwise.scala 105:31]
- wire [31:0] _state2_0_a_clz_T_44 = _GEN_62 & 32'h55555555; // @[Bitwise.scala 105:31]
+ wire [31:0] _GEN_51 = {{1'd0}, _state2_0_a_clz_T_39[31:1]}; // @[Bitwise.scala 105:31]
+ wire [31:0] _state2_0_a_clz_T_44 = _GEN_51 & 32'h55555555; // @[Bitwise.scala 105:31]
wire [31:0] _state2_0_a_clz_T_46 = {_state2_0_a_clz_T_39[30:0], 1'h0}; // @[Bitwise.scala 105:70]
wire [31:0] _state2_0_a_clz_T_48 = _state2_0_a_clz_T_46 & 32'haaaaaaaa; // @[Bitwise.scala 105:80]
wire [31:0] _state2_0_a_clz_T_49 = _state2_0_a_clz_T_44 | _state2_0_a_clz_T_48; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_63 = {{8'd0}, state1__0_mul[47:40]}; // @[Bitwise.scala 105:31]
- wire [15:0] _state2_0_a_clz_T_54 = _GEN_63 & 16'hff; // @[Bitwise.scala 105:31]
+ wire [15:0] _GEN_52 = {{8'd0}, state1__0_mul[47:40]}; // @[Bitwise.scala 105:31]
+ wire [15:0] _state2_0_a_clz_T_54 = _GEN_52 & 16'hff; // @[Bitwise.scala 105:31]
wire [15:0] _state2_0_a_clz_T_56 = {state1__0_mul[39:32], 8'h0}; // @[Bitwise.scala 105:70]
wire [15:0] _state2_0_a_clz_T_58 = _state2_0_a_clz_T_56 & 16'hff00; // @[Bitwise.scala 105:80]
wire [15:0] _state2_0_a_clz_T_59 = _state2_0_a_clz_T_54 | _state2_0_a_clz_T_58; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_64 = {{4'd0}, _state2_0_a_clz_T_59[15:4]}; // @[Bitwise.scala 105:31]
- wire [15:0] _state2_0_a_clz_T_64 = _GEN_64 & 16'hf0f; // @[Bitwise.scala 105:31]
+ wire [15:0] _GEN_53 = {{4'd0}, _state2_0_a_clz_T_59[15:4]}; // @[Bitwise.scala 105:31]
+ wire [15:0] _state2_0_a_clz_T_64 = _GEN_53 & 16'hf0f; // @[Bitwise.scala 105:31]
wire [15:0] _state2_0_a_clz_T_66 = {_state2_0_a_clz_T_59[11:0], 4'h0}; // @[Bitwise.scala 105:70]
wire [15:0] _state2_0_a_clz_T_68 = _state2_0_a_clz_T_66 & 16'hf0f0; // @[Bitwise.scala 105:80]
wire [15:0] _state2_0_a_clz_T_69 = _state2_0_a_clz_T_64 | _state2_0_a_clz_T_68; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_65 = {{2'd0}, _state2_0_a_clz_T_69[15:2]}; // @[Bitwise.scala 105:31]
- wire [15:0] _state2_0_a_clz_T_74 = _GEN_65 & 16'h3333; // @[Bitwise.scala 105:31]
+ wire [15:0] _GEN_54 = {{2'd0}, _state2_0_a_clz_T_69[15:2]}; // @[Bitwise.scala 105:31]
+ wire [15:0] _state2_0_a_clz_T_74 = _GEN_54 & 16'h3333; // @[Bitwise.scala 105:31]
wire [15:0] _state2_0_a_clz_T_76 = {_state2_0_a_clz_T_69[13:0], 2'h0}; // @[Bitwise.scala 105:70]
wire [15:0] _state2_0_a_clz_T_78 = _state2_0_a_clz_T_76 & 16'hcccc; // @[Bitwise.scala 105:80]
wire [15:0] _state2_0_a_clz_T_79 = _state2_0_a_clz_T_74 | _state2_0_a_clz_T_78; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_66 = {{1'd0}, _state2_0_a_clz_T_79[15:1]}; // @[Bitwise.scala 105:31]
- wire [15:0] _state2_0_a_clz_T_84 = _GEN_66 & 16'h5555; // @[Bitwise.scala 105:31]
+ wire [15:0] _GEN_55 = {{1'd0}, _state2_0_a_clz_T_79[15:1]}; // @[Bitwise.scala 105:31]
+ wire [15:0] _state2_0_a_clz_T_84 = _GEN_55 & 16'h5555; // @[Bitwise.scala 105:31]
wire [15:0] _state2_0_a_clz_T_86 = {_state2_0_a_clz_T_79[14:0], 1'h0}; // @[Bitwise.scala 105:70]
wire [15:0] _state2_0_a_clz_T_88 = _state2_0_a_clz_T_86 & 16'haaaa; // @[Bitwise.scala 105:80]
wire [15:0] _state2_0_a_clz_T_89 = _state2_0_a_clz_T_84 | _state2_0_a_clz_T_88; // @[Bitwise.scala 105:39]
@@ -26953,40 +26819,40 @@
wire [5:0] _state2_0_a_clz_T_183 = _state2_0_a_clz_T_90[2] ? 6'h2 : _state2_0_a_clz_T_182; // @[Mux.scala 47:70]
wire [5:0] _state2_0_a_clz_T_184 = _state2_0_a_clz_T_90[1] ? 6'h1 : _state2_0_a_clz_T_183; // @[Mux.scala 47:70]
wire [5:0] state2_0_a_clz = _state2_0_a_clz_T_90[0] ? 6'h0 : _state2_0_a_clz_T_184; // @[Mux.scala 47:70]
- wire _state2_0_b_clz_T_1 = cm[30:23] != 8'h0; // @[FMAdd.scala 244:32]
+ wire _state2_0_b_clz_T_1 = cm[30:23] != 8'h0; // @[FMAdd.scala 228:32]
wire [23:0] _state2_0_b_clz_T_3 = {1'h0,cm[22:0]}; // @[Cat.scala 31:58]
- wire [15:0] _GEN_67 = {{8'd0}, _state2_0_b_clz_T_3[15:8]}; // @[Bitwise.scala 105:31]
- wire [15:0] _state2_0_b_clz_T_8 = _GEN_67 & 16'hff; // @[Bitwise.scala 105:31]
+ wire [15:0] _GEN_56 = {{8'd0}, _state2_0_b_clz_T_3[15:8]}; // @[Bitwise.scala 105:31]
+ wire [15:0] _state2_0_b_clz_T_8 = _GEN_56 & 16'hff; // @[Bitwise.scala 105:31]
wire [15:0] _state2_0_b_clz_T_10 = {_state2_0_b_clz_T_3[7:0], 8'h0}; // @[Bitwise.scala 105:70]
wire [15:0] _state2_0_b_clz_T_12 = _state2_0_b_clz_T_10 & 16'hff00; // @[Bitwise.scala 105:80]
wire [15:0] _state2_0_b_clz_T_13 = _state2_0_b_clz_T_8 | _state2_0_b_clz_T_12; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_68 = {{4'd0}, _state2_0_b_clz_T_13[15:4]}; // @[Bitwise.scala 105:31]
- wire [15:0] _state2_0_b_clz_T_18 = _GEN_68 & 16'hf0f; // @[Bitwise.scala 105:31]
+ wire [15:0] _GEN_57 = {{4'd0}, _state2_0_b_clz_T_13[15:4]}; // @[Bitwise.scala 105:31]
+ wire [15:0] _state2_0_b_clz_T_18 = _GEN_57 & 16'hf0f; // @[Bitwise.scala 105:31]
wire [15:0] _state2_0_b_clz_T_20 = {_state2_0_b_clz_T_13[11:0], 4'h0}; // @[Bitwise.scala 105:70]
wire [15:0] _state2_0_b_clz_T_22 = _state2_0_b_clz_T_20 & 16'hf0f0; // @[Bitwise.scala 105:80]
wire [15:0] _state2_0_b_clz_T_23 = _state2_0_b_clz_T_18 | _state2_0_b_clz_T_22; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_69 = {{2'd0}, _state2_0_b_clz_T_23[15:2]}; // @[Bitwise.scala 105:31]
- wire [15:0] _state2_0_b_clz_T_28 = _GEN_69 & 16'h3333; // @[Bitwise.scala 105:31]
+ wire [15:0] _GEN_58 = {{2'd0}, _state2_0_b_clz_T_23[15:2]}; // @[Bitwise.scala 105:31]
+ wire [15:0] _state2_0_b_clz_T_28 = _GEN_58 & 16'h3333; // @[Bitwise.scala 105:31]
wire [15:0] _state2_0_b_clz_T_30 = {_state2_0_b_clz_T_23[13:0], 2'h0}; // @[Bitwise.scala 105:70]
wire [15:0] _state2_0_b_clz_T_32 = _state2_0_b_clz_T_30 & 16'hcccc; // @[Bitwise.scala 105:80]
wire [15:0] _state2_0_b_clz_T_33 = _state2_0_b_clz_T_28 | _state2_0_b_clz_T_32; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_70 = {{1'd0}, _state2_0_b_clz_T_33[15:1]}; // @[Bitwise.scala 105:31]
- wire [15:0] _state2_0_b_clz_T_38 = _GEN_70 & 16'h5555; // @[Bitwise.scala 105:31]
+ wire [15:0] _GEN_59 = {{1'd0}, _state2_0_b_clz_T_33[15:1]}; // @[Bitwise.scala 105:31]
+ wire [15:0] _state2_0_b_clz_T_38 = _GEN_59 & 16'h5555; // @[Bitwise.scala 105:31]
wire [15:0] _state2_0_b_clz_T_40 = {_state2_0_b_clz_T_33[14:0], 1'h0}; // @[Bitwise.scala 105:70]
wire [15:0] _state2_0_b_clz_T_42 = _state2_0_b_clz_T_40 & 16'haaaa; // @[Bitwise.scala 105:80]
wire [15:0] _state2_0_b_clz_T_43 = _state2_0_b_clz_T_38 | _state2_0_b_clz_T_42; // @[Bitwise.scala 105:39]
- wire [7:0] _GEN_71 = {{4'd0}, _state2_0_b_clz_T_3[23:20]}; // @[Bitwise.scala 105:31]
- wire [7:0] _state2_0_b_clz_T_48 = _GEN_71 & 8'hf; // @[Bitwise.scala 105:31]
+ wire [7:0] _GEN_60 = {{4'd0}, _state2_0_b_clz_T_3[23:20]}; // @[Bitwise.scala 105:31]
+ wire [7:0] _state2_0_b_clz_T_48 = _GEN_60 & 8'hf; // @[Bitwise.scala 105:31]
wire [7:0] _state2_0_b_clz_T_50 = {_state2_0_b_clz_T_3[19:16], 4'h0}; // @[Bitwise.scala 105:70]
wire [7:0] _state2_0_b_clz_T_52 = _state2_0_b_clz_T_50 & 8'hf0; // @[Bitwise.scala 105:80]
wire [7:0] _state2_0_b_clz_T_53 = _state2_0_b_clz_T_48 | _state2_0_b_clz_T_52; // @[Bitwise.scala 105:39]
- wire [7:0] _GEN_72 = {{2'd0}, _state2_0_b_clz_T_53[7:2]}; // @[Bitwise.scala 105:31]
- wire [7:0] _state2_0_b_clz_T_58 = _GEN_72 & 8'h33; // @[Bitwise.scala 105:31]
+ wire [7:0] _GEN_61 = {{2'd0}, _state2_0_b_clz_T_53[7:2]}; // @[Bitwise.scala 105:31]
+ wire [7:0] _state2_0_b_clz_T_58 = _GEN_61 & 8'h33; // @[Bitwise.scala 105:31]
wire [7:0] _state2_0_b_clz_T_60 = {_state2_0_b_clz_T_53[5:0], 2'h0}; // @[Bitwise.scala 105:70]
wire [7:0] _state2_0_b_clz_T_62 = _state2_0_b_clz_T_60 & 8'hcc; // @[Bitwise.scala 105:80]
wire [7:0] _state2_0_b_clz_T_63 = _state2_0_b_clz_T_58 | _state2_0_b_clz_T_62; // @[Bitwise.scala 105:39]
- wire [7:0] _GEN_73 = {{1'd0}, _state2_0_b_clz_T_63[7:1]}; // @[Bitwise.scala 105:31]
- wire [7:0] _state2_0_b_clz_T_68 = _GEN_73 & 8'h55; // @[Bitwise.scala 105:31]
+ wire [7:0] _GEN_62 = {{1'd0}, _state2_0_b_clz_T_63[7:1]}; // @[Bitwise.scala 105:31]
+ wire [7:0] _state2_0_b_clz_T_68 = _GEN_62 & 8'h55; // @[Bitwise.scala 105:31]
wire [7:0] _state2_0_b_clz_T_70 = {_state2_0_b_clz_T_63[6:0], 1'h0}; // @[Bitwise.scala 105:70]
wire [7:0] _state2_0_b_clz_T_72 = _state2_0_b_clz_T_70 & 8'haa; // @[Bitwise.scala 105:80]
wire [7:0] _state2_0_b_clz_T_73 = _state2_0_b_clz_T_68 | _state2_0_b_clz_T_72; // @[Bitwise.scala 105:39]
@@ -27014,135 +26880,135 @@
wire [4:0] _state2_0_b_clz_T_119 = _state2_0_b_clz_T_74[2] ? 5'h2 : _state2_0_b_clz_T_118; // @[Mux.scala 47:70]
wire [4:0] _state2_0_b_clz_T_120 = _state2_0_b_clz_T_74[1] ? 5'h1 : _state2_0_b_clz_T_119; // @[Mux.scala 47:70]
wire [4:0] _state2_0_b_clz_T_121 = _state2_0_b_clz_T_74[0] ? 5'h0 : _state2_0_b_clz_T_120; // @[Mux.scala 47:70]
- wire [4:0] state2_0_b_clz = cm[30:23] != 8'h0 ? 5'h0 : _state2_0_b_clz_T_121; // @[FMAdd.scala 244:20]
- wire state2_0_acm_sign = cm[31]; // @[FMAdd.scala 246:23]
- wire _state2_0_acm_exp_T_4 = cm[22:0] != 23'h0; // @[FMAdd.scala 247:69]
- wire [7:0] state2_0_acm_exp = _state2_0_b_clz_T_1 ? cm[30:23] : {{7'd0}, cm[22:0] != 23'h0}; // @[FMAdd.scala 247:22]
- wire _state2_0_b_zero_T_1 = cm[22:0] == 23'h0; // @[FMAdd.scala 251:46]
- wire state2_0_b_zero = state2_0_acm_exp == 8'h0 & cm[22:0] == 23'h0; // @[FMAdd.scala 251:34]
- wire [9:0] _GEN_74 = {{4'd0}, state2_0_a_clz}; // @[FMAdd.scala 256:28]
- wire [9:0] state2_0_a_exp = state1__0_exp - _GEN_74; // @[FMAdd.scala 256:28]
+ wire [4:0] state2_0_b_clz = cm[30:23] != 8'h0 ? 5'h0 : _state2_0_b_clz_T_121; // @[FMAdd.scala 228:20]
+ wire state2_0_acm_sign = cm[31]; // @[FMAdd.scala 230:23]
+ wire _state2_0_acm_exp_T_4 = cm[22:0] != 23'h0; // @[FMAdd.scala 231:69]
+ wire [7:0] state2_0_acm_exp = _state2_0_b_clz_T_1 ? cm[30:23] : {{7'd0}, cm[22:0] != 23'h0}; // @[FMAdd.scala 231:22]
+ wire _state2_0_b_zero_T_1 = cm[22:0] == 23'h0; // @[FMAdd.scala 235:46]
+ wire state2_0_b_zero = state2_0_acm_exp == 8'h0 & cm[22:0] == 23'h0; // @[FMAdd.scala 235:34]
+ wire [9:0] _GEN_63 = {{4'd0}, state2_0_a_clz}; // @[FMAdd.scala 240:28]
+ wire [9:0] state2_0_a_exp = state1__0_exp - _GEN_63; // @[FMAdd.scala 240:28]
wire [9:0] _state2_0_b_exp_T = {2'h0,state2_0_acm_exp}; // @[Cat.scala 31:58]
- wire [9:0] _GEN_75 = {{5'd0}, state2_0_b_clz}; // @[FMAdd.scala 257:40]
- wire [9:0] _state2_0_b_exp_T_2 = _state2_0_b_exp_T - _GEN_75; // @[FMAdd.scala 257:40]
- wire [9:0] state2_0_b_exp = _state2_0_b_exp_T_2 - 10'h1; // @[FMAdd.scala 257:48]
+ wire [9:0] _GEN_64 = {{5'd0}, state2_0_b_clz}; // @[FMAdd.scala 241:40]
+ wire [9:0] _state2_0_b_exp_T_2 = _state2_0_b_exp_T - _GEN_64; // @[FMAdd.scala 241:40]
+ wire [9:0] state2_0_b_exp = _state2_0_b_exp_T_2 - 10'h1; // @[FMAdd.scala 241:48]
wire [47:0] state2_0_b_man = {_state2_0_b_clz_T_1,cm[22:0],24'h0}; // @[Cat.scala 31:58]
- wire [110:0] _GEN_0 = {{63'd0}, state1__0_mul}; // @[FMAdd.scala 264:24]
- wire [110:0] _state2_0_a_shl_T = _GEN_0 << state2_0_a_clz; // @[FMAdd.scala 264:24]
- wire [47:0] state2_0_a_shl = _state2_0_a_shl_T[47:0]; // @[FMAdd.scala 264:33]
- wire [78:0] _GEN_1 = {{31'd0}, state2_0_b_man}; // @[FMAdd.scala 265:24]
- wire [78:0] _state2_0_b_shl_T = _GEN_1 << state2_0_b_clz; // @[FMAdd.scala 265:24]
- wire [47:0] state2_0_b_shl = _state2_0_b_shl_T[47:0]; // @[FMAdd.scala 265:33]
+ wire [110:0] _GEN_0 = {{63'd0}, state1__0_mul}; // @[FMAdd.scala 248:24]
+ wire [110:0] _state2_0_a_shl_T = _GEN_0 << state2_0_a_clz; // @[FMAdd.scala 248:24]
+ wire [47:0] state2_0_a_shl = _state2_0_a_shl_T[47:0]; // @[FMAdd.scala 248:33]
+ wire [78:0] _GEN_1 = {{31'd0}, state2_0_b_man}; // @[FMAdd.scala 249:24]
+ wire [78:0] _state2_0_b_shl_T = _GEN_1 << state2_0_b_clz; // @[FMAdd.scala 249:24]
+ wire [47:0] state2_0_b_shl = _state2_0_b_shl_T[47:0]; // @[FMAdd.scala 249:33]
wire _state2_0_sp_state_c_inf_T_1 = cm[30:23] == 8'hff; // @[FBase.scala 64:19]
wire state2_0_sp_state_c_inf = cm[30:23] == 8'hff & _state2_0_b_zero_T_1; // @[FBase.scala 64:37]
wire state2_0_sp_state_c_nan = _state2_0_sp_state_c_inf_T_1 & _state2_0_acm_exp_T_4; // @[FBase.scala 68:37]
- wire _state2_0_sp_state_T_1 = state1__0_inf_a | state1__0_inf_b; // @[FMAdd.scala 311:32]
- wire _state2_0_sp_state_T_3 = state1__0_sign != state2_0_acm_sign; // @[FMAdd.scala 311:73]
- wire _GEN_21 = _state2_0_sp_state_T_3 ? 1'h0 : state2_0_acm_sign; // @[FMAdd.scala 296:17 319:37 320:21]
- wire [22:0] _GEN_22 = _state2_0_sp_state_T_3 ? 23'h400000 : 23'h0; // @[FMAdd.scala 319:37 321:20 323:20]
- wire _GEN_23 = state1__0_zero ? 1'h0 : state1__0_sign; // @[FMAdd.scala 328:26 329:21 332:21]
- wire [22:0] _GEN_24 = state1__0_zero ? 23'h400000 : 23'h0; // @[FMAdd.scala 328:26 330:20 333:20]
- wire _GEN_26 = state2_0_sp_state_c_inf | state1__0_zero; // @[FMAdd.scala 335:25 336:18]
- wire _GEN_27 = _state2_0_sp_state_T_1 | _GEN_26; // @[FMAdd.scala 325:48 326:18]
- wire [7:0] _GEN_28 = _state2_0_sp_state_T_1 ? 8'hff : cm[30:23]; // @[FMAdd.scala 297:16 325:48 327:18]
- wire _GEN_29 = _state2_0_sp_state_T_1 ? _GEN_23 : state2_0_acm_sign; // @[FMAdd.scala 296:17 325:48]
- wire [22:0] _GEN_30 = _state2_0_sp_state_T_1 ? _GEN_24 : cm[22:0]; // @[FMAdd.scala 298:16 325:48]
- wire _GEN_31 = state1__0_inf_a & state1__0_inf_b & state2_0_sp_state_c_inf | _GEN_27; // @[FMAdd.scala 316:57 317:18]
- wire [7:0] _GEN_32 = state1__0_inf_a & state1__0_inf_b & state2_0_sp_state_c_inf ? 8'hff : _GEN_28; // @[FMAdd.scala 316:57 318:18]
- wire _GEN_33 = state1__0_inf_a & state1__0_inf_b & state2_0_sp_state_c_inf ? _GEN_21 : _GEN_29; // @[FMAdd.scala 316:57]
- wire [22:0] _GEN_34 = state1__0_inf_a & state1__0_inf_b & state2_0_sp_state_c_inf ? _GEN_22 : _GEN_30; // @[FMAdd.scala 316:57]
- wire _GEN_36 = (state1__0_inf_a | state1__0_inf_b) & state2_0_sp_state_c_inf & state1__0_sign != state2_0_acm_sign |
- _GEN_31; // @[FMAdd.scala 311:85 313:18]
- wire [7:0] _GEN_37 = (state1__0_inf_a | state1__0_inf_b) & state2_0_sp_state_c_inf & state1__0_sign !=
- state2_0_acm_sign ? 8'hff : _GEN_32; // @[FMAdd.scala 311:85 314:18]
- wire [22:0] _GEN_38 = (state1__0_inf_a | state1__0_inf_b) & state2_0_sp_state_c_inf & state1__0_sign !=
- state2_0_acm_sign ? 23'h400000 : _GEN_34; // @[FMAdd.scala 311:85 315:18]
- wire state2_0_sp_state_sel = state1__0_nan | state2_0_sp_state_c_nan | _GEN_36; // @[FMAdd.scala 306:32 308:18]
- wire [7:0] _GEN_41 = state1__0_nan | state2_0_sp_state_c_nan ? 8'hff : _GEN_37; // @[FMAdd.scala 306:32 309:18]
- wire [22:0] _GEN_42 = state1__0_nan | state2_0_sp_state_c_nan ? 23'h400000 : _GEN_38; // @[FMAdd.scala 306:32 310:18]
+ wire _state2_0_sp_state_T_1 = state1__0_inf_a | state1__0_inf_b; // @[FMAdd.scala 295:32]
+ wire _state2_0_sp_state_T_3 = state1__0_sign != state2_0_acm_sign; // @[FMAdd.scala 295:73]
+ wire _GEN_13 = _state2_0_sp_state_T_3 ? 1'h0 : state2_0_acm_sign; // @[FMAdd.scala 280:17 303:37 304:21]
+ wire [22:0] _GEN_14 = _state2_0_sp_state_T_3 ? 23'h400000 : 23'h0; // @[FMAdd.scala 303:37 305:20 307:20]
+ wire _GEN_15 = state1__0_zero ? 1'h0 : state1__0_sign; // @[FMAdd.scala 312:26 313:21 316:21]
+ wire [22:0] _GEN_16 = state1__0_zero ? 23'h400000 : 23'h0; // @[FMAdd.scala 312:26 314:20 317:20]
+ wire _GEN_18 = state2_0_sp_state_c_inf | state1__0_zero; // @[FMAdd.scala 319:25 320:18]
+ wire _GEN_19 = _state2_0_sp_state_T_1 | _GEN_18; // @[FMAdd.scala 309:48 310:18]
+ wire [7:0] _GEN_20 = _state2_0_sp_state_T_1 ? 8'hff : cm[30:23]; // @[FMAdd.scala 281:16 309:48 311:18]
+ wire _GEN_21 = _state2_0_sp_state_T_1 ? _GEN_15 : state2_0_acm_sign; // @[FMAdd.scala 280:17 309:48]
+ wire [22:0] _GEN_22 = _state2_0_sp_state_T_1 ? _GEN_16 : cm[22:0]; // @[FMAdd.scala 282:16 309:48]
+ wire _GEN_23 = state1__0_inf_a & state1__0_inf_b & state2_0_sp_state_c_inf | _GEN_19; // @[FMAdd.scala 300:57 301:18]
+ wire [7:0] _GEN_24 = state1__0_inf_a & state1__0_inf_b & state2_0_sp_state_c_inf ? 8'hff : _GEN_20; // @[FMAdd.scala 300:57 302:18]
+ wire _GEN_25 = state1__0_inf_a & state1__0_inf_b & state2_0_sp_state_c_inf ? _GEN_13 : _GEN_21; // @[FMAdd.scala 300:57]
+ wire [22:0] _GEN_26 = state1__0_inf_a & state1__0_inf_b & state2_0_sp_state_c_inf ? _GEN_14 : _GEN_22; // @[FMAdd.scala 300:57]
+ wire _GEN_28 = (state1__0_inf_a | state1__0_inf_b) & state2_0_sp_state_c_inf & state1__0_sign != state2_0_acm_sign |
+ _GEN_23; // @[FMAdd.scala 295:85 297:18]
+ wire [7:0] _GEN_29 = (state1__0_inf_a | state1__0_inf_b) & state2_0_sp_state_c_inf & state1__0_sign !=
+ state2_0_acm_sign ? 8'hff : _GEN_24; // @[FMAdd.scala 295:85 298:18]
+ wire [22:0] _GEN_30 = (state1__0_inf_a | state1__0_inf_b) & state2_0_sp_state_c_inf & state1__0_sign !=
+ state2_0_acm_sign ? 23'h400000 : _GEN_26; // @[FMAdd.scala 295:85 299:18]
+ wire state2_0_sp_state_sel = state1__0_nan | state2_0_sp_state_c_nan | _GEN_28; // @[FMAdd.scala 290:32 292:18]
+ wire [7:0] _GEN_33 = state1__0_nan | state2_0_sp_state_c_nan ? 8'hff : _GEN_29; // @[FMAdd.scala 290:32 293:18]
+ wire [22:0] _GEN_34 = state1__0_nan | state2_0_sp_state_c_nan ? 23'h400000 : _GEN_30; // @[FMAdd.scala 290:32 294:18]
wire [48:0] state2_0_ab_state_a_shbits = {state2_0_a_shl,1'h0}; // @[Cat.scala 31:58]
- wire [9:0] state2_0_ab_state_b_shdiff = state2_0_a_exp - state2_0_b_exp; // @[FMAdd.scala 356:26]
- wire [5:0] state2_0_ab_state_b_shamt = state2_0_ab_state_b_shdiff < 10'h40 ? state2_0_ab_state_b_shdiff[5:0] : 6'h3f; // @[FMAdd.scala 357:22]
- wire [111:0] _state2_0_ab_state_b_shmask_T_1 = 112'h1ffffffffffff << state2_0_ab_state_b_shamt; // @[FMAdd.scala 360:35]
- wire [48:0] state2_0_ab_state_b_shmask = ~_state2_0_ab_state_b_shmask_T_1[48:0]; // @[FMAdd.scala 360:20]
+ wire [9:0] state2_0_ab_state_b_shdiff = state2_0_a_exp - state2_0_b_exp; // @[FMAdd.scala 340:26]
+ wire [5:0] state2_0_ab_state_b_shamt = state2_0_ab_state_b_shdiff < 10'h40 ? state2_0_ab_state_b_shdiff[5:0] : 6'h3f; // @[FMAdd.scala 341:22]
+ wire [111:0] _state2_0_ab_state_b_shmask_T_1 = 112'h1ffffffffffff << state2_0_ab_state_b_shamt; // @[FMAdd.scala 344:35]
+ wire [48:0] state2_0_ab_state_b_shmask = ~_state2_0_ab_state_b_shmask_T_1[48:0]; // @[FMAdd.scala 344:20]
wire [48:0] _state2_0_ab_state_b_shbits_T = {state2_0_b_shl,1'h0}; // @[Cat.scala 31:58]
- wire [48:0] _state2_0_ab_state_b_shbits_T_1 = _state2_0_ab_state_b_shbits_T >> state2_0_ab_state_b_shamt; // @[FMAdd.scala 361:42]
- wire [48:0] _GEN_76 = {{1'd0}, state2_0_b_shl}; // @[FMAdd.scala 361:64]
- wire [48:0] _state2_0_ab_state_b_shbits_T_2 = _GEN_76 & state2_0_ab_state_b_shmask; // @[FMAdd.scala 361:64]
- wire [48:0] _GEN_77 = {{48'd0}, _state2_0_ab_state_b_shbits_T_2 != 49'h0}; // @[FMAdd.scala 361:54]
- wire [48:0] state2_0_ab_state_b_shbits = _state2_0_ab_state_b_shbits_T_1 | _GEN_77; // @[FMAdd.scala 361:54]
- wire state2_0_ab_state_add = state1__0_sign == state2_0_acm_sign; // @[FMAdd.scala 371:26]
- wire [9:0] state2_0_ba_state_b_shdiff = state2_0_b_exp - state2_0_a_exp; // @[FMAdd.scala 356:26]
- wire [5:0] state2_0_ba_state_b_shamt = state2_0_ba_state_b_shdiff < 10'h40 ? state2_0_ba_state_b_shdiff[5:0] : 6'h3f; // @[FMAdd.scala 357:22]
- wire [111:0] _state2_0_ba_state_b_shmask_T_1 = 112'h1ffffffffffff << state2_0_ba_state_b_shamt; // @[FMAdd.scala 360:35]
- wire [48:0] state2_0_ba_state_b_shmask = ~_state2_0_ba_state_b_shmask_T_1[48:0]; // @[FMAdd.scala 360:20]
- wire [48:0] _state2_0_ba_state_b_shbits_T_1 = state2_0_ab_state_a_shbits >> state2_0_ba_state_b_shamt; // @[FMAdd.scala 361:42]
- wire [48:0] _GEN_78 = {{1'd0}, state2_0_a_shl}; // @[FMAdd.scala 361:64]
- wire [48:0] _state2_0_ba_state_b_shbits_T_2 = _GEN_78 & state2_0_ba_state_b_shmask; // @[FMAdd.scala 361:64]
- wire [48:0] _GEN_79 = {{48'd0}, _state2_0_ba_state_b_shbits_T_2 != 49'h0}; // @[FMAdd.scala 361:54]
- wire [48:0] state2_0_ba_state_b_shbits = _state2_0_ba_state_b_shbits_T_1 | _GEN_79; // @[FMAdd.scala 361:54]
- wire state2_0_ba_state_add = state2_0_acm_sign == state1__0_sign; // @[FMAdd.scala 371:26]
- wire state2_0_ba_state_sub = state2_0_acm_sign != state1__0_sign; // @[FMAdd.scala 372:26]
- wire [9:0] _state2_0_sel_ab_T_1 = state1__0_exp - _GEN_74; // @[FMAdd.scala 274:36]
- wire [9:0] _state2_0_sel_ab_T_2 = _state2_0_b_exp_T_2 - 10'h1; // @[FMAdd.scala 274:51]
+ wire [48:0] _state2_0_ab_state_b_shbits_T_1 = _state2_0_ab_state_b_shbits_T >> state2_0_ab_state_b_shamt; // @[FMAdd.scala 345:42]
+ wire [48:0] _GEN_65 = {{1'd0}, state2_0_b_shl}; // @[FMAdd.scala 345:64]
+ wire [48:0] _state2_0_ab_state_b_shbits_T_2 = _GEN_65 & state2_0_ab_state_b_shmask; // @[FMAdd.scala 345:64]
+ wire [48:0] _GEN_66 = {{48'd0}, _state2_0_ab_state_b_shbits_T_2 != 49'h0}; // @[FMAdd.scala 345:54]
+ wire [48:0] state2_0_ab_state_b_shbits = _state2_0_ab_state_b_shbits_T_1 | _GEN_66; // @[FMAdd.scala 345:54]
+ wire state2_0_ab_state_add = state1__0_sign == state2_0_acm_sign; // @[FMAdd.scala 355:26]
+ wire [9:0] state2_0_ba_state_b_shdiff = state2_0_b_exp - state2_0_a_exp; // @[FMAdd.scala 340:26]
+ wire [5:0] state2_0_ba_state_b_shamt = state2_0_ba_state_b_shdiff < 10'h40 ? state2_0_ba_state_b_shdiff[5:0] : 6'h3f; // @[FMAdd.scala 341:22]
+ wire [111:0] _state2_0_ba_state_b_shmask_T_1 = 112'h1ffffffffffff << state2_0_ba_state_b_shamt; // @[FMAdd.scala 344:35]
+ wire [48:0] state2_0_ba_state_b_shmask = ~_state2_0_ba_state_b_shmask_T_1[48:0]; // @[FMAdd.scala 344:20]
+ wire [48:0] _state2_0_ba_state_b_shbits_T_1 = state2_0_ab_state_a_shbits >> state2_0_ba_state_b_shamt; // @[FMAdd.scala 345:42]
+ wire [48:0] _GEN_67 = {{1'd0}, state2_0_a_shl}; // @[FMAdd.scala 345:64]
+ wire [48:0] _state2_0_ba_state_b_shbits_T_2 = _GEN_67 & state2_0_ba_state_b_shmask; // @[FMAdd.scala 345:64]
+ wire [48:0] _GEN_68 = {{48'd0}, _state2_0_ba_state_b_shbits_T_2 != 49'h0}; // @[FMAdd.scala 345:54]
+ wire [48:0] state2_0_ba_state_b_shbits = _state2_0_ba_state_b_shbits_T_1 | _GEN_68; // @[FMAdd.scala 345:54]
+ wire state2_0_ba_state_add = state2_0_acm_sign == state1__0_sign; // @[FMAdd.scala 355:26]
+ wire state2_0_ba_state_sub = state2_0_acm_sign != state1__0_sign; // @[FMAdd.scala 356:26]
+ wire [9:0] _state2_0_sel_ab_T_1 = state1__0_exp - _GEN_63; // @[FMAdd.scala 258:36]
+ wire [9:0] _state2_0_sel_ab_T_2 = _state2_0_b_exp_T_2 - 10'h1; // @[FMAdd.scala 258:51]
wire state2_0_sel_ab = ~state2_0_sp_state_sel & ($signed(_state2_0_sel_ab_T_1) > $signed(_state2_0_sel_ab_T_2) |
- state2_0_a_exp == state2_0_b_exp & state2_0_a_shl >= state2_0_b_shl | state2_0_b_zero); // @[FMAdd.scala 274:26]
- wire [9:0] state2_0_sp_state_exp = {{2'd0}, _GEN_41}; // @[FMAdd.scala 286:22]
- wire [48:0] state2_0_sp_state_ain = {{26'd0}, _GEN_42}; // @[FMAdd.scala 286:22]
- wire [49:0] state3_0_add = state2_0_ain + state2_0_bin; // @[FMAdd.scala 389:26]
- wire [49:0] state3_0_sub = state2_0_ain - state2_0_bin; // @[FMAdd.scala 390:26]
- wire [48:0] _state3_0_result_man_T = state2_0_sel ? state2_0_ain : 49'h0; // @[FMAdd.scala 394:25]
- wire [49:0] _state3_0_result_man_T_1 = state2_0_add ? state3_0_add : 50'h0; // @[FMAdd.scala 395:25]
- wire [49:0] _GEN_80 = {{1'd0}, _state3_0_result_man_T}; // @[FMAdd.scala 394:55]
- wire [49:0] _state3_0_result_man_T_2 = _GEN_80 | _state3_0_result_man_T_1; // @[FMAdd.scala 394:55]
- wire [49:0] _state3_0_result_man_T_3 = state2_0_sub ? state3_0_sub : 50'h0; // @[FMAdd.scala 396:25]
- wire [49:0] state3_0_result_man = _state3_0_result_man_T_2 | _state3_0_result_man_T_3; // @[FMAdd.scala 395:48]
+ state2_0_a_exp == state2_0_b_exp & state2_0_a_shl >= state2_0_b_shl | state2_0_b_zero); // @[FMAdd.scala 258:26]
+ wire [9:0] state2_0_sp_state_exp = {{2'd0}, _GEN_33}; // @[FMAdd.scala 270:22]
+ wire [48:0] state2_0_sp_state_ain = {{26'd0}, _GEN_34}; // @[FMAdd.scala 270:22]
+ wire [49:0] state3_0_add = state2_0_ain + state2_0_bin; // @[FMAdd.scala 373:26]
+ wire [49:0] state3_0_sub = state2_0_ain - state2_0_bin; // @[FMAdd.scala 374:26]
+ wire [48:0] _state3_0_result_man_T = state2_0_sel ? state2_0_ain : 49'h0; // @[FMAdd.scala 378:25]
+ wire [49:0] _state3_0_result_man_T_1 = state2_0_add ? state3_0_add : 50'h0; // @[FMAdd.scala 379:25]
+ wire [49:0] _GEN_69 = {{1'd0}, _state3_0_result_man_T}; // @[FMAdd.scala 378:55]
+ wire [49:0] _state3_0_result_man_T_2 = _GEN_69 | _state3_0_result_man_T_1; // @[FMAdd.scala 378:55]
+ wire [49:0] _state3_0_result_man_T_3 = state2_0_sub ? state3_0_sub : 50'h0; // @[FMAdd.scala 380:25]
+ wire [49:0] state3_0_result_man = _state3_0_result_man_T_2 | _state3_0_result_man_T_3; // @[FMAdd.scala 379:48]
wire [2:0] _state3_0_T = {state2_0_sel,state2_0_add,state2_0_sub}; // @[Cat.scala 31:58]
wire [1:0] _state3_0_T_4 = _state3_0_T[1] + _state3_0_T[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_81 = {{1'd0}, _state3_0_T[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _state3_0_T_6 = _GEN_81 + _state3_0_T_4; // @[Bitwise.scala 48:55]
- wire [31:0] _GEN_82 = {{16'd0}, state3_0_result_man[31:16]}; // @[Bitwise.scala 105:31]
- wire [31:0] _state3_0_norm_clz_T_7 = _GEN_82 & 32'hffff; // @[Bitwise.scala 105:31]
+ wire [1:0] _GEN_70 = {{1'd0}, _state3_0_T[0]}; // @[Bitwise.scala 48:55]
+ wire [2:0] _state3_0_T_6 = _GEN_70 + _state3_0_T_4; // @[Bitwise.scala 48:55]
+ wire [31:0] _GEN_71 = {{16'd0}, state3_0_result_man[31:16]}; // @[Bitwise.scala 105:31]
+ wire [31:0] _state3_0_norm_clz_T_7 = _GEN_71 & 32'hffff; // @[Bitwise.scala 105:31]
wire [31:0] _state3_0_norm_clz_T_9 = {state3_0_result_man[15:0], 16'h0}; // @[Bitwise.scala 105:70]
wire [31:0] _state3_0_norm_clz_T_11 = _state3_0_norm_clz_T_9 & 32'hffff0000; // @[Bitwise.scala 105:80]
wire [31:0] _state3_0_norm_clz_T_12 = _state3_0_norm_clz_T_7 | _state3_0_norm_clz_T_11; // @[Bitwise.scala 105:39]
- wire [31:0] _GEN_83 = {{8'd0}, _state3_0_norm_clz_T_12[31:8]}; // @[Bitwise.scala 105:31]
- wire [31:0] _state3_0_norm_clz_T_17 = _GEN_83 & 32'hff00ff; // @[Bitwise.scala 105:31]
+ wire [31:0] _GEN_72 = {{8'd0}, _state3_0_norm_clz_T_12[31:8]}; // @[Bitwise.scala 105:31]
+ wire [31:0] _state3_0_norm_clz_T_17 = _GEN_72 & 32'hff00ff; // @[Bitwise.scala 105:31]
wire [31:0] _state3_0_norm_clz_T_19 = {_state3_0_norm_clz_T_12[23:0], 8'h0}; // @[Bitwise.scala 105:70]
wire [31:0] _state3_0_norm_clz_T_21 = _state3_0_norm_clz_T_19 & 32'hff00ff00; // @[Bitwise.scala 105:80]
wire [31:0] _state3_0_norm_clz_T_22 = _state3_0_norm_clz_T_17 | _state3_0_norm_clz_T_21; // @[Bitwise.scala 105:39]
- wire [31:0] _GEN_84 = {{4'd0}, _state3_0_norm_clz_T_22[31:4]}; // @[Bitwise.scala 105:31]
- wire [31:0] _state3_0_norm_clz_T_27 = _GEN_84 & 32'hf0f0f0f; // @[Bitwise.scala 105:31]
+ wire [31:0] _GEN_73 = {{4'd0}, _state3_0_norm_clz_T_22[31:4]}; // @[Bitwise.scala 105:31]
+ wire [31:0] _state3_0_norm_clz_T_27 = _GEN_73 & 32'hf0f0f0f; // @[Bitwise.scala 105:31]
wire [31:0] _state3_0_norm_clz_T_29 = {_state3_0_norm_clz_T_22[27:0], 4'h0}; // @[Bitwise.scala 105:70]
wire [31:0] _state3_0_norm_clz_T_31 = _state3_0_norm_clz_T_29 & 32'hf0f0f0f0; // @[Bitwise.scala 105:80]
wire [31:0] _state3_0_norm_clz_T_32 = _state3_0_norm_clz_T_27 | _state3_0_norm_clz_T_31; // @[Bitwise.scala 105:39]
- wire [31:0] _GEN_85 = {{2'd0}, _state3_0_norm_clz_T_32[31:2]}; // @[Bitwise.scala 105:31]
- wire [31:0] _state3_0_norm_clz_T_37 = _GEN_85 & 32'h33333333; // @[Bitwise.scala 105:31]
+ wire [31:0] _GEN_74 = {{2'd0}, _state3_0_norm_clz_T_32[31:2]}; // @[Bitwise.scala 105:31]
+ wire [31:0] _state3_0_norm_clz_T_37 = _GEN_74 & 32'h33333333; // @[Bitwise.scala 105:31]
wire [31:0] _state3_0_norm_clz_T_39 = {_state3_0_norm_clz_T_32[29:0], 2'h0}; // @[Bitwise.scala 105:70]
wire [31:0] _state3_0_norm_clz_T_41 = _state3_0_norm_clz_T_39 & 32'hcccccccc; // @[Bitwise.scala 105:80]
wire [31:0] _state3_0_norm_clz_T_42 = _state3_0_norm_clz_T_37 | _state3_0_norm_clz_T_41; // @[Bitwise.scala 105:39]
- wire [31:0] _GEN_86 = {{1'd0}, _state3_0_norm_clz_T_42[31:1]}; // @[Bitwise.scala 105:31]
- wire [31:0] _state3_0_norm_clz_T_47 = _GEN_86 & 32'h55555555; // @[Bitwise.scala 105:31]
+ wire [31:0] _GEN_75 = {{1'd0}, _state3_0_norm_clz_T_42[31:1]}; // @[Bitwise.scala 105:31]
+ wire [31:0] _state3_0_norm_clz_T_47 = _GEN_75 & 32'h55555555; // @[Bitwise.scala 105:31]
wire [31:0] _state3_0_norm_clz_T_49 = {_state3_0_norm_clz_T_42[30:0], 1'h0}; // @[Bitwise.scala 105:70]
wire [31:0] _state3_0_norm_clz_T_51 = _state3_0_norm_clz_T_49 & 32'haaaaaaaa; // @[Bitwise.scala 105:80]
wire [31:0] _state3_0_norm_clz_T_52 = _state3_0_norm_clz_T_47 | _state3_0_norm_clz_T_51; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_87 = {{8'd0}, state3_0_result_man[47:40]}; // @[Bitwise.scala 105:31]
- wire [15:0] _state3_0_norm_clz_T_58 = _GEN_87 & 16'hff; // @[Bitwise.scala 105:31]
+ wire [15:0] _GEN_76 = {{8'd0}, state3_0_result_man[47:40]}; // @[Bitwise.scala 105:31]
+ wire [15:0] _state3_0_norm_clz_T_58 = _GEN_76 & 16'hff; // @[Bitwise.scala 105:31]
wire [15:0] _state3_0_norm_clz_T_60 = {state3_0_result_man[39:32], 8'h0}; // @[Bitwise.scala 105:70]
wire [15:0] _state3_0_norm_clz_T_62 = _state3_0_norm_clz_T_60 & 16'hff00; // @[Bitwise.scala 105:80]
wire [15:0] _state3_0_norm_clz_T_63 = _state3_0_norm_clz_T_58 | _state3_0_norm_clz_T_62; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_88 = {{4'd0}, _state3_0_norm_clz_T_63[15:4]}; // @[Bitwise.scala 105:31]
- wire [15:0] _state3_0_norm_clz_T_68 = _GEN_88 & 16'hf0f; // @[Bitwise.scala 105:31]
+ wire [15:0] _GEN_77 = {{4'd0}, _state3_0_norm_clz_T_63[15:4]}; // @[Bitwise.scala 105:31]
+ wire [15:0] _state3_0_norm_clz_T_68 = _GEN_77 & 16'hf0f; // @[Bitwise.scala 105:31]
wire [15:0] _state3_0_norm_clz_T_70 = {_state3_0_norm_clz_T_63[11:0], 4'h0}; // @[Bitwise.scala 105:70]
wire [15:0] _state3_0_norm_clz_T_72 = _state3_0_norm_clz_T_70 & 16'hf0f0; // @[Bitwise.scala 105:80]
wire [15:0] _state3_0_norm_clz_T_73 = _state3_0_norm_clz_T_68 | _state3_0_norm_clz_T_72; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_89 = {{2'd0}, _state3_0_norm_clz_T_73[15:2]}; // @[Bitwise.scala 105:31]
- wire [15:0] _state3_0_norm_clz_T_78 = _GEN_89 & 16'h3333; // @[Bitwise.scala 105:31]
+ wire [15:0] _GEN_78 = {{2'd0}, _state3_0_norm_clz_T_73[15:2]}; // @[Bitwise.scala 105:31]
+ wire [15:0] _state3_0_norm_clz_T_78 = _GEN_78 & 16'h3333; // @[Bitwise.scala 105:31]
wire [15:0] _state3_0_norm_clz_T_80 = {_state3_0_norm_clz_T_73[13:0], 2'h0}; // @[Bitwise.scala 105:70]
wire [15:0] _state3_0_norm_clz_T_82 = _state3_0_norm_clz_T_80 & 16'hcccc; // @[Bitwise.scala 105:80]
wire [15:0] _state3_0_norm_clz_T_83 = _state3_0_norm_clz_T_78 | _state3_0_norm_clz_T_82; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_90 = {{1'd0}, _state3_0_norm_clz_T_83[15:1]}; // @[Bitwise.scala 105:31]
- wire [15:0] _state3_0_norm_clz_T_88 = _GEN_90 & 16'h5555; // @[Bitwise.scala 105:31]
+ wire [15:0] _GEN_79 = {{1'd0}, _state3_0_norm_clz_T_83[15:1]}; // @[Bitwise.scala 105:31]
+ wire [15:0] _state3_0_norm_clz_T_88 = _GEN_79 & 16'h5555; // @[Bitwise.scala 105:31]
wire [15:0] _state3_0_norm_clz_T_90 = {_state3_0_norm_clz_T_83[14:0], 1'h0}; // @[Bitwise.scala 105:70]
wire [15:0] _state3_0_norm_clz_T_92 = _state3_0_norm_clz_T_90 & 16'haaaa; // @[Bitwise.scala 105:80]
wire [15:0] _state3_0_norm_clz_T_93 = _state3_0_norm_clz_T_88 | _state3_0_norm_clz_T_92; // @[Bitwise.scala 105:39]
@@ -27195,20 +27061,20 @@
wire [5:0] _state3_0_norm_clz_T_191 = _state3_0_norm_clz_T_96[2] ? 6'h2 : _state3_0_norm_clz_T_190; // @[Mux.scala 47:70]
wire [5:0] _state3_0_norm_clz_T_192 = _state3_0_norm_clz_T_96[1] ? 6'h1 : _state3_0_norm_clz_T_191; // @[Mux.scala 47:70]
wire [5:0] _state3_0_norm_clz_T_193 = _state3_0_norm_clz_T_96[0] ? 6'h0 : _state3_0_norm_clz_T_192; // @[Mux.scala 47:70]
- wire [9:0] state3_0_norm_clz = state3_0_result_man[49] ? 10'h3ff : {{4'd0}, _state3_0_norm_clz_T_193}; // @[FMAdd.scala 402:23]
- wire [9:0] _state3_0_result_exp_s_T_1 = state2_0_exp - state3_0_norm_clz; // @[FMAdd.scala 407:35]
- wire [9:0] state3_0_result_exp_s = _state3_0_result_exp_s_T_1 + 10'h1; // @[FMAdd.scala 407:46]
- wire [8:0] state3_0_result_exp = state3_0_result_exp_s[9] ? 9'h0 : state3_0_result_exp_s[8:0]; // @[FMAdd.scala 410:25]
- wire state3_0_result_inf = state3_0_result_exp >= 9'hff; // @[FMAdd.scala 411:33]
- wire [7:0] state3_0_result_inf_exp = state3_0_result_inf ? 8'hff : 8'h0; // @[FMAdd.scala 412:29]
- wire [9:0] state3_0_result_shl_amt = state2_0_exp < state3_0_norm_clz ? state2_0_exp : state3_0_norm_clz; // @[FMAdd.scala 467:8]
- wire [21:0] state3_0_shl_mask = 22'h3fffff >> state3_0_result_shl_amt; // @[FMAdd.scala 417:33]
- wire [1072:0] _GEN_2 = {{1023'd0}, state3_0_result_man}; // @[FMAdd.scala 420:42]
- wire [1072:0] _state3_0_result_shl_man_grs_T = _GEN_2 << state3_0_result_shl_amt; // @[FMAdd.scala 420:42]
- wire [21:0] _state3_0_result_shl_man_grs_T_3 = state3_0_result_man[21:0] & state3_0_shl_mask; // @[FMAdd.scala 421:49]
- wire _state3_0_result_shl_man_grs_T_4 = _state3_0_result_shl_man_grs_T_3 != 22'h0; // @[FMAdd.scala 421:61]
- wire [26:0] _GEN_91 = {{26'd0}, _state3_0_result_shl_man_grs_T_4}; // @[FMAdd.scala 420:68]
- wire [26:0] state3_0_result_shl_man_grs = _state3_0_result_shl_man_grs_T[48:22] | _GEN_91; // @[FMAdd.scala 420:68]
+ wire [9:0] state3_0_norm_clz = state3_0_result_man[49] ? 10'h3ff : {{4'd0}, _state3_0_norm_clz_T_193}; // @[FMAdd.scala 386:23]
+ wire [9:0] _state3_0_result_exp_s_T_1 = state2_0_exp - state3_0_norm_clz; // @[FMAdd.scala 391:35]
+ wire [9:0] state3_0_result_exp_s = _state3_0_result_exp_s_T_1 + 10'h1; // @[FMAdd.scala 391:46]
+ wire [8:0] state3_0_result_exp = state3_0_result_exp_s[9] ? 9'h0 : state3_0_result_exp_s[8:0]; // @[FMAdd.scala 394:25]
+ wire state3_0_result_inf = state3_0_result_exp >= 9'hff; // @[FMAdd.scala 395:33]
+ wire [7:0] state3_0_result_inf_exp = state3_0_result_inf ? 8'hff : 8'h0; // @[FMAdd.scala 396:29]
+ wire [9:0] state3_0_result_shl_amt = state2_0_exp < state3_0_norm_clz ? state2_0_exp : state3_0_norm_clz; // @[FMAdd.scala 451:8]
+ wire [21:0] state3_0_shl_mask = 22'h3fffff >> state3_0_result_shl_amt; // @[FMAdd.scala 401:33]
+ wire [1072:0] _GEN_2 = {{1023'd0}, state3_0_result_man}; // @[FMAdd.scala 404:42]
+ wire [1072:0] _state3_0_result_shl_man_grs_T = _GEN_2 << state3_0_result_shl_amt; // @[FMAdd.scala 404:42]
+ wire [21:0] _state3_0_result_shl_man_grs_T_3 = state3_0_result_man[21:0] & state3_0_shl_mask; // @[FMAdd.scala 405:49]
+ wire _state3_0_result_shl_man_grs_T_4 = _state3_0_result_shl_man_grs_T_3 != 22'h0; // @[FMAdd.scala 405:61]
+ wire [26:0] _GEN_80 = {{26'd0}, _state3_0_result_shl_man_grs_T_4}; // @[FMAdd.scala 404:68]
+ wire [26:0] state3_0_result_shl_man_grs = _state3_0_result_shl_man_grs_T[48:22] | _GEN_80; // @[FMAdd.scala 404:68]
wire _state3_0_shl_round_round_T_1 = state3_0_result_shl_man_grs[2:0] != 3'h0; // @[FBase.scala 82:30]
wire _state3_0_shl_round_round_T_2 = state3_0_result_shl_man_grs[2:0] != 3'h0 & state2_0_sign; // @[FBase.scala 82:38]
wire _state3_0_shl_round_round_T_6 = _state3_0_shl_round_round_T_1 & ~state2_0_sign; // @[FBase.scala 83:38]
@@ -27217,26 +27083,26 @@
wire [3:0] state3_0_shl_round_round = {_state3_0_shl_round_round_T_2,_state3_0_shl_round_round_T_6,1'h0,
_state3_0_shl_round_round_T_11}; // @[Cat.scala 31:58]
wire state3_0_shl_round = state3_0_shl_round_round[0]; // @[FBase.scala 86:10]
- wire [23:0] _state3_0_result_shl_man_T_2 = state3_0_result_shl_man_grs[26:3] + 24'h1; // @[FMAdd.scala 425:66]
+ wire [23:0] _state3_0_result_shl_man_T_2 = state3_0_result_shl_man_grs[26:3] + 24'h1; // @[FMAdd.scala 409:66]
wire [23:0] state3_0_result_shl_man = state3_0_shl_round ? _state3_0_result_shl_man_T_2 : state3_0_result_shl_man_grs[
- 26:3]; // @[FMAdd.scala 425:29]
- wire [8:0] _state3_0_result_shl_exp_T_5 = state3_0_result_exp + 9'h1; // @[FMAdd.scala 427:41]
+ 26:3]; // @[FMAdd.scala 409:29]
+ wire [8:0] _state3_0_result_shl_exp_T_5 = state3_0_result_exp + 9'h1; // @[FMAdd.scala 411:41]
wire [8:0] state3_0_result_shl_exp = state3_0_shl_round & state3_0_result_shl_man_grs[26:3] == 24'hffffff ?
- _state3_0_result_shl_exp_T_5 : state3_0_result_exp; // @[FMAdd.scala 426:29]
- wire [9:0] _state3_0_result_shr_amt_T_1 = 10'h0 - state2_0_exp; // @[FMAdd.scala 430:42]
- wire [9:0] _state3_0_result_shr_amt_T_3 = 10'h0 - state3_0_norm_clz; // @[FMAdd.scala 430:53]
- wire [9:0] _state3_0_result_shr_amt_T_4 = 10'h0 - state2_0_exp; // @[FMAdd.scala 471:11]
- wire [9:0] _state3_0_result_shr_amt_T_5 = 10'h0 - state3_0_norm_clz; // @[FMAdd.scala 471:22]
+ _state3_0_result_shl_exp_T_5 : state3_0_result_exp; // @[FMAdd.scala 410:29]
+ wire [9:0] _state3_0_result_shr_amt_T_1 = 10'h0 - state2_0_exp; // @[FMAdd.scala 414:42]
+ wire [9:0] _state3_0_result_shr_amt_T_3 = 10'h0 - state3_0_norm_clz; // @[FMAdd.scala 414:53]
+ wire [9:0] _state3_0_result_shr_amt_T_4 = 10'h0 - state2_0_exp; // @[FMAdd.scala 455:11]
+ wire [9:0] _state3_0_result_shr_amt_T_5 = 10'h0 - state3_0_norm_clz; // @[FMAdd.scala 455:22]
wire [9:0] _state3_0_result_shr_amt_T_7 = $signed(_state3_0_result_shr_amt_T_4) > $signed(_state3_0_result_shr_amt_T_5
- ) ? _state3_0_result_shr_amt_T_1 : _state3_0_result_shr_amt_T_3; // @[FMAdd.scala 471:8]
- wire [9:0] state3_0_result_shr_amt = 10'h1b < _state3_0_result_shr_amt_T_7 ? 10'h1b : _state3_0_result_shr_amt_T_7; // @[FMAdd.scala 467:8]
- wire [1072:0] _state3_0_shr_mask_T_2 = 1073'h3ffffffc00000 << state3_0_result_shr_amt; // @[FMAdd.scala 431:50]
- wire [49:0] state3_0_shr_mask = ~_state3_0_shr_mask_T_2[49:0]; // @[FMAdd.scala 431:20]
- wire [27:0] _state3_0_result_shr_man_grs_T_1 = state3_0_result_man[49:22] >> state3_0_result_shr_amt; // @[FMAdd.scala 434:49]
- wire [49:0] _state3_0_result_shr_man_grs_T_4 = state3_0_result_man & state3_0_shr_mask; // @[FMAdd.scala 435:49]
- wire _state3_0_result_shr_man_grs_T_5 = _state3_0_result_shr_man_grs_T_4 != 50'h0; // @[FMAdd.scala 435:61]
- wire [26:0] _GEN_92 = {{26'd0}, _state3_0_result_shr_man_grs_T_5}; // @[FMAdd.scala 434:74]
- wire [26:0] state3_0_result_shr_man_grs = _state3_0_result_shr_man_grs_T_1[26:0] | _GEN_92; // @[FMAdd.scala 434:74]
+ ) ? _state3_0_result_shr_amt_T_1 : _state3_0_result_shr_amt_T_3; // @[FMAdd.scala 455:8]
+ wire [9:0] state3_0_result_shr_amt = 10'h1b < _state3_0_result_shr_amt_T_7 ? 10'h1b : _state3_0_result_shr_amt_T_7; // @[FMAdd.scala 451:8]
+ wire [1072:0] _state3_0_shr_mask_T_2 = 1073'h3ffffffc00000 << state3_0_result_shr_amt; // @[FMAdd.scala 415:50]
+ wire [49:0] state3_0_shr_mask = ~_state3_0_shr_mask_T_2[49:0]; // @[FMAdd.scala 415:20]
+ wire [27:0] _state3_0_result_shr_man_grs_T_1 = state3_0_result_man[49:22] >> state3_0_result_shr_amt; // @[FMAdd.scala 418:49]
+ wire [49:0] _state3_0_result_shr_man_grs_T_4 = state3_0_result_man & state3_0_shr_mask; // @[FMAdd.scala 419:49]
+ wire _state3_0_result_shr_man_grs_T_5 = _state3_0_result_shr_man_grs_T_4 != 50'h0; // @[FMAdd.scala 419:61]
+ wire [26:0] _GEN_81 = {{26'd0}, _state3_0_result_shr_man_grs_T_5}; // @[FMAdd.scala 418:74]
+ wire [26:0] state3_0_result_shr_man_grs = _state3_0_result_shr_man_grs_T_1[26:0] | _GEN_81; // @[FMAdd.scala 418:74]
wire _state3_0_shr_round_round_T_1 = state3_0_result_shr_man_grs[2:0] != 3'h0; // @[FBase.scala 82:30]
wire _state3_0_shr_round_round_T_2 = state3_0_result_shr_man_grs[2:0] != 3'h0 & state2_0_sign; // @[FBase.scala 82:38]
wire _state3_0_shr_round_round_T_6 = _state3_0_shr_round_round_T_1 & ~state2_0_sign; // @[FBase.scala 83:38]
@@ -27245,208 +27111,177 @@
wire [3:0] state3_0_shr_round_round = {_state3_0_shr_round_round_T_2,_state3_0_shr_round_round_T_6,1'h0,
_state3_0_shr_round_round_T_11}; // @[Cat.scala 31:58]
wire state3_0_shr_round = state3_0_shr_round_round[0]; // @[FBase.scala 86:10]
- wire [24:0] _state3_0_result_shr_man_T_1 = state3_0_result_shr_man_grs[26:3] + 24'h1; // @[FMAdd.scala 439:66]
+ wire [24:0] _state3_0_result_shr_man_T_1 = state3_0_result_shr_man_grs[26:3] + 24'h1; // @[FMAdd.scala 423:66]
wire [24:0] state3_0_result_shr_man = state3_0_shr_round ? _state3_0_result_shr_man_T_1 : {{1'd0},
- state3_0_result_shr_man_grs[26:3]}; // @[FMAdd.scala 439:29]
- wire _state3_0_result_shr_exp_T_2 = state3_0_result_shr_man_grs[25:3] == 23'h7fffff; // @[FMAdd.scala 441:55]
- wire _state3_0_result_shr_exp_T_3 = state3_0_shr_round & _state3_0_result_shr_exp_T_2; // @[FMAdd.scala 440:40]
- wire _state3_0_result_shr_exp_T_6 = state3_0_result_shr_man_grs[26] | state3_0_result_exp == 9'h0; // @[FMAdd.scala 442:54]
- wire _state3_0_result_shr_exp_T_7 = _state3_0_result_shr_exp_T_3 & _state3_0_result_shr_exp_T_6; // @[FMAdd.scala 441:70]
+ state3_0_result_shr_man_grs[26:3]}; // @[FMAdd.scala 423:29]
+ wire _state3_0_result_shr_exp_T_2 = state3_0_result_shr_man_grs[25:3] == 23'h7fffff; // @[FMAdd.scala 425:55]
+ wire _state3_0_result_shr_exp_T_3 = state3_0_shr_round & _state3_0_result_shr_exp_T_2; // @[FMAdd.scala 424:40]
+ wire _state3_0_result_shr_exp_T_6 = state3_0_result_shr_man_grs[26] | state3_0_result_exp == 9'h0; // @[FMAdd.scala 426:54]
+ wire _state3_0_result_shr_exp_T_7 = _state3_0_result_shr_exp_T_3 & _state3_0_result_shr_exp_T_6; // @[FMAdd.scala 425:70]
wire [8:0] state3_0_result_shr_exp = _state3_0_result_shr_exp_T_7 ? _state3_0_result_shl_exp_T_5 : state3_0_result_exp
- ; // @[FMAdd.scala 440:29]
- wire state3_0_sel_gez = ~state2_0_exp[9] & ~state3_0_norm_clz[9]; // @[FMAdd.scala 446:32]
- wire _state3_0_sel_shl_T = ~state2_0_sel; // @[FMAdd.scala 447:19]
- wire _state3_0_sel_shl_T_2 = state3_0_result_man != 50'h0; // @[FMAdd.scala 447:54]
- wire state3_0_sel_shl = ~state2_0_sel & state3_0_sel_gez & state3_0_result_man != 50'h0; // @[FMAdd.scala 447:40]
- wire state3_0_sel_shr = _state3_0_sel_shl_T & ~state3_0_sel_gez & _state3_0_sel_shl_T_2; // @[FMAdd.scala 448:40]
+ ; // @[FMAdd.scala 424:29]
+ wire state3_0_sel_gez = ~state2_0_exp[9] & ~state3_0_norm_clz[9]; // @[FMAdd.scala 430:32]
+ wire _state3_0_sel_shl_T = ~state2_0_sel; // @[FMAdd.scala 431:19]
+ wire _state3_0_sel_shl_T_2 = state3_0_result_man != 50'h0; // @[FMAdd.scala 431:54]
+ wire state3_0_sel_shl = ~state2_0_sel & state3_0_sel_gez & state3_0_result_man != 50'h0; // @[FMAdd.scala 431:40]
+ wire state3_0_sel_shr = _state3_0_sel_shl_T & ~state3_0_sel_gez & _state3_0_sel_shl_T_2; // @[FMAdd.scala 432:40]
wire [2:0] _state3_0_T_12 = {state2_0_sel,state3_0_sel_shl,state3_0_sel_shr}; // @[Cat.scala 31:58]
wire [1:0] _state3_0_T_16 = _state3_0_T_12[1] + _state3_0_T_12[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_93 = {{1'd0}, _state3_0_T_12[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _state3_0_T_18 = _GEN_93 + _state3_0_T_16; // @[Bitwise.scala 48:55]
- wire [9:0] _state3_0_state3_exp_T = state2_0_sel ? state2_0_exp : 10'h0; // @[FMAdd.scala 452:22]
- wire [8:0] _GEN_94 = {{1'd0}, state3_0_result_inf_exp}; // @[FMAdd.scala 453:47]
- wire [8:0] _state3_0_state3_exp_T_1 = state3_0_result_shl_exp | _GEN_94; // @[FMAdd.scala 453:47]
- wire [8:0] _state3_0_state3_exp_T_2 = state3_0_sel_shl ? _state3_0_state3_exp_T_1 : 9'h0; // @[FMAdd.scala 453:22]
- wire [9:0] _GEN_95 = {{1'd0}, _state3_0_state3_exp_T_2}; // @[FMAdd.scala 452:49]
- wire [9:0] _state3_0_state3_exp_T_3 = _state3_0_state3_exp_T | _GEN_95; // @[FMAdd.scala 452:49]
- wire [8:0] _state3_0_state3_exp_T_4 = state3_0_result_shr_exp | _GEN_94; // @[FMAdd.scala 454:47]
- wire [8:0] _state3_0_state3_exp_T_5 = state3_0_sel_shr ? _state3_0_state3_exp_T_4 : 9'h0; // @[FMAdd.scala 454:22]
- wire [9:0] _GEN_97 = {{1'd0}, _state3_0_state3_exp_T_5}; // @[FMAdd.scala 453:70]
- wire [9:0] _state3_0_state3_exp_T_6 = _state3_0_state3_exp_T_3 | _GEN_97; // @[FMAdd.scala 453:70]
- wire _state3_0_state3_man_T_1 = ~state3_0_result_inf; // @[FMAdd.scala 456:34]
- wire [23:0] _state3_0_state3_man_T_3 = state3_0_sel_shl & ~state3_0_result_inf ? state3_0_result_shl_man : 24'h0; // @[FMAdd.scala 456:22]
- wire [48:0] _GEN_98 = {{25'd0}, _state3_0_state3_man_T_3}; // @[FMAdd.scala 455:49]
- wire [48:0] _state3_0_state3_man_T_4 = _state3_0_result_man_T | _GEN_98; // @[FMAdd.scala 455:49]
- wire [24:0] _state3_0_state3_man_T_7 = state3_0_sel_shr & _state3_0_state3_man_T_1 ? state3_0_result_shr_man : 25'h0; // @[FMAdd.scala 457:22]
- wire [48:0] _GEN_99 = {{24'd0}, _state3_0_state3_man_T_7}; // @[FMAdd.scala 456:68]
- wire [48:0] _state3_0_state3_man_T_8 = _state3_0_state3_man_T_4 | _GEN_99; // @[FMAdd.scala 456:68]
- wire [22:0] state3_0_state3_man = _state3_0_state3_man_T_8[22:0]; // @[FMAdd.scala 383:22 455:16]
- wire [7:0] state3_0_state3_exp = _state3_0_state3_exp_T_6[7:0]; // @[FMAdd.scala 383:22 452:16]
- wire _io_ina_ready_T_2 = _update1_T_3 | io_inc_valid & io_inc_ready; // @[FMAdd.scala 112:45]
+ wire [1:0] _GEN_82 = {{1'd0}, _state3_0_T_12[0]}; // @[Bitwise.scala 48:55]
+ wire [2:0] _state3_0_T_18 = _GEN_82 + _state3_0_T_16; // @[Bitwise.scala 48:55]
+ wire [9:0] _state3_0_state3_exp_T = state2_0_sel ? state2_0_exp : 10'h0; // @[FMAdd.scala 436:22]
+ wire [8:0] _GEN_83 = {{1'd0}, state3_0_result_inf_exp}; // @[FMAdd.scala 437:47]
+ wire [8:0] _state3_0_state3_exp_T_1 = state3_0_result_shl_exp | _GEN_83; // @[FMAdd.scala 437:47]
+ wire [8:0] _state3_0_state3_exp_T_2 = state3_0_sel_shl ? _state3_0_state3_exp_T_1 : 9'h0; // @[FMAdd.scala 437:22]
+ wire [9:0] _GEN_84 = {{1'd0}, _state3_0_state3_exp_T_2}; // @[FMAdd.scala 436:49]
+ wire [9:0] _state3_0_state3_exp_T_3 = _state3_0_state3_exp_T | _GEN_84; // @[FMAdd.scala 436:49]
+ wire [8:0] _state3_0_state3_exp_T_4 = state3_0_result_shr_exp | _GEN_83; // @[FMAdd.scala 438:47]
+ wire [8:0] _state3_0_state3_exp_T_5 = state3_0_sel_shr ? _state3_0_state3_exp_T_4 : 9'h0; // @[FMAdd.scala 438:22]
+ wire [9:0] _GEN_86 = {{1'd0}, _state3_0_state3_exp_T_5}; // @[FMAdd.scala 437:70]
+ wire [9:0] _state3_0_state3_exp_T_6 = _state3_0_state3_exp_T_3 | _GEN_86; // @[FMAdd.scala 437:70]
+ wire _state3_0_state3_man_T_1 = ~state3_0_result_inf; // @[FMAdd.scala 440:34]
+ wire [23:0] _state3_0_state3_man_T_3 = state3_0_sel_shl & ~state3_0_result_inf ? state3_0_result_shl_man : 24'h0; // @[FMAdd.scala 440:22]
+ wire [48:0] _GEN_87 = {{25'd0}, _state3_0_state3_man_T_3}; // @[FMAdd.scala 439:49]
+ wire [48:0] _state3_0_state3_man_T_4 = _state3_0_result_man_T | _GEN_87; // @[FMAdd.scala 439:49]
+ wire [24:0] _state3_0_state3_man_T_7 = state3_0_sel_shr & _state3_0_state3_man_T_1 ? state3_0_result_shr_man : 25'h0; // @[FMAdd.scala 441:22]
+ wire [48:0] _GEN_88 = {{24'd0}, _state3_0_state3_man_T_7}; // @[FMAdd.scala 440:68]
+ wire [48:0] _state3_0_state3_man_T_8 = _state3_0_state3_man_T_4 | _GEN_88; // @[FMAdd.scala 440:68]
+ wire [22:0] state3_0_state3_man = _state3_0_state3_man_T_8[22:0]; // @[FMAdd.scala 367:22 439:16]
+ wire [7:0] state3_0_state3_exp = _state3_0_state3_exp_T_6[7:0]; // @[FMAdd.scala 367:22 436:16]
+ wire _io_ina_ready_T_2 = _update1_T_3 | io_inc_valid & io_inc_ready; // @[FMAdd.scala 96:45]
wire [8:0] io_out_bits_0_hi = {state3_0_sign,state3_0_exp}; // @[Cat.scala 31:58]
- wire _GEN_100 = update1 & io_op_bits[4]; // @[BFDot.scala 62:13]
- wire _GEN_107 = active2 & _bfst_T_30; // @[FMAdd.scala 398:11]
- assign io_ina_ready = io_inb_valid & (_update1_T_3 | io_inc_valid & io_inc_ready); // @[FMAdd.scala 112:32]
- assign io_inb_ready = io_ina_valid & _io_ina_ready_T_2; // @[FMAdd.scala 113:32]
- assign io_inc_ready = active1; // @[FMAdd.scala 114:27]
- assign io_out_valid = active3; // @[FMAdd.scala 116:16]
+ wire _GEN_89 = active2 & ~reset; // @[FMAdd.scala 382:11]
+ assign io_ina_ready = io_inb_valid & (_update1_T_3 | io_inc_valid & io_inc_ready); // @[FMAdd.scala 96:32]
+ assign io_inb_ready = io_ina_valid & _io_ina_ready_T_2; // @[FMAdd.scala 97:32]
+ assign io_inc_ready = active1; // @[FMAdd.scala 98:27]
+ assign io_out_valid = active3; // @[FMAdd.scala 100:16]
assign io_out_bits_0 = {io_out_bits_0_hi,state3_0_man}; // @[Cat.scala 31:58]
always @(posedge clock) begin
- if (update1) begin // @[FMAdd.scala 58:18]
- op1 <= io_op_bits; // @[FMAdd.scala 59:9]
+ if (update1) begin // @[FMAdd.scala 57:18]
+ op1 <= io_op_bits; // @[FMAdd.scala 58:9]
end
- if (update1) begin // @[FMAdd.scala 83:20]
- if (io_op_bits[4]) begin // @[FMAdd.scala 87:40]
- state1__0_sign <= bfst__sign; // @[FMAdd.scala 90:19]
- end else if (state1_0_nan_a) begin // @[FMAdd.scala 203:24]
+ if (update1) begin // @[FMAdd.scala 79:20]
+ if (state1_0_nan_a) begin // @[FMAdd.scala 187:24]
state1__0_sign <= state1_0_sign_a;
- end else if (state1_0_nan_b) begin // @[FMAdd.scala 203:43]
+ end else if (state1_0_nan_b) begin // @[FMAdd.scala 187:43]
state1__0_sign <= state1_0_sign_b;
end else begin
state1__0_sign <= state1_0_sign;
end
end
- if (update1) begin // @[FMAdd.scala 83:20]
- if (io_op_bits[4]) begin // @[FMAdd.scala 87:40]
- state1__0_exp <= {{2'd0}, bfst__exp}; // @[FMAdd.scala 91:19]
- end else if (state1_0_nan_a) begin // @[FMAdd.scala 204:24]
+ if (update1) begin // @[FMAdd.scala 79:20]
+ if (state1_0_nan_a) begin // @[FMAdd.scala 188:24]
state1__0_exp <= {{2'd0}, mul_sina[30:23]};
- end else if (state1_0_nan_b) begin // @[FMAdd.scala 204:42]
+ end else if (state1_0_nan_b) begin // @[FMAdd.scala 188:42]
state1__0_exp <= {{2'd0}, mul_sina[30:23]};
+ end else if (~state1_0_zero) begin // @[FMAdd.scala 181:20]
+ state1__0_exp <= state1_0_exp;
end else begin
- state1__0_exp <= state1_0_exp_z;
+ state1__0_exp <= 10'h0;
end
end
- if (update1) begin // @[FMAdd.scala 83:20]
- if (io_op_bits[4]) begin // @[FMAdd.scala 87:40]
- state1__0_mul <= bfst__mul; // @[FMAdd.scala 92:19]
- end else if (state1_0_nan_a) begin // @[FMAdd.scala 205:24]
+ if (update1) begin // @[FMAdd.scala 79:20]
+ if (state1_0_nan_a) begin // @[FMAdd.scala 189:24]
state1__0_mul <= {{25'd0}, mul_sina[22:0]};
- end else if (state1_0_nan_b) begin // @[FMAdd.scala 205:42]
+ end else if (state1_0_nan_b) begin // @[FMAdd.scala 189:42]
state1__0_mul <= {{25'd0}, mul_inb[22:0]};
+ end else if (_state1_0_exp_z_T) begin // @[FMAdd.scala 182:20]
+ state1__0_mul <= state1_0_mul;
end else begin
- state1__0_mul <= state1_0_mul_z;
+ state1__0_mul <= 48'h0;
end
end
- if (update1) begin // @[FMAdd.scala 83:20]
- if (io_op_bits[4]) begin // @[FMAdd.scala 87:40]
- state1__0_zero <= bfst__exp == 8'h0 & bfst__mul == 48'h0; // @[FMAdd.scala 93:19]
- end else begin
- state1__0_zero <= state1_0_zero; // @[FMAdd.scala 85:11]
- end
+ if (update1) begin // @[FMAdd.scala 79:20]
+ state1__0_zero <= state1_0_zero; // @[FMAdd.scala 81:11]
end
- if (update1) begin // @[FMAdd.scala 83:20]
- if (io_op_bits[4]) begin // @[FMAdd.scala 87:40]
- state1__0_inf_a <= bfst__exp == 8'hff; // @[FMAdd.scala 94:19]
- end else begin
- state1__0_inf_a <= state1_0_inf_a; // @[FMAdd.scala 85:11]
- end
+ if (update1) begin // @[FMAdd.scala 79:20]
+ state1__0_inf_a <= state1_0_inf_a; // @[FMAdd.scala 81:11]
end
- if (update1) begin // @[FMAdd.scala 83:20]
- if (io_op_bits[4]) begin // @[FMAdd.scala 87:40]
- state1__0_inf_b <= 1'h0; // @[FMAdd.scala 95:19]
- end else begin
- state1__0_inf_b <= state1_0_inf_b; // @[FMAdd.scala 85:11]
- end
+ if (update1) begin // @[FMAdd.scala 79:20]
+ state1__0_inf_b <= state1_0_inf_b; // @[FMAdd.scala 81:11]
end
- if (update1) begin // @[FMAdd.scala 83:20]
- if (io_op_bits[4]) begin // @[FMAdd.scala 87:40]
- state1__0_nan <= 1'h0; // @[FMAdd.scala 96:19]
- end else begin
- state1__0_nan <= state1_0_state1_nan; // @[FMAdd.scala 85:11]
- end
+ if (update1) begin // @[FMAdd.scala 79:20]
+ state1__0_nan <= state1_0_state1_nan; // @[FMAdd.scala 81:11]
end
- if (update2) begin // @[FMAdd.scala 100:20]
- if (state2_0_sp_state_sel) begin // @[FMAdd.scala 275:21]
- if (state1__0_nan | state2_0_sp_state_c_nan) begin // @[FMAdd.scala 306:32]
- state2_0_sign <= 1'h0; // @[FMAdd.scala 307:19]
+ if (update2) begin // @[FMAdd.scala 84:20]
+ if (state2_0_sp_state_sel) begin // @[FMAdd.scala 259:21]
+ if (state1__0_nan | state2_0_sp_state_c_nan) begin // @[FMAdd.scala 290:32]
+ state2_0_sign <= 1'h0; // @[FMAdd.scala 291:19]
end else if ((state1__0_inf_a | state1__0_inf_b) & state2_0_sp_state_c_inf & state1__0_sign != state2_0_acm_sign
- ) begin // @[FMAdd.scala 311:85]
- state2_0_sign <= 1'h0; // @[FMAdd.scala 312:19]
+ ) begin // @[FMAdd.scala 295:85]
+ state2_0_sign <= 1'h0; // @[FMAdd.scala 296:19]
end else begin
- state2_0_sign <= _GEN_33;
+ state2_0_sign <= _GEN_25;
end
- end else if (state2_0_sel_ab) begin // @[FMAdd.scala 275:43]
+ end else if (state2_0_sel_ab) begin // @[FMAdd.scala 259:43]
state2_0_sign <= state1__0_sign;
end else begin
state2_0_sign <= state2_0_acm_sign;
end
end
- if (update2) begin // @[FMAdd.scala 100:20]
- if (state2_0_sp_state_sel) begin // @[FMAdd.scala 275:21]
+ if (update2) begin // @[FMAdd.scala 84:20]
+ if (state2_0_sp_state_sel) begin // @[FMAdd.scala 259:21]
state2_0_exp <= state2_0_sp_state_exp;
- end else if (state2_0_sel_ab) begin // @[FMAdd.scala 275:43]
+ end else if (state2_0_sel_ab) begin // @[FMAdd.scala 259:43]
state2_0_exp <= state2_0_a_exp;
end else begin
state2_0_exp <= state2_0_b_exp;
end
end
- if (update2) begin // @[FMAdd.scala 100:20]
- if (state2_0_sp_state_sel) begin // @[FMAdd.scala 275:21]
+ if (update2) begin // @[FMAdd.scala 84:20]
+ if (state2_0_sp_state_sel) begin // @[FMAdd.scala 259:21]
state2_0_ain <= state2_0_sp_state_ain;
- end else if (state2_0_sel_ab) begin // @[FMAdd.scala 275:43]
+ end else if (state2_0_sel_ab) begin // @[FMAdd.scala 259:43]
state2_0_ain <= state2_0_ab_state_a_shbits;
end else begin
state2_0_ain <= _state2_0_ab_state_b_shbits_T;
end
end
- if (update2) begin // @[FMAdd.scala 100:20]
- if (state2_0_sp_state_sel) begin // @[FMAdd.scala 275:21]
+ if (update2) begin // @[FMAdd.scala 84:20]
+ if (state2_0_sp_state_sel) begin // @[FMAdd.scala 259:21]
state2_0_bin <= 49'h0;
- end else if (state2_0_sel_ab) begin // @[FMAdd.scala 275:43]
+ end else if (state2_0_sel_ab) begin // @[FMAdd.scala 259:43]
state2_0_bin <= state2_0_ab_state_b_shbits;
end else begin
state2_0_bin <= state2_0_ba_state_b_shbits;
end
end
- if (update2) begin // @[FMAdd.scala 100:20]
- state2_0_sel <= state2_0_sp_state_sel; // @[FMAdd.scala 103:11]
+ if (update2) begin // @[FMAdd.scala 84:20]
+ state2_0_sel <= state2_0_sp_state_sel; // @[FMAdd.scala 87:11]
end
- if (update2) begin // @[FMAdd.scala 100:20]
- if (state2_0_sp_state_sel) begin // @[FMAdd.scala 275:21]
+ if (update2) begin // @[FMAdd.scala 84:20]
+ if (state2_0_sp_state_sel) begin // @[FMAdd.scala 259:21]
state2_0_add <= 1'h0;
- end else if (state2_0_sel_ab) begin // @[FMAdd.scala 275:43]
+ end else if (state2_0_sel_ab) begin // @[FMAdd.scala 259:43]
state2_0_add <= state2_0_ab_state_add;
end else begin
state2_0_add <= state2_0_ba_state_add;
end
end
- if (update2) begin // @[FMAdd.scala 100:20]
- if (state2_0_sp_state_sel) begin // @[FMAdd.scala 275:21]
+ if (update2) begin // @[FMAdd.scala 84:20]
+ if (state2_0_sp_state_sel) begin // @[FMAdd.scala 259:21]
state2_0_sub <= 1'h0;
- end else if (state2_0_sel_ab) begin // @[FMAdd.scala 275:43]
+ end else if (state2_0_sel_ab) begin // @[FMAdd.scala 259:43]
state2_0_sub <= _state2_0_sp_state_T_3;
end else begin
state2_0_sub <= state2_0_ba_state_sub;
end
end
- if (active2) begin // @[FMAdd.scala 106:20]
- state3_0_sign <= state2_0_sign; // @[FMAdd.scala 107:11]
+ if (active2) begin // @[FMAdd.scala 90:20]
+ state3_0_sign <= state2_0_sign; // @[FMAdd.scala 91:11]
end
- if (active2) begin // @[FMAdd.scala 106:20]
- state3_0_exp <= state3_0_state3_exp; // @[FMAdd.scala 107:11]
+ if (active2) begin // @[FMAdd.scala 90:20]
+ state3_0_exp <= state3_0_state3_exp; // @[FMAdd.scala 91:11]
end
- if (active2) begin // @[FMAdd.scala 106:20]
- state3_0_man <= state3_0_state3_man; // @[FMAdd.scala 107:11]
+ if (active2) begin // @[FMAdd.scala 90:20]
+ state3_0_man <= state3_0_state3_man; // @[FMAdd.scala 91:11]
end
`ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (update1 & io_op_bits[4] & _bfst_T_27 & ~reset) begin
- $fwrite(32'h80000002,"Select = %b : %x %x %x %x\n",_bfst_T_4,dot_ina[15:0],dot_inb[15:0],dot_ina[31:16],
- dot_inb[31:16]); // @[BFDot.scala 62:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
- if (_GEN_100 & _bfst_T_30 & ~(_bfst_T_25 == 4'h1)) begin
- $fatal; // @[BFDot.scala 64:11]
+ if (active2 & ~reset & ~(_state3_0_T_6[1:0] <= 2'h1)) begin
+ $fatal; // @[FMAdd.scala 382:11]
end
`ifdef STOP_COND
end
@@ -27456,32 +27291,10 @@
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
- if (_GEN_100 & _bfst_T_30 & ~(_bfst_T_25 == 4'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at BFDot.scala:64 assert(PopCount(select.asUInt) === 1.U)\n"); // @[BFDot.scala 64:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (active2 & _bfst_T_30 & ~(_state3_0_T_6[1:0] <= 2'h1)) begin
- $fatal; // @[FMAdd.scala 398:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (active2 & _bfst_T_30 & ~(_state3_0_T_6[1:0] <= 2'h1)) begin
+ if (active2 & ~reset & ~(_state3_0_T_6[1:0] <= 2'h1)) begin
$fwrite(32'h80000002,
- "Assertion failed\n at FMAdd.scala:398 assert(PopCount(Cat(state2.sel, state2.add, state2.sub)) <= 1.U)\n"
- ); // @[FMAdd.scala 398:11]
+ "Assertion failed\n at FMAdd.scala:382 assert(PopCount(Cat(state2.sel, state2.add, state2.sub)) <= 1.U)\n"
+ ); // @[FMAdd.scala 382:11]
end
`ifdef PRINTF_COND
end
@@ -27491,8 +27304,8 @@
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
- if (_GEN_107 & ~(_state3_0_T_18[1:0] <= 2'h1)) begin
- $fatal; // @[FMAdd.scala 449:11]
+ if (_GEN_89 & ~(_state3_0_T_18[1:0] <= 2'h1)) begin
+ $fatal; // @[FMAdd.scala 433:11]
end
`ifdef STOP_COND
end
@@ -27502,9 +27315,9 @@
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
- if (_GEN_107 & ~(_state3_0_T_18[1:0] <= 2'h1)) begin
+ if (_GEN_89 & ~(_state3_0_T_18[1:0] <= 2'h1)) begin
$fwrite(32'h80000002,
- "Assertion failed\n at FMAdd.scala:449 assert(PopCount(Cat(sel_ain, sel_shl, sel_shr)) <= 1.U)\n"); // @[FMAdd.scala 449:11]
+ "Assertion failed\n at FMAdd.scala:433 assert(PopCount(Cat(sel_ain, sel_shl, sel_shr)) <= 1.U)\n"); // @[FMAdd.scala 433:11]
end
`ifdef PRINTF_COND
end
@@ -27512,24 +27325,24 @@
`endif // SYNTHESIS
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[FMAdd.scala 46:29]
- active1 <= 1'h0; // @[FMAdd.scala 47:13]
- end else if (update1 | update2) begin // @[FMAdd.scala 33:24]
+ if (reset) begin // @[FMAdd.scala 45:29]
+ active1 <= 1'h0; // @[FMAdd.scala 46:13]
+ end else if (update1 | update2) begin // @[FMAdd.scala 32:24]
active1 <= update1;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[FMAdd.scala 50:29]
- active2 <= 1'h0; // @[FMAdd.scala 51:13]
- end else if (update2 | active2) begin // @[FMAdd.scala 34:24]
+ if (reset) begin // @[FMAdd.scala 49:29]
+ active2 <= 1'h0; // @[FMAdd.scala 50:13]
+ end else if (update2 | active2) begin // @[FMAdd.scala 33:24]
active2 <= update2;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[FMAdd.scala 54:34]
- active3 <= 1'h0; // @[FMAdd.scala 55:13]
+ if (reset) begin // @[FMAdd.scala 53:34]
+ active3 <= 1'h0; // @[FMAdd.scala 54:13]
end else begin
- active3 <= active2; // @[FMAdd.scala 35:24]
+ active3 <= active2; // @[FMAdd.scala 34:24]
end
end
// Register and memory initialization
@@ -27575,7 +27388,7 @@
_RAND_2 = {1{`RANDOM}};
active3 = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
- op1 = _RAND_3[4:0];
+ op1 = _RAND_3[3:0];
_RAND_4 = {1{`RANDOM}};
state1__0_sign = _RAND_4[0:0];
_RAND_5 = {1{`RANDOM}};
@@ -27646,12 +27459,12 @@
reg [31:0] mem_0; // @[Slice.scala 27:16]
wire empty = ipos == opos; // @[Slice.scala 29:20]
wire ivalid = io_in_valid & io_in_ready; // @[Slice.scala 31:28]
- assign io_in_ready = 1'h1; // @[Slice.scala 93:28]
- assign io_out_valid = ~empty; // @[Slice.scala 107:21]
- assign io_out_bits = mem_0; // @[Slice.scala 108:18]
+ assign io_in_ready = 1'h1; // @[Slice.scala 74:28]
+ assign io_out_valid = ~empty; // @[Slice.scala 88:21]
+ assign io_out_bits = mem_0; // @[Slice.scala 89:18]
always @(posedge clock) begin
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0 <= io_in_bits; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0 <= io_in_bits; // @[Slice.scala 80:14]
end
end
always @(posedge clock or posedge reset) begin
@@ -27740,7 +27553,7 @@
wire fmadd_clock; // @[FMAdd.scala 8:18]
wire fmadd_reset; // @[FMAdd.scala 8:18]
wire fmadd_io_op_valid; // @[FMAdd.scala 8:18]
- wire [4:0] fmadd_io_op_bits; // @[FMAdd.scala 8:18]
+ wire [3:0] fmadd_io_op_bits; // @[FMAdd.scala 8:18]
wire fmadd_io_ina_ready; // @[FMAdd.scala 8:18]
wire fmadd_io_ina_valid; // @[FMAdd.scala 8:18]
wire [31:0] fmadd_io_ina_bits_0; // @[FMAdd.scala 8:18]
@@ -27771,9 +27584,9 @@
wire op_1 = io_in_op[3]; // @[FMAdd.scala 39:33]
wire op_2 = io_in_op[4]; // @[FMAdd.scala 40:33]
wire op_3 = io_in_op[5]; // @[FMAdd.scala 41:33]
- wire [1:0] fmadd_io_op_bits_lo = {op_1,op_0}; // @[FMAdd.scala 45:26]
- wire [2:0] fmadd_io_op_bits_hi = {1'h0,op_3,op_2}; // @[FMAdd.scala 45:26]
- wire _T_4 = ~reset; // @[FMAdd.scala 70:9]
+ wire [1:0] fmadd_io_op_bits_lo = {op_1,op_0}; // @[FMAdd.scala 44:26]
+ wire [1:0] fmadd_io_op_bits_hi = {op_3,op_2}; // @[FMAdd.scala 44:26]
+ wire _T_4 = ~reset; // @[FMAdd.scala 69:9]
FMAdd fmadd ( // @[FMAdd.scala 8:18]
.clock(fmadd_clock),
.reset(fmadd_reset),
@@ -27810,34 +27623,57 @@
.io_out_valid(data_io_out_valid),
.io_out_bits(data_io_out_bits)
);
- assign io_out_valid = fmadd_io_out_valid; // @[FMAdd.scala 62:16]
- assign io_out_addr = addr_io_out_bits; // @[FMAdd.scala 63:15]
- assign io_out_fd = fmadd_io_out_bits_0; // @[FMAdd.scala 64:13]
+ assign io_out_valid = fmadd_io_out_valid; // @[FMAdd.scala 61:16]
+ assign io_out_addr = addr_io_out_bits; // @[FMAdd.scala 62:15]
+ assign io_out_fd = fmadd_io_out_bits_0; // @[FMAdd.scala 63:13]
assign fmadd_clock = clock;
assign fmadd_reset = reset;
- assign fmadd_io_op_valid = io_in_valid; // @[FMAdd.scala 44:21]
- assign fmadd_io_op_bits = {fmadd_io_op_bits_hi,fmadd_io_op_bits_lo}; // @[FMAdd.scala 45:26]
- assign fmadd_io_ina_valid = io_in_valid; // @[FMAdd.scala 48:22]
- assign fmadd_io_ina_bits_0 = io_in_fs1; // @[FMAdd.scala 52:24]
- assign fmadd_io_inb_valid = io_in_valid; // @[FMAdd.scala 49:22]
- assign fmadd_io_inb_bits_0 = io_in_fs2; // @[FMAdd.scala 53:24]
- assign fmadd_io_inc_valid = data_io_out_valid; // @[FMAdd.scala 50:22]
- assign fmadd_io_inc_bits_0 = data_io_out_bits; // @[FMAdd.scala 54:24]
+ assign fmadd_io_op_valid = io_in_valid; // @[FMAdd.scala 43:21]
+ assign fmadd_io_op_bits = {fmadd_io_op_bits_hi,fmadd_io_op_bits_lo}; // @[FMAdd.scala 44:26]
+ assign fmadd_io_ina_valid = io_in_valid; // @[FMAdd.scala 47:22]
+ assign fmadd_io_ina_bits_0 = io_in_fs1; // @[FMAdd.scala 51:24]
+ assign fmadd_io_inb_valid = io_in_valid; // @[FMAdd.scala 48:22]
+ assign fmadd_io_inb_bits_0 = io_in_fs2; // @[FMAdd.scala 52:24]
+ assign fmadd_io_inc_valid = data_io_out_valid; // @[FMAdd.scala 49:22]
+ assign fmadd_io_inc_bits_0 = data_io_out_bits; // @[FMAdd.scala 53:24]
assign addr_clock = clock;
assign addr_reset = reset;
- assign addr_io_in_valid = io_in_valid; // @[FMAdd.scala 56:20]
- assign addr_io_in_bits = io_in_addr; // @[FMAdd.scala 57:19]
- assign addr_io_out_ready = io_out_valid; // @[FMAdd.scala 66:21]
+ assign addr_io_in_valid = io_in_valid; // @[FMAdd.scala 55:20]
+ assign addr_io_in_bits = io_in_addr; // @[FMAdd.scala 56:19]
+ assign addr_io_out_ready = io_out_valid; // @[FMAdd.scala 65:21]
assign data_clock = clock;
assign data_reset = reset;
- assign data_io_in_valid = io_in_valid; // @[FMAdd.scala 59:20]
- assign data_io_in_bits = io_in_op[8] ? 32'h0 : io_in_fs3; // @[FMAdd.scala 60:25]
+ assign data_io_in_valid = io_in_valid; // @[FMAdd.scala 58:20]
+ assign data_io_in_bits = io_in_op[8] ? 32'h0 : io_in_fs3; // @[FMAdd.scala 59:25]
always @(posedge clock) begin
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (~reset & ~(~(fmadd_io_ina_valid & ~fmadd_io_ina_ready))) begin
+ $fatal; // @[FMAdd.scala 69:9]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~(~(fmadd_io_ina_valid & ~fmadd_io_ina_ready))) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at FMAdd.scala:69 assert(!(fmadd.io.ina.valid && !fmadd.io.ina.ready))\n"); // @[FMAdd.scala 69:9]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_4 & ~(~(fmadd_io_inb_valid & ~fmadd_io_inb_ready))) begin
$fatal; // @[FMAdd.scala 70:9]
end
`ifdef STOP_COND
@@ -27848,9 +27684,9 @@
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
- if (~reset & ~(~(fmadd_io_ina_valid & ~fmadd_io_ina_ready))) begin
+ if (_T_4 & ~(~(fmadd_io_inb_valid & ~fmadd_io_inb_ready))) begin
$fwrite(32'h80000002,
- "Assertion failed\n at FMAdd.scala:70 assert(!(fmadd.io.ina.valid && !fmadd.io.ina.ready))\n"); // @[FMAdd.scala 70:9]
+ "Assertion failed\n at FMAdd.scala:70 assert(!(fmadd.io.inb.valid && !fmadd.io.inb.ready))\n"); // @[FMAdd.scala 70:9]
end
`ifdef PRINTF_COND
end
@@ -27860,7 +27696,7 @@
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
- if (_T_4 & ~(~(fmadd_io_inb_valid & ~fmadd_io_inb_ready))) begin
+ if (_T_4 & ~(~(fmadd_io_inc_valid & ~fmadd_io_inc_ready))) begin
$fatal; // @[FMAdd.scala 71:9]
end
`ifdef STOP_COND
@@ -27871,9 +27707,9 @@
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
- if (_T_4 & ~(~(fmadd_io_inb_valid & ~fmadd_io_inb_ready))) begin
+ if (_T_4 & ~(~(fmadd_io_inc_valid & ~fmadd_io_inc_ready))) begin
$fwrite(32'h80000002,
- "Assertion failed\n at FMAdd.scala:71 assert(!(fmadd.io.inb.valid && !fmadd.io.inb.ready))\n"); // @[FMAdd.scala 71:9]
+ "Assertion failed\n at FMAdd.scala:71 assert(!(fmadd.io.inc.valid && !fmadd.io.inc.ready))\n"); // @[FMAdd.scala 71:9]
end
`ifdef PRINTF_COND
end
@@ -27883,7 +27719,7 @@
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
- if (_T_4 & ~(~(fmadd_io_inc_valid & ~fmadd_io_inc_ready))) begin
+ if (_T_4 & ~(~(addr_io_in_valid & ~addr_io_in_ready))) begin
$fatal; // @[FMAdd.scala 72:9]
end
`ifdef STOP_COND
@@ -27894,32 +27730,9 @@
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
- if (_T_4 & ~(~(fmadd_io_inc_valid & ~fmadd_io_inc_ready))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at FMAdd.scala:72 assert(!(fmadd.io.inc.valid && !fmadd.io.inc.ready))\n"); // @[FMAdd.scala 72:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(~(addr_io_in_valid & ~addr_io_in_ready))) begin
- $fatal; // @[FMAdd.scala 73:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
if (_T_4 & ~(~(addr_io_in_valid & ~addr_io_in_ready))) begin
$fwrite(32'h80000002,
- "Assertion failed\n at FMAdd.scala:73 assert(!(addr.io.in.valid && !addr.io.in.ready))\n"); // @[FMAdd.scala 73:9]
+ "Assertion failed\n at FMAdd.scala:72 assert(!(addr.io.in.valid && !addr.io.in.ready))\n"); // @[FMAdd.scala 72:9]
end
`ifdef PRINTF_COND
end
@@ -32865,158 +32678,158 @@
wire [1:0] _opos_T_1 = opos + 2'h1; // @[Slice.scala 39:18]
wire full = ipos[0] == opos[0] & ipos[1] != opos[1]; // @[Slice.scala 47:36]
wire _io_in_ready_T = ~full; // @[Slice.scala 51:22]
- wire _T_3 = ivalid & ~ovalid; // @[Slice.scala 77:18]
- wire _T_5 = ivalid & ovalid; // @[Slice.scala 78:18]
- wire _T_7 = ivalid & ovalid & _io_in_ready_T; // @[Slice.scala 78:28]
- wire _T_8 = ivalid & ~ovalid & empty | _T_7; // @[Slice.scala 77:38]
- wire _T_14 = _T_5 & full; // @[Slice.scala 83:28]
- wire _T_15 = _T_3 & ~empty | _T_14; // @[Slice.scala 82:39]
+ wire _T_3 = ivalid & ~ovalid; // @[Slice.scala 58:18]
+ wire _T_5 = ivalid & ovalid; // @[Slice.scala 59:18]
+ wire _T_7 = ivalid & ovalid & _io_in_ready_T; // @[Slice.scala 59:28]
+ wire _T_8 = ivalid & ~ovalid & empty | _T_7; // @[Slice.scala 58:38]
+ wire _T_14 = _T_5 & full; // @[Slice.scala 64:28]
+ wire _T_15 = _T_3 & ~empty | _T_14; // @[Slice.scala 63:39]
assign io_in_ready = ~full; // @[Slice.scala 51:22]
- assign io_out_valid = ~empty; // @[Slice.scala 107:21]
- assign io_out_bits_0_lane_valid = mem_0_0_lane_valid; // @[Slice.scala 108:18]
- assign io_out_bits_0_lane_bits_inst = mem_0_0_lane_bits_inst; // @[Slice.scala 108:18]
- assign io_out_bits_0_lane_bits_addr = mem_0_0_lane_bits_addr; // @[Slice.scala 108:18]
- assign io_out_bits_0_lane_bits_data = mem_0_0_lane_bits_data; // @[Slice.scala 108:18]
- assign io_out_bits_1_lane_valid = mem_0_1_lane_valid; // @[Slice.scala 108:18]
- assign io_out_bits_1_lane_bits_inst = mem_0_1_lane_bits_inst; // @[Slice.scala 108:18]
- assign io_out_bits_1_lane_bits_addr = mem_0_1_lane_bits_addr; // @[Slice.scala 108:18]
- assign io_out_bits_1_lane_bits_data = mem_0_1_lane_bits_data; // @[Slice.scala 108:18]
- assign io_out_bits_2_lane_valid = mem_0_2_lane_valid; // @[Slice.scala 108:18]
- assign io_out_bits_2_lane_bits_inst = mem_0_2_lane_bits_inst; // @[Slice.scala 108:18]
- assign io_out_bits_2_lane_bits_addr = mem_0_2_lane_bits_addr; // @[Slice.scala 108:18]
- assign io_out_bits_2_lane_bits_data = mem_0_2_lane_bits_data; // @[Slice.scala 108:18]
- assign io_out_bits_3_lane_valid = mem_0_3_lane_valid; // @[Slice.scala 108:18]
- assign io_out_bits_3_lane_bits_inst = mem_0_3_lane_bits_inst; // @[Slice.scala 108:18]
- assign io_out_bits_3_lane_bits_addr = mem_0_3_lane_bits_addr; // @[Slice.scala 108:18]
- assign io_out_bits_3_lane_bits_data = mem_0_3_lane_bits_data; // @[Slice.scala 108:18]
+ assign io_out_valid = ~empty; // @[Slice.scala 88:21]
+ assign io_out_bits_0_lane_valid = mem_0_0_lane_valid; // @[Slice.scala 89:18]
+ assign io_out_bits_0_lane_bits_inst = mem_0_0_lane_bits_inst; // @[Slice.scala 89:18]
+ assign io_out_bits_0_lane_bits_addr = mem_0_0_lane_bits_addr; // @[Slice.scala 89:18]
+ assign io_out_bits_0_lane_bits_data = mem_0_0_lane_bits_data; // @[Slice.scala 89:18]
+ assign io_out_bits_1_lane_valid = mem_0_1_lane_valid; // @[Slice.scala 89:18]
+ assign io_out_bits_1_lane_bits_inst = mem_0_1_lane_bits_inst; // @[Slice.scala 89:18]
+ assign io_out_bits_1_lane_bits_addr = mem_0_1_lane_bits_addr; // @[Slice.scala 89:18]
+ assign io_out_bits_1_lane_bits_data = mem_0_1_lane_bits_data; // @[Slice.scala 89:18]
+ assign io_out_bits_2_lane_valid = mem_0_2_lane_valid; // @[Slice.scala 89:18]
+ assign io_out_bits_2_lane_bits_inst = mem_0_2_lane_bits_inst; // @[Slice.scala 89:18]
+ assign io_out_bits_2_lane_bits_addr = mem_0_2_lane_bits_addr; // @[Slice.scala 89:18]
+ assign io_out_bits_2_lane_bits_data = mem_0_2_lane_bits_data; // @[Slice.scala 89:18]
+ assign io_out_bits_3_lane_valid = mem_0_3_lane_valid; // @[Slice.scala 89:18]
+ assign io_out_bits_3_lane_bits_inst = mem_0_3_lane_bits_inst; // @[Slice.scala 89:18]
+ assign io_out_bits_3_lane_bits_addr = mem_0_3_lane_bits_addr; // @[Slice.scala 89:18]
+ assign io_out_bits_3_lane_bits_data = mem_0_3_lane_bits_data; // @[Slice.scala 89:18]
always @(posedge clock) begin
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_0_lane_valid <= io_in_bits_0_lane_valid; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_0_lane_valid <= mem_1_0_lane_valid; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_0_lane_valid <= io_in_bits_0_lane_valid; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_0_lane_valid <= mem_1_0_lane_valid; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_0_lane_bits_inst <= io_in_bits_0_lane_bits_inst; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_0_lane_bits_inst <= mem_1_0_lane_bits_inst; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_0_lane_bits_inst <= io_in_bits_0_lane_bits_inst; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_0_lane_bits_inst <= mem_1_0_lane_bits_inst; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_0_lane_bits_addr <= io_in_bits_0_lane_bits_addr; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_0_lane_bits_addr <= mem_1_0_lane_bits_addr; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_0_lane_bits_addr <= io_in_bits_0_lane_bits_addr; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_0_lane_bits_addr <= mem_1_0_lane_bits_addr; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_0_lane_bits_data <= io_in_bits_0_lane_bits_data; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_0_lane_bits_data <= mem_1_0_lane_bits_data; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_0_lane_bits_data <= io_in_bits_0_lane_bits_data; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_0_lane_bits_data <= mem_1_0_lane_bits_data; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_1_lane_valid <= io_in_bits_1_lane_valid; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_1_lane_valid <= mem_1_1_lane_valid; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_1_lane_valid <= io_in_bits_1_lane_valid; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_1_lane_valid <= mem_1_1_lane_valid; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_1_lane_bits_inst <= io_in_bits_1_lane_bits_inst; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_1_lane_bits_inst <= mem_1_1_lane_bits_inst; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_1_lane_bits_inst <= io_in_bits_1_lane_bits_inst; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_1_lane_bits_inst <= mem_1_1_lane_bits_inst; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_1_lane_bits_addr <= io_in_bits_1_lane_bits_addr; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_1_lane_bits_addr <= mem_1_1_lane_bits_addr; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_1_lane_bits_addr <= io_in_bits_1_lane_bits_addr; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_1_lane_bits_addr <= mem_1_1_lane_bits_addr; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_1_lane_bits_data <= io_in_bits_1_lane_bits_data; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_1_lane_bits_data <= mem_1_1_lane_bits_data; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_1_lane_bits_data <= io_in_bits_1_lane_bits_data; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_1_lane_bits_data <= mem_1_1_lane_bits_data; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_2_lane_valid <= io_in_bits_2_lane_valid; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_2_lane_valid <= mem_1_2_lane_valid; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_2_lane_valid <= io_in_bits_2_lane_valid; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_2_lane_valid <= mem_1_2_lane_valid; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_2_lane_bits_inst <= io_in_bits_2_lane_bits_inst; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_2_lane_bits_inst <= mem_1_2_lane_bits_inst; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_2_lane_bits_inst <= io_in_bits_2_lane_bits_inst; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_2_lane_bits_inst <= mem_1_2_lane_bits_inst; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_2_lane_bits_addr <= io_in_bits_2_lane_bits_addr; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_2_lane_bits_addr <= mem_1_2_lane_bits_addr; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_2_lane_bits_addr <= io_in_bits_2_lane_bits_addr; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_2_lane_bits_addr <= mem_1_2_lane_bits_addr; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_2_lane_bits_data <= io_in_bits_2_lane_bits_data; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_2_lane_bits_data <= mem_1_2_lane_bits_data; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_2_lane_bits_data <= io_in_bits_2_lane_bits_data; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_2_lane_bits_data <= mem_1_2_lane_bits_data; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_3_lane_valid <= io_in_bits_3_lane_valid; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_3_lane_valid <= mem_1_3_lane_valid; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_3_lane_valid <= io_in_bits_3_lane_valid; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_3_lane_valid <= mem_1_3_lane_valid; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_3_lane_bits_inst <= io_in_bits_3_lane_bits_inst; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_3_lane_bits_inst <= mem_1_3_lane_bits_inst; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_3_lane_bits_inst <= io_in_bits_3_lane_bits_inst; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_3_lane_bits_inst <= mem_1_3_lane_bits_inst; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_3_lane_bits_addr <= io_in_bits_3_lane_bits_addr; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_3_lane_bits_addr <= mem_1_3_lane_bits_addr; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_3_lane_bits_addr <= io_in_bits_3_lane_bits_addr; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_3_lane_bits_addr <= mem_1_3_lane_bits_addr; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_3_lane_bits_data <= io_in_bits_3_lane_bits_data; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_3_lane_bits_data <= mem_1_3_lane_bits_data; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_3_lane_bits_data <= io_in_bits_3_lane_bits_data; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_3_lane_bits_data <= mem_1_3_lane_bits_data; // @[Slice.scala 55:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_0_lane_valid <= io_in_bits_0_lane_valid; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_0_lane_valid <= io_in_bits_0_lane_valid; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_0_lane_bits_inst <= io_in_bits_0_lane_bits_inst; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_0_lane_bits_inst <= io_in_bits_0_lane_bits_inst; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_0_lane_bits_addr <= io_in_bits_0_lane_bits_addr; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_0_lane_bits_addr <= io_in_bits_0_lane_bits_addr; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_0_lane_bits_data <= io_in_bits_0_lane_bits_data; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_0_lane_bits_data <= io_in_bits_0_lane_bits_data; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_1_lane_valid <= io_in_bits_1_lane_valid; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_1_lane_valid <= io_in_bits_1_lane_valid; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_1_lane_bits_inst <= io_in_bits_1_lane_bits_inst; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_1_lane_bits_inst <= io_in_bits_1_lane_bits_inst; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_1_lane_bits_addr <= io_in_bits_1_lane_bits_addr; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_1_lane_bits_addr <= io_in_bits_1_lane_bits_addr; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_1_lane_bits_data <= io_in_bits_1_lane_bits_data; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_1_lane_bits_data <= io_in_bits_1_lane_bits_data; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_2_lane_valid <= io_in_bits_2_lane_valid; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_2_lane_valid <= io_in_bits_2_lane_valid; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_2_lane_bits_inst <= io_in_bits_2_lane_bits_inst; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_2_lane_bits_inst <= io_in_bits_2_lane_bits_inst; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_2_lane_bits_addr <= io_in_bits_2_lane_bits_addr; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_2_lane_bits_addr <= io_in_bits_2_lane_bits_addr; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_2_lane_bits_data <= io_in_bits_2_lane_bits_data; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_2_lane_bits_data <= io_in_bits_2_lane_bits_data; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_3_lane_valid <= io_in_bits_3_lane_valid; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_3_lane_valid <= io_in_bits_3_lane_valid; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_3_lane_bits_inst <= io_in_bits_3_lane_bits_inst; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_3_lane_bits_inst <= io_in_bits_3_lane_bits_inst; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_3_lane_bits_addr <= io_in_bits_3_lane_bits_addr; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_3_lane_bits_addr <= io_in_bits_3_lane_bits_addr; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_3_lane_bits_data <= io_in_bits_3_lane_bits_data; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_3_lane_bits_data <= io_in_bits_3_lane_bits_data; // @[Slice.scala 65:14]
end
end
always @(posedge clock or posedge reset) begin
@@ -37567,8 +37380,8 @@
wire [1:0] _GEN_93 = {{1'd0}, cmdqchk[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_367 = _GEN_93 + _T_365; // @[Bitwise.scala 48:55]
wire [2:0] _T_369 = _T_363[1:0] + _T_367[1:0]; // @[Bitwise.scala 48:55]
- wire _io_actv_ractive_T_6 = vfmt6 & ~vslideh2; // @[VDecodeInstruction.scala 671:17]
- wire _io_actv_ractive_T_7 = _io_out_vt_valid_T_6 | _io_actv_ractive_T_6; // @[VDecodeInstruction.scala 670:62]
+ wire _io_actv_ractive_T_6 = vfmt6 & ~vslideh2; // @[VDecodeInstruction.scala 670:17]
+ wire _io_actv_ractive_T_7 = _io_out_vt_valid_T_6 | _io_actv_ractive_T_6; // @[VDecodeInstruction.scala 669:62]
wire [63:0] io_actv_ractive_vs = 64'h1 << vsbits; // @[OneHot.scala 64:12]
wire [63:0] io_actv_ractive_vsm = m ? ractivedi : 64'h0; // @[Library.scala 18:8]
wire [63:0] _io_actv_ractive_vt_T_1 = 64'h1 << vtbits; // @[OneHot.scala 64:12]
@@ -37627,66 +37440,66 @@
wire [63:0] _io_actv_ractive_T_13 = _io_actv_ractive_T_8 | io_actv_ractive_vt_1; // @[VDecodeInstruction.scala 86:14]
wire [63:0] _io_actv_ractive_T_14 = _io_actv_ractive_T_13 | io_actv_ractive_vtm_1; // @[VDecodeInstruction.scala 86:19]
wire [63:0] _io_actv_ractive_T_15 = vfmadd4 ? _io_actv_ractive_T_14 : 64'h0; // @[Library.scala 18:8]
- wire [63:0] _io_actv_ractive_T_16 = _io_actv_ractive_T_11 | _io_actv_ractive_T_15; // @[VDecodeInstruction.scala 671:80]
- wire _io_actv_ractive_T_17 = vsraqs | vsrans; // @[VDecodeInstruction.scala 673:18]
+ wire [63:0] _io_actv_ractive_T_16 = _io_actv_ractive_T_11 | _io_actv_ractive_T_15; // @[VDecodeInstruction.scala 670:80]
+ wire _io_actv_ractive_T_17 = vsraqs | vsrans; // @[VDecodeInstruction.scala 672:18]
wire [64:0] _io_actv_ractive_vs_T_4 = {io_actv_ractive_vs,1'h0}; // @[Cat.scala 31:58]
wire [63:0] io_actv_ractive_vs_2 = _io_actv_ractive_vs_T_4[63:0]; // @[VDecodeInstruction.scala 91:48]
wire [67:0] _io_actv_ractive_vsm_T_9 = {ractivedi_b_hi,ractivedi_b_lo,4'h0}; // @[Cat.scala 31:58]
wire [63:0] io_actv_ractive_vsm_2 = m ? _io_actv_ractive_vsm_T_9[63:0] : 64'h0; // @[Library.scala 18:8]
wire [63:0] _io_actv_ractive_T_18 = io_actv_ractive_vs_2 | io_actv_ractive_vsm_2; // @[VDecodeInstruction.scala 95:8]
wire [63:0] _io_actv_ractive_T_19 = _io_actv_ractive_T_17 ? _io_actv_ractive_T_18 : 64'h0; // @[Library.scala 18:8]
- wire [63:0] _io_actv_ractive_T_20 = _io_actv_ractive_T_16 | _io_actv_ractive_T_19; // @[VDecodeInstruction.scala 672:80]
+ wire [63:0] _io_actv_ractive_T_20 = _io_actv_ractive_T_16 | _io_actv_ractive_T_19; // @[VDecodeInstruction.scala 671:80]
wire [65:0] _io_actv_ractive_vs_T_7 = {io_actv_ractive_vs,2'h0}; // @[Cat.scala 31:58]
wire [63:0] io_actv_ractive_vs_3 = _io_actv_ractive_vs_T_7[63:0]; // @[VDecodeInstruction.scala 100:48]
wire [71:0] _io_actv_ractive_vsm_T_14 = {ractivedi_b_hi,ractivedi_b_lo,8'h0}; // @[Cat.scala 31:58]
wire [63:0] io_actv_ractive_vsm_3 = m ? _io_actv_ractive_vsm_T_14[63:0] : 64'h0; // @[Library.scala 18:8]
wire [63:0] _io_actv_ractive_T_21 = io_actv_ractive_vs_3 | io_actv_ractive_vsm_3; // @[VDecodeInstruction.scala 104:8]
wire [63:0] _io_actv_ractive_T_22 = vsraqs ? _io_actv_ractive_T_21 : 64'h0; // @[Library.scala 18:8]
- wire [63:0] _io_actv_ractive_T_23 = _io_actv_ractive_T_20 | _io_actv_ractive_T_22; // @[VDecodeInstruction.scala 673:80]
+ wire [63:0] _io_actv_ractive_T_23 = _io_actv_ractive_T_20 | _io_actv_ractive_T_22; // @[VDecodeInstruction.scala 672:80]
wire [66:0] _io_actv_ractive_vs_T_10 = {io_actv_ractive_vs,3'h0}; // @[Cat.scala 31:58]
wire [63:0] io_actv_ractive_vs_4 = _io_actv_ractive_vs_T_10[63:0]; // @[VDecodeInstruction.scala 109:48]
wire [75:0] _io_actv_ractive_vsm_T_19 = {ractivedi_b_hi,ractivedi_b_lo,12'h0}; // @[Cat.scala 31:58]
wire [63:0] io_actv_ractive_vsm_4 = m ? _io_actv_ractive_vsm_T_19[63:0] : 64'h0; // @[Library.scala 18:8]
wire [63:0] _io_actv_ractive_T_24 = io_actv_ractive_vs_4 | io_actv_ractive_vsm_4; // @[VDecodeInstruction.scala 113:8]
wire [63:0] _io_actv_ractive_T_25 = vsraqs ? _io_actv_ractive_T_24 : 64'h0; // @[Library.scala 18:8]
- wire [63:0] _io_actv_ractive_T_26 = _io_actv_ractive_T_23 | _io_actv_ractive_T_25; // @[VDecodeInstruction.scala 674:80]
- wire _io_actv_ractive_T_29 = vmacc | vmadd | vst | vstq; // @[VDecodeInstruction.scala 676:33]
+ wire [63:0] _io_actv_ractive_T_26 = _io_actv_ractive_T_23 | _io_actv_ractive_T_25; // @[VDecodeInstruction.scala 673:80]
+ wire _io_actv_ractive_T_29 = vmacc | vmadd | vst | vstq; // @[VDecodeInstruction.scala 675:33]
wire [63:0] io_actv_ractive_vd = 64'h1 << vdbits; // @[OneHot.scala 64:12]
wire [63:0] io_actv_ractive_vdm = m ? wactivedw : 64'h0; // @[Library.scala 18:8]
wire [63:0] _io_actv_ractive_T_30 = io_actv_ractive_vd | io_actv_ractive_vdm; // @[VDecodeInstruction.scala 121:8]
wire [63:0] _io_actv_ractive_T_31 = _io_actv_ractive_T_29 ? _io_actv_ractive_T_30 : 64'h0; // @[Library.scala 18:8]
- wire [63:0] _io_actv_ractive_T_32 = _io_actv_ractive_T_26 | _io_actv_ractive_T_31; // @[VDecodeInstruction.scala 675:80]
+ wire [63:0] _io_actv_ractive_T_32 = _io_actv_ractive_T_26 | _io_actv_ractive_T_31; // @[VDecodeInstruction.scala 674:80]
wire [63:0] _io_actv_ractive_T_33 = ra_vx | ra_vxm; // @[VDecodeInstruction.scala 129:8]
wire [63:0] _io_actv_ractive_T_34 = vfmadd4 ? _io_actv_ractive_T_33 : 64'h0; // @[Library.scala 18:8]
- wire [63:0] _io_actv_ractive_T_35 = _io_actv_ractive_T_32 | _io_actv_ractive_T_34; // @[VDecodeInstruction.scala 676:80]
+ wire [63:0] _io_actv_ractive_T_35 = _io_actv_ractive_T_32 | _io_actv_ractive_T_34; // @[VDecodeInstruction.scala 675:80]
wire [63:0] _io_actv_ractive_T_36 = vadwconv ? ractivedw : 64'h0; // @[Library.scala 18:8]
- wire [63:0] _io_actv_ractive_T_37 = _io_actv_ractive_T_35 | _io_actv_ractive_T_36; // @[VDecodeInstruction.scala 677:80]
+ wire [63:0] _io_actv_ractive_T_37 = _io_actv_ractive_T_35 | _io_actv_ractive_T_36; // @[VDecodeInstruction.scala 676:80]
wire [63:0] _io_actv_ractive_T_38 = adwinit ? ractivedi : 64'h0; // @[Library.scala 18:8]
- wire [63:0] _io_actv_ractive_T_39 = _io_actv_ractive_T_37 | _io_actv_ractive_T_38; // @[VDecodeInstruction.scala 678:80]
+ wire [63:0] _io_actv_ractive_T_39 = _io_actv_ractive_T_37 | _io_actv_ractive_T_38; // @[VDecodeInstruction.scala 677:80]
wire [63:0] _io_actv_ractive_T_40 = vslideh2 ? ractivesl : 64'h0; // @[Library.scala 18:8]
- wire [63:0] _io_actv_ractive_T_41 = _io_actv_ractive_T_39 | _io_actv_ractive_T_40; // @[VDecodeInstruction.scala 679:80]
- wire _io_actv_ractive_T_42 = aconv | actr; // @[VDecodeInstruction.scala 681:17]
+ wire [63:0] _io_actv_ractive_T_41 = _io_actv_ractive_T_39 | _io_actv_ractive_T_40; // @[VDecodeInstruction.scala 678:80]
+ wire _io_actv_ractive_T_42 = aconv | actr; // @[VDecodeInstruction.scala 680:17]
wire [63:0] ractiveconv1 = _ractiveconv1_T_2[63:0]; // @[VDecodeInstruction.scala 557:26 571:18]
wire [63:0] _io_actv_ractive_T_43 = _io_actv_ractive_T_42 ? ractiveconv1 : 64'h0; // @[Library.scala 18:8]
- wire [63:0] _io_actv_ractive_T_44 = _io_actv_ractive_T_41 | _io_actv_ractive_T_43; // @[VDecodeInstruction.scala 680:80]
+ wire [63:0] _io_actv_ractive_T_44 = _io_actv_ractive_T_41 | _io_actv_ractive_T_43; // @[VDecodeInstruction.scala 679:80]
wire [63:0] ractiveconv2 = _ractiveconv2_T_2[63:0]; // @[VDecodeInstruction.scala 558:26 572:18]
wire [63:0] _io_actv_ractive_T_45 = aconv ? ractiveconv2 : 64'h0; // @[Library.scala 18:8]
- wire [63:0] _io_actv_ractive_T_46 = _io_actv_ractive_T_44 | _io_actv_ractive_T_45; // @[VDecodeInstruction.scala 681:80]
+ wire [63:0] _io_actv_ractive_T_46 = _io_actv_ractive_T_44 | _io_actv_ractive_T_45; // @[VDecodeInstruction.scala 680:80]
wire [63:0] ractiveaset = _ractiveaset_T_2[63:0]; // @[VDecodeInstruction.scala 559:26 573:18]
wire [63:0] _io_actv_ractive_T_47 = acset ? ractiveaset : 64'h0; // @[Library.scala 18:8]
- wire _io_actv_wactive_T_6 = _io_out_vt_valid_T_7 | vdup; // @[VDecodeInstruction.scala 686:71]
- wire _io_actv_wactive_T_8 = _io_actv_wactive_T_6 | vld | vfmadd4; // @[VDecodeInstruction.scala 687:23]
+ wire _io_actv_wactive_T_6 = _io_out_vt_valid_T_7 | vdup; // @[VDecodeInstruction.scala 685:71]
+ wire _io_actv_wactive_T_8 = _io_actv_wactive_T_6 | vld | vfmadd4; // @[VDecodeInstruction.scala 686:23]
wire [63:0] _io_actv_wactive_T_10 = _io_actv_wactive_T_8 ? _io_actv_ractive_T_30 : 64'h0; // @[Library.scala 18:8]
- wire _io_actv_wactive_T_16 = vmvp | vmulw | vacc | vaddw | vsubw | vevnodd | vzip; // @[VDecodeInstruction.scala 688:62]
+ wire _io_actv_wactive_T_16 = vmvp | vmulw | vacc | vaddw | vsubw | vevnodd | vzip; // @[VDecodeInstruction.scala 687:62]
wire [64:0] _io_actv_wactive_vd_T_3 = {io_actv_ractive_vd,1'h0}; // @[Cat.scala 31:58]
wire [63:0] io_actv_wactive_vd_1 = _io_actv_wactive_vd_T_3[63:0]; // @[VDecodeInstruction.scala 142:48]
wire [67:0] _io_actv_wactive_vdm_T_6 = {wactivedw_b_hi,wactivedw_b_lo,4'h0}; // @[Cat.scala 31:58]
wire [63:0] io_actv_wactive_vdm_1 = m ? _io_actv_wactive_vdm_T_6[63:0] : 64'h0; // @[Library.scala 18:8]
wire [63:0] _io_actv_wactive_T_17 = io_actv_wactive_vd_1 | io_actv_wactive_vdm_1; // @[VDecodeInstruction.scala 146:8]
wire [63:0] _io_actv_wactive_T_18 = _io_actv_wactive_T_16 ? _io_actv_wactive_T_17 : 64'h0; // @[Library.scala 18:8]
- wire [63:0] _io_actv_wactive_T_19 = _io_actv_wactive_T_10 | _io_actv_wactive_T_18; // @[VDecodeInstruction.scala 687:80]
+ wire [63:0] _io_actv_wactive_T_19 = _io_actv_wactive_T_10 | _io_actv_wactive_T_18; // @[VDecodeInstruction.scala 686:80]
wire [63:0] _io_actv_wactive_T_20 = vdwconv ? wactivedw : 64'h0; // @[Library.scala 18:8]
- wire [63:0] _io_actv_wactive_T_21 = _io_actv_wactive_T_19 | _io_actv_wactive_T_20; // @[VDecodeInstruction.scala 689:80]
+ wire [63:0] _io_actv_wactive_T_21 = _io_actv_wactive_T_19 | _io_actv_wactive_T_20; // @[VDecodeInstruction.scala 688:80]
wire [63:0] wactiveconv = _wactiveconv_T_2[63:0]; // @[VDecodeInstruction.scala 560:26 574:18]
wire [63:0] _io_actv_wactive_T_22 = vcget ? wactiveconv : 64'h0; // @[Library.scala 18:8]
assign io_out_op = _op_T_206 | _op_T_207; // @[VDecodeInstruction.scala 535:38]
@@ -37723,8 +37536,8 @@
assign io_cmdq_ldst = vldst & ~uncached; // @[VDecodeInstruction.scala 661:25]
assign io_cmdq_ld = vld & uncached; // @[VDecodeInstruction.scala 662:21]
assign io_cmdq_st = (vst | vstq) & uncached; // @[VDecodeInstruction.scala 663:31]
- assign io_actv_ractive = _io_actv_ractive_T_46 | _io_actv_ractive_T_47; // @[VDecodeInstruction.scala 682:80]
- assign io_actv_wactive = _io_actv_wactive_T_21 | _io_actv_wactive_T_22; // @[VDecodeInstruction.scala 690:80]
+ assign io_actv_ractive = _io_actv_ractive_T_46 | _io_actv_ractive_T_47; // @[VDecodeInstruction.scala 681:80]
+ assign io_actv_wactive = _io_actv_wactive_T_21 | _io_actv_wactive_T_22; // @[VDecodeInstruction.scala 689:80]
assign io_undef = ~undef_value_6_0; // @[VDecodeInstruction.scala 416:15]
always @(posedge clock) begin
`ifndef SYNTHESIS
@@ -39817,7 +39630,7 @@
wire [1:0] _ordered_T_5 = ~_ordered_T[1:0]; // @[VDecode.scala 354:20]
wire [2:0] _ordered_T_8 = ~_ordered_T[2:0]; // @[VDecode.scala 354:20]
wire [3:0] _ordered_T_11 = ~_ordered_T; // @[VDecode.scala 354:20]
- reg nempty; // @[VDecode.scala 370:23]
+ reg nempty; // @[VDecode.scala 368:23]
Fifo4x4 f ( // @[Fifo4x4.scala 8:11]
.clock(f_clock),
.reset(f_reset),
@@ -40024,158 +39837,158 @@
);
assign io_in_ready = f_io_in_ready; // @[VDecode.scala 113:11]
assign io_out_0_valid = ~(~_ordered_T[0]); // @[VDecode.scala 354:43]
- assign io_out_0_bits_op = data_0_op; // @[VDecode.scala 363:20]
- assign io_out_0_bits_f2 = data_0_f2; // @[VDecode.scala 363:20]
- assign io_out_0_bits_sz = data_0_sz; // @[VDecode.scala 363:20]
- assign io_out_0_bits_m = data_0_m; // @[VDecode.scala 363:20]
- assign io_out_0_bits_vd_valid = data_0_vd_valid; // @[VDecode.scala 363:20]
- assign io_out_0_bits_vd_addr = data_0_vd_addr; // @[VDecode.scala 363:20]
- assign io_out_0_bits_ve_addr = data_0_ve_addr; // @[VDecode.scala 363:20]
- assign io_out_0_bits_vf_addr = data_0_vf_addr; // @[VDecode.scala 363:20]
- assign io_out_0_bits_vg_addr = data_0_vg_addr; // @[VDecode.scala 363:20]
- assign io_out_0_bits_vs_valid = data_0_vs_valid; // @[VDecode.scala 363:20]
- assign io_out_0_bits_vs_addr = data_0_vs_addr; // @[VDecode.scala 363:20]
- assign io_out_0_bits_vs_tag = data_0_vs_tag; // @[VDecode.scala 363:20]
- assign io_out_0_bits_vt_valid = data_0_vt_valid; // @[VDecode.scala 363:20]
- assign io_out_0_bits_vt_addr = data_0_vt_addr; // @[VDecode.scala 363:20]
- assign io_out_0_bits_vt_tag = data_0_vt_tag; // @[VDecode.scala 363:20]
- assign io_out_0_bits_vu_valid = data_0_vu_valid; // @[VDecode.scala 363:20]
- assign io_out_0_bits_vu_addr = data_0_vu_addr; // @[VDecode.scala 363:20]
- assign io_out_0_bits_vu_tag = data_0_vu_tag; // @[VDecode.scala 363:20]
- assign io_out_0_bits_vx_valid = data_0_vx_valid; // @[VDecode.scala 363:20]
- assign io_out_0_bits_vx_addr = data_0_vx_addr; // @[VDecode.scala 363:20]
- assign io_out_0_bits_vx_tag = data_0_vx_tag; // @[VDecode.scala 363:20]
- assign io_out_0_bits_vy_valid = data_0_vy_valid; // @[VDecode.scala 363:20]
- assign io_out_0_bits_vy_addr = data_0_vy_addr; // @[VDecode.scala 363:20]
- assign io_out_0_bits_vy_tag = data_0_vy_tag; // @[VDecode.scala 363:20]
- assign io_out_0_bits_vz_valid = data_0_vz_valid; // @[VDecode.scala 363:20]
- assign io_out_0_bits_vz_addr = data_0_vz_addr; // @[VDecode.scala 363:20]
- assign io_out_0_bits_vz_tag = data_0_vz_tag; // @[VDecode.scala 363:20]
- assign io_out_0_bits_sv_valid = data_0_sv_valid; // @[VDecode.scala 363:20]
- assign io_out_0_bits_sv_addr = data_0_sv_addr; // @[VDecode.scala 363:20]
- assign io_out_0_bits_sv_data = data_0_sv_data; // @[VDecode.scala 363:20]
- assign io_out_0_bits_cmdsync = data_0_cmdsync; // @[VDecode.scala 363:20]
+ assign io_out_0_bits_op = data_0_op; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_f2 = data_0_f2; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_sz = data_0_sz; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_m = data_0_m; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_vd_valid = data_0_vd_valid; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_vd_addr = data_0_vd_addr; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_ve_addr = data_0_ve_addr; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_vf_addr = data_0_vf_addr; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_vg_addr = data_0_vg_addr; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_vs_valid = data_0_vs_valid; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_vs_addr = data_0_vs_addr; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_vs_tag = data_0_vs_tag; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_vt_valid = data_0_vt_valid; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_vt_addr = data_0_vt_addr; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_vt_tag = data_0_vt_tag; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_vu_valid = data_0_vu_valid; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_vu_addr = data_0_vu_addr; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_vu_tag = data_0_vu_tag; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_vx_valid = data_0_vx_valid; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_vx_addr = data_0_vx_addr; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_vx_tag = data_0_vx_tag; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_vy_valid = data_0_vy_valid; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_vy_addr = data_0_vy_addr; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_vy_tag = data_0_vy_tag; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_vz_valid = data_0_vz_valid; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_vz_addr = data_0_vz_addr; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_vz_tag = data_0_vz_tag; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_sv_valid = data_0_sv_valid; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_sv_addr = data_0_sv_addr; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_sv_data = data_0_sv_data; // @[VDecode.scala 361:20]
+ assign io_out_0_bits_cmdsync = data_0_cmdsync; // @[VDecode.scala 361:20]
assign io_out_1_valid = _ordered_T_5 == 2'h0; // @[VDecode.scala 354:43]
- assign io_out_1_bits_op = data_1_op; // @[VDecode.scala 363:20]
- assign io_out_1_bits_f2 = data_1_f2; // @[VDecode.scala 363:20]
- assign io_out_1_bits_sz = data_1_sz; // @[VDecode.scala 363:20]
- assign io_out_1_bits_m = data_1_m; // @[VDecode.scala 363:20]
- assign io_out_1_bits_vd_valid = data_1_vd_valid; // @[VDecode.scala 363:20]
- assign io_out_1_bits_vd_addr = data_1_vd_addr; // @[VDecode.scala 363:20]
- assign io_out_1_bits_ve_addr = data_1_ve_addr; // @[VDecode.scala 363:20]
- assign io_out_1_bits_vf_addr = data_1_vf_addr; // @[VDecode.scala 363:20]
- assign io_out_1_bits_vg_addr = data_1_vg_addr; // @[VDecode.scala 363:20]
- assign io_out_1_bits_vs_valid = data_1_vs_valid; // @[VDecode.scala 363:20]
- assign io_out_1_bits_vs_addr = data_1_vs_addr; // @[VDecode.scala 363:20]
- assign io_out_1_bits_vs_tag = data_1_vs_tag; // @[VDecode.scala 363:20]
- assign io_out_1_bits_vt_valid = data_1_vt_valid; // @[VDecode.scala 363:20]
- assign io_out_1_bits_vt_addr = data_1_vt_addr; // @[VDecode.scala 363:20]
- assign io_out_1_bits_vt_tag = data_1_vt_tag; // @[VDecode.scala 363:20]
- assign io_out_1_bits_vu_valid = data_1_vu_valid; // @[VDecode.scala 363:20]
- assign io_out_1_bits_vu_addr = data_1_vu_addr; // @[VDecode.scala 363:20]
- assign io_out_1_bits_vu_tag = data_1_vu_tag; // @[VDecode.scala 363:20]
- assign io_out_1_bits_vx_valid = data_1_vx_valid; // @[VDecode.scala 363:20]
- assign io_out_1_bits_vx_addr = data_1_vx_addr; // @[VDecode.scala 363:20]
- assign io_out_1_bits_vx_tag = data_1_vx_tag; // @[VDecode.scala 363:20]
- assign io_out_1_bits_vy_valid = data_1_vy_valid; // @[VDecode.scala 363:20]
- assign io_out_1_bits_vy_addr = data_1_vy_addr; // @[VDecode.scala 363:20]
- assign io_out_1_bits_vy_tag = data_1_vy_tag; // @[VDecode.scala 363:20]
- assign io_out_1_bits_vz_valid = data_1_vz_valid; // @[VDecode.scala 363:20]
- assign io_out_1_bits_vz_addr = data_1_vz_addr; // @[VDecode.scala 363:20]
- assign io_out_1_bits_vz_tag = data_1_vz_tag; // @[VDecode.scala 363:20]
- assign io_out_1_bits_sv_valid = data_1_sv_valid; // @[VDecode.scala 363:20]
- assign io_out_1_bits_sv_addr = data_1_sv_addr; // @[VDecode.scala 363:20]
- assign io_out_1_bits_sv_data = data_1_sv_data; // @[VDecode.scala 363:20]
- assign io_out_1_bits_cmdsync = data_1_cmdsync; // @[VDecode.scala 363:20]
+ assign io_out_1_bits_op = data_1_op; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_f2 = data_1_f2; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_sz = data_1_sz; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_m = data_1_m; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_vd_valid = data_1_vd_valid; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_vd_addr = data_1_vd_addr; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_ve_addr = data_1_ve_addr; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_vf_addr = data_1_vf_addr; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_vg_addr = data_1_vg_addr; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_vs_valid = data_1_vs_valid; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_vs_addr = data_1_vs_addr; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_vs_tag = data_1_vs_tag; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_vt_valid = data_1_vt_valid; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_vt_addr = data_1_vt_addr; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_vt_tag = data_1_vt_tag; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_vu_valid = data_1_vu_valid; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_vu_addr = data_1_vu_addr; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_vu_tag = data_1_vu_tag; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_vx_valid = data_1_vx_valid; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_vx_addr = data_1_vx_addr; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_vx_tag = data_1_vx_tag; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_vy_valid = data_1_vy_valid; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_vy_addr = data_1_vy_addr; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_vy_tag = data_1_vy_tag; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_vz_valid = data_1_vz_valid; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_vz_addr = data_1_vz_addr; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_vz_tag = data_1_vz_tag; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_sv_valid = data_1_sv_valid; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_sv_addr = data_1_sv_addr; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_sv_data = data_1_sv_data; // @[VDecode.scala 361:20]
+ assign io_out_1_bits_cmdsync = data_1_cmdsync; // @[VDecode.scala 361:20]
assign io_out_2_valid = _ordered_T_8 == 3'h0; // @[VDecode.scala 354:43]
- assign io_out_2_bits_op = data_2_op; // @[VDecode.scala 363:20]
- assign io_out_2_bits_f2 = data_2_f2; // @[VDecode.scala 363:20]
- assign io_out_2_bits_sz = data_2_sz; // @[VDecode.scala 363:20]
- assign io_out_2_bits_m = data_2_m; // @[VDecode.scala 363:20]
- assign io_out_2_bits_vd_valid = data_2_vd_valid; // @[VDecode.scala 363:20]
- assign io_out_2_bits_vd_addr = data_2_vd_addr; // @[VDecode.scala 363:20]
- assign io_out_2_bits_ve_addr = data_2_ve_addr; // @[VDecode.scala 363:20]
- assign io_out_2_bits_vf_addr = data_2_vf_addr; // @[VDecode.scala 363:20]
- assign io_out_2_bits_vg_addr = data_2_vg_addr; // @[VDecode.scala 363:20]
- assign io_out_2_bits_vs_valid = data_2_vs_valid; // @[VDecode.scala 363:20]
- assign io_out_2_bits_vs_addr = data_2_vs_addr; // @[VDecode.scala 363:20]
- assign io_out_2_bits_vs_tag = data_2_vs_tag; // @[VDecode.scala 363:20]
- assign io_out_2_bits_vt_valid = data_2_vt_valid; // @[VDecode.scala 363:20]
- assign io_out_2_bits_vt_addr = data_2_vt_addr; // @[VDecode.scala 363:20]
- assign io_out_2_bits_vt_tag = data_2_vt_tag; // @[VDecode.scala 363:20]
- assign io_out_2_bits_vu_valid = data_2_vu_valid; // @[VDecode.scala 363:20]
- assign io_out_2_bits_vu_addr = data_2_vu_addr; // @[VDecode.scala 363:20]
- assign io_out_2_bits_vu_tag = data_2_vu_tag; // @[VDecode.scala 363:20]
- assign io_out_2_bits_vx_valid = data_2_vx_valid; // @[VDecode.scala 363:20]
- assign io_out_2_bits_vx_addr = data_2_vx_addr; // @[VDecode.scala 363:20]
- assign io_out_2_bits_vx_tag = data_2_vx_tag; // @[VDecode.scala 363:20]
- assign io_out_2_bits_vy_valid = data_2_vy_valid; // @[VDecode.scala 363:20]
- assign io_out_2_bits_vy_addr = data_2_vy_addr; // @[VDecode.scala 363:20]
- assign io_out_2_bits_vy_tag = data_2_vy_tag; // @[VDecode.scala 363:20]
- assign io_out_2_bits_vz_valid = data_2_vz_valid; // @[VDecode.scala 363:20]
- assign io_out_2_bits_vz_addr = data_2_vz_addr; // @[VDecode.scala 363:20]
- assign io_out_2_bits_vz_tag = data_2_vz_tag; // @[VDecode.scala 363:20]
- assign io_out_2_bits_sv_valid = data_2_sv_valid; // @[VDecode.scala 363:20]
- assign io_out_2_bits_sv_addr = data_2_sv_addr; // @[VDecode.scala 363:20]
- assign io_out_2_bits_sv_data = data_2_sv_data; // @[VDecode.scala 363:20]
- assign io_out_2_bits_cmdsync = data_2_cmdsync; // @[VDecode.scala 363:20]
+ assign io_out_2_bits_op = data_2_op; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_f2 = data_2_f2; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_sz = data_2_sz; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_m = data_2_m; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_vd_valid = data_2_vd_valid; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_vd_addr = data_2_vd_addr; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_ve_addr = data_2_ve_addr; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_vf_addr = data_2_vf_addr; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_vg_addr = data_2_vg_addr; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_vs_valid = data_2_vs_valid; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_vs_addr = data_2_vs_addr; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_vs_tag = data_2_vs_tag; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_vt_valid = data_2_vt_valid; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_vt_addr = data_2_vt_addr; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_vt_tag = data_2_vt_tag; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_vu_valid = data_2_vu_valid; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_vu_addr = data_2_vu_addr; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_vu_tag = data_2_vu_tag; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_vx_valid = data_2_vx_valid; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_vx_addr = data_2_vx_addr; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_vx_tag = data_2_vx_tag; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_vy_valid = data_2_vy_valid; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_vy_addr = data_2_vy_addr; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_vy_tag = data_2_vy_tag; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_vz_valid = data_2_vz_valid; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_vz_addr = data_2_vz_addr; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_vz_tag = data_2_vz_tag; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_sv_valid = data_2_sv_valid; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_sv_addr = data_2_sv_addr; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_sv_data = data_2_sv_data; // @[VDecode.scala 361:20]
+ assign io_out_2_bits_cmdsync = data_2_cmdsync; // @[VDecode.scala 361:20]
assign io_out_3_valid = _ordered_T_11 == 4'h0; // @[VDecode.scala 354:43]
- assign io_out_3_bits_op = data_3_op; // @[VDecode.scala 363:20]
- assign io_out_3_bits_f2 = data_3_f2; // @[VDecode.scala 363:20]
- assign io_out_3_bits_sz = data_3_sz; // @[VDecode.scala 363:20]
- assign io_out_3_bits_m = data_3_m; // @[VDecode.scala 363:20]
- assign io_out_3_bits_vd_valid = data_3_vd_valid; // @[VDecode.scala 363:20]
- assign io_out_3_bits_vd_addr = data_3_vd_addr; // @[VDecode.scala 363:20]
- assign io_out_3_bits_ve_addr = data_3_ve_addr; // @[VDecode.scala 363:20]
- assign io_out_3_bits_vf_addr = data_3_vf_addr; // @[VDecode.scala 363:20]
- assign io_out_3_bits_vg_addr = data_3_vg_addr; // @[VDecode.scala 363:20]
- assign io_out_3_bits_vs_valid = data_3_vs_valid; // @[VDecode.scala 363:20]
- assign io_out_3_bits_vs_addr = data_3_vs_addr; // @[VDecode.scala 363:20]
- assign io_out_3_bits_vs_tag = data_3_vs_tag; // @[VDecode.scala 363:20]
- assign io_out_3_bits_vt_valid = data_3_vt_valid; // @[VDecode.scala 363:20]
- assign io_out_3_bits_vt_addr = data_3_vt_addr; // @[VDecode.scala 363:20]
- assign io_out_3_bits_vt_tag = data_3_vt_tag; // @[VDecode.scala 363:20]
- assign io_out_3_bits_vu_valid = data_3_vu_valid; // @[VDecode.scala 363:20]
- assign io_out_3_bits_vu_addr = data_3_vu_addr; // @[VDecode.scala 363:20]
- assign io_out_3_bits_vu_tag = data_3_vu_tag; // @[VDecode.scala 363:20]
- assign io_out_3_bits_vx_valid = data_3_vx_valid; // @[VDecode.scala 363:20]
- assign io_out_3_bits_vx_addr = data_3_vx_addr; // @[VDecode.scala 363:20]
- assign io_out_3_bits_vx_tag = data_3_vx_tag; // @[VDecode.scala 363:20]
- assign io_out_3_bits_vy_valid = data_3_vy_valid; // @[VDecode.scala 363:20]
- assign io_out_3_bits_vy_addr = data_3_vy_addr; // @[VDecode.scala 363:20]
- assign io_out_3_bits_vy_tag = data_3_vy_tag; // @[VDecode.scala 363:20]
- assign io_out_3_bits_vz_valid = data_3_vz_valid; // @[VDecode.scala 363:20]
- assign io_out_3_bits_vz_addr = data_3_vz_addr; // @[VDecode.scala 363:20]
- assign io_out_3_bits_vz_tag = data_3_vz_tag; // @[VDecode.scala 363:20]
- assign io_out_3_bits_sv_valid = data_3_sv_valid; // @[VDecode.scala 363:20]
- assign io_out_3_bits_sv_addr = data_3_sv_addr; // @[VDecode.scala 363:20]
- assign io_out_3_bits_sv_data = data_3_sv_data; // @[VDecode.scala 363:20]
- assign io_out_3_bits_cmdsync = data_3_cmdsync; // @[VDecode.scala 363:20]
- assign io_cmdq_0_alu = cmdq_0_alu; // @[VDecode.scala 364:16]
- assign io_cmdq_0_conv = cmdq_0_conv; // @[VDecode.scala 364:16]
- assign io_cmdq_0_ldst = cmdq_0_ldst; // @[VDecode.scala 364:16]
- assign io_cmdq_0_ld = cmdq_0_ld; // @[VDecode.scala 364:16]
- assign io_cmdq_0_st = cmdq_0_st; // @[VDecode.scala 364:16]
- assign io_cmdq_1_alu = cmdq_1_alu; // @[VDecode.scala 364:16]
- assign io_cmdq_1_conv = cmdq_1_conv; // @[VDecode.scala 364:16]
- assign io_cmdq_1_ldst = cmdq_1_ldst; // @[VDecode.scala 364:16]
- assign io_cmdq_1_ld = cmdq_1_ld; // @[VDecode.scala 364:16]
- assign io_cmdq_1_st = cmdq_1_st; // @[VDecode.scala 364:16]
- assign io_cmdq_2_alu = cmdq_2_alu; // @[VDecode.scala 364:16]
- assign io_cmdq_2_conv = cmdq_2_conv; // @[VDecode.scala 364:16]
- assign io_cmdq_2_ldst = cmdq_2_ldst; // @[VDecode.scala 364:16]
- assign io_cmdq_2_ld = cmdq_2_ld; // @[VDecode.scala 364:16]
- assign io_cmdq_2_st = cmdq_2_st; // @[VDecode.scala 364:16]
- assign io_cmdq_3_alu = cmdq_3_alu; // @[VDecode.scala 364:16]
- assign io_cmdq_3_conv = cmdq_3_conv; // @[VDecode.scala 364:16]
- assign io_cmdq_3_ldst = cmdq_3_ldst; // @[VDecode.scala 364:16]
- assign io_cmdq_3_ld = cmdq_3_ld; // @[VDecode.scala 364:16]
- assign io_cmdq_3_st = cmdq_3_st; // @[VDecode.scala 364:16]
+ assign io_out_3_bits_op = data_3_op; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_f2 = data_3_f2; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_sz = data_3_sz; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_m = data_3_m; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_vd_valid = data_3_vd_valid; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_vd_addr = data_3_vd_addr; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_ve_addr = data_3_ve_addr; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_vf_addr = data_3_vf_addr; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_vg_addr = data_3_vg_addr; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_vs_valid = data_3_vs_valid; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_vs_addr = data_3_vs_addr; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_vs_tag = data_3_vs_tag; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_vt_valid = data_3_vt_valid; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_vt_addr = data_3_vt_addr; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_vt_tag = data_3_vt_tag; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_vu_valid = data_3_vu_valid; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_vu_addr = data_3_vu_addr; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_vu_tag = data_3_vu_tag; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_vx_valid = data_3_vx_valid; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_vx_addr = data_3_vx_addr; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_vx_tag = data_3_vx_tag; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_vy_valid = data_3_vy_valid; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_vy_addr = data_3_vy_addr; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_vy_tag = data_3_vy_tag; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_vz_valid = data_3_vz_valid; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_vz_addr = data_3_vz_addr; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_vz_tag = data_3_vz_tag; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_sv_valid = data_3_sv_valid; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_sv_addr = data_3_sv_addr; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_sv_data = data_3_sv_data; // @[VDecode.scala 361:20]
+ assign io_out_3_bits_cmdsync = data_3_cmdsync; // @[VDecode.scala 361:20]
+ assign io_cmdq_0_alu = cmdq_0_alu; // @[VDecode.scala 362:16]
+ assign io_cmdq_0_conv = cmdq_0_conv; // @[VDecode.scala 362:16]
+ assign io_cmdq_0_ldst = cmdq_0_ldst; // @[VDecode.scala 362:16]
+ assign io_cmdq_0_ld = cmdq_0_ld; // @[VDecode.scala 362:16]
+ assign io_cmdq_0_st = cmdq_0_st; // @[VDecode.scala 362:16]
+ assign io_cmdq_1_alu = cmdq_1_alu; // @[VDecode.scala 362:16]
+ assign io_cmdq_1_conv = cmdq_1_conv; // @[VDecode.scala 362:16]
+ assign io_cmdq_1_ldst = cmdq_1_ldst; // @[VDecode.scala 362:16]
+ assign io_cmdq_1_ld = cmdq_1_ld; // @[VDecode.scala 362:16]
+ assign io_cmdq_1_st = cmdq_1_st; // @[VDecode.scala 362:16]
+ assign io_cmdq_2_alu = cmdq_2_alu; // @[VDecode.scala 362:16]
+ assign io_cmdq_2_conv = cmdq_2_conv; // @[VDecode.scala 362:16]
+ assign io_cmdq_2_ldst = cmdq_2_ldst; // @[VDecode.scala 362:16]
+ assign io_cmdq_2_ld = cmdq_2_ld; // @[VDecode.scala 362:16]
+ assign io_cmdq_2_st = cmdq_2_st; // @[VDecode.scala 362:16]
+ assign io_cmdq_3_alu = cmdq_3_alu; // @[VDecode.scala 362:16]
+ assign io_cmdq_3_conv = cmdq_3_conv; // @[VDecode.scala 362:16]
+ assign io_cmdq_3_ldst = cmdq_3_ldst; // @[VDecode.scala 362:16]
+ assign io_cmdq_3_ld = cmdq_3_ld; // @[VDecode.scala 362:16]
+ assign io_cmdq_3_st = cmdq_3_st; // @[VDecode.scala 362:16]
assign io_stall = _io_stall_T_1 > 5'h10; // @[VDecode.scala 142:37]
assign io_vrfsb_set_valid = output_[0] | output_[1] | output_[2] | output_[3]; // @[VDecode.scala 330:61]
assign io_vrfsb_set_bits = _io_vrfsb_set_bits_T_7 | _io_vrfsb_set_bits_T_9; // @[VDecode.scala 334:60]
assign io_undef = io_in_valid & (d_0_io_undef | d_1_io_undef | d_2_io_undef | d_3_io_undef); // @[VDecode.scala 109:27]
- assign io_nempty = nempty; // @[VDecode.scala 375:13]
+ assign io_nempty = nempty; // @[VDecode.scala 373:13]
assign f_clock = clock;
assign f_reset = reset;
assign f_io_in_valid = io_in_valid; // @[VDecode.scala 113:11]
@@ -42118,7 +41931,7 @@
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VDecode.scala 373:40]
+ if (reset) begin // @[VDecode.scala 371:40]
nempty <= 1'h0;
end else begin
nempty <= io_in_valid | f_io_nempty | _dataEn_T_2;
@@ -88016,41 +87829,41 @@
wire [1:0] _opos_T_1 = opos + 2'h1; // @[Slice.scala 39:18]
wire full = ipos[0] == opos[0] & ipos[1] != opos[1]; // @[Slice.scala 47:36]
wire _io_in_ready_T = ~full; // @[Slice.scala 49:22]
- wire _T_3 = ivalid & ~ovalid; // @[Slice.scala 77:18]
- wire _T_5 = ivalid & ovalid; // @[Slice.scala 78:18]
- wire _T_7 = ivalid & ovalid & _io_in_ready_T; // @[Slice.scala 78:28]
- wire _T_8 = ivalid & ~ovalid & empty | _T_7; // @[Slice.scala 77:38]
- wire _T_14 = _T_5 & full; // @[Slice.scala 83:28]
- wire _T_15 = _T_3 & ~empty | _T_14; // @[Slice.scala 82:39]
+ wire _T_3 = ivalid & ~ovalid; // @[Slice.scala 58:18]
+ wire _T_5 = ivalid & ovalid; // @[Slice.scala 59:18]
+ wire _T_7 = ivalid & ovalid & _io_in_ready_T; // @[Slice.scala 59:28]
+ wire _T_8 = ivalid & ~ovalid & empty | _T_7; // @[Slice.scala 58:38]
+ wire _T_14 = _T_5 & full; // @[Slice.scala 64:28]
+ wire _T_15 = _T_3 & ~empty | _T_14; // @[Slice.scala 63:39]
assign io_in_ready = ~full | io_out_ready; // @[Slice.scala 49:28]
- assign io_out_valid = ~empty; // @[Slice.scala 107:21]
- assign io_out_bits_widx = mem_0_widx; // @[Slice.scala 108:18]
- assign io_out_bits_addr = mem_0_addr; // @[Slice.scala 108:18]
- assign io_out_bits_size = mem_0_size; // @[Slice.scala 108:18]
+ assign io_out_valid = ~empty; // @[Slice.scala 88:21]
+ assign io_out_bits_widx = mem_0_widx; // @[Slice.scala 89:18]
+ assign io_out_bits_addr = mem_0_addr; // @[Slice.scala 89:18]
+ assign io_out_bits_size = mem_0_size; // @[Slice.scala 89:18]
always @(posedge clock) begin
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_widx <= io_in_bits_widx; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_widx <= mem_1_widx; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_widx <= io_in_bits_widx; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_widx <= mem_1_widx; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_addr <= io_in_bits_addr; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_addr <= mem_1_addr; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_addr <= io_in_bits_addr; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_addr <= mem_1_addr; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_size <= io_in_bits_size; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_size <= mem_1_size; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_size <= io_in_bits_size; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_size <= mem_1_size; // @[Slice.scala 55:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_widx <= io_in_bits_widx; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_widx <= io_in_bits_widx; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_addr <= io_in_bits_addr; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_addr <= io_in_bits_addr; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_size <= io_in_bits_size; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_size <= io_in_bits_size; // @[Slice.scala 65:14]
end
end
always @(posedge clock or posedge reset) begin
@@ -88154,12 +87967,12 @@
wire empty = ipos == opos; // @[Slice.scala 29:20]
wire ivalid = io_in_valid & io_in_ready; // @[Slice.scala 31:28]
wire ovalid = io_out_valid & io_out_ready; // @[Slice.scala 32:29]
- assign io_in_ready = empty | io_out_ready; // @[Slice.scala 93:28]
- assign io_out_valid = ~empty; // @[Slice.scala 107:21]
- assign io_out_bits = mem_0; // @[Slice.scala 108:18]
+ assign io_in_ready = empty | io_out_ready; // @[Slice.scala 74:28]
+ assign io_out_valid = ~empty; // @[Slice.scala 88:21]
+ assign io_out_bits = mem_0; // @[Slice.scala 89:18]
always @(posedge clock) begin
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0 <= io_in_bits; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0 <= io_in_bits; // @[Slice.scala 80:14]
end
end
always @(posedge clock or posedge reset) begin
@@ -102511,66 +102324,66 @@
reg [5:0] value_tin_vd_addr; // @[VCmdq.scala 37:18]
reg value_m; // @[VCmdq.scala 37:18]
reg [4:0] step; // @[VCmdq.scala 42:21]
- wire [4:0] addrAlign = value_tin_addr[4:0]; // @[VLd.scala 86:28]
- wire [4:0] offsAlign = value_tin_offset[4:0]; // @[VLd.scala 87:30]
- wire _T_2 = ~reset; // @[VLd.scala 88:11]
- wire _T_8 = ~valid; // @[VLd.scala 90:12]
- wire _outlast_T = ~value_m; // @[VLd.scala 95:19]
- wire last = _outlast_T | step == 5'h3; // @[VLd.scala 97:19]
- wire [5:0] tin_vd_addr = value_tin_vd_addr + 6'h1; // @[VLd.scala 101:31]
- wire [31:0] tin_addr = value_tin_addr + value_tin_offset; // @[VLd.scala 103:27]
- wire f_io_in_bits_0_bits_tin_stride = io_in_bits_0_bits_f2[1]; // @[VLd.scala 56:23]
+ wire [4:0] addrAlign = value_tin_addr[4:0]; // @[VLd.scala 87:28]
+ wire [4:0] offsAlign = value_tin_offset[4:0]; // @[VLd.scala 88:30]
+ wire _T_2 = ~reset; // @[VLd.scala 89:11]
+ wire _T_8 = ~valid; // @[VLd.scala 91:12]
+ wire _outlast_T = ~value_m; // @[VLd.scala 96:19]
+ wire last = _outlast_T | step == 5'h3; // @[VLd.scala 98:19]
+ wire [5:0] tin_vd_addr = value_tin_vd_addr + 6'h1; // @[VLd.scala 102:31]
+ wire [31:0] tin_addr = value_tin_addr + value_tin_offset; // @[VLd.scala 104:27]
+ wire f_io_in_bits_0_bits_tin_stride = io_in_bits_0_bits_f2[1]; // @[VLd.scala 57:23]
wire [1:0] _f_io_in_bits_0_bits_tin_T_3 = io_in_bits_0_bits_sz[1] + io_in_bits_0_bits_sz[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_47 = {{1'd0}, io_in_bits_0_bits_sz[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _f_io_in_bits_0_bits_tin_T_5 = _GEN_47 + _f_io_in_bits_0_bits_tin_T_3; // @[Bitwise.scala 48:55]
wire [31:0] _f_io_in_bits_0_bits_tin_data_T_1 = io_in_bits_0_bits_sz[0] ? io_in_bits_0_bits_sv_data : 32'h0; // @[Library.scala 8:8]
wire [32:0] _f_io_in_bits_0_bits_tin_data_T_3 = {io_in_bits_0_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
wire [32:0] _f_io_in_bits_0_bits_tin_data_T_4 = io_in_bits_0_bits_sz[1] ? _f_io_in_bits_0_bits_tin_data_T_3 : 33'h0; // @[Library.scala 8:8]
- wire [32:0] _GEN_48 = {{1'd0}, _f_io_in_bits_0_bits_tin_data_T_1}; // @[VLd.scala 63:44]
- wire [32:0] _f_io_in_bits_0_bits_tin_data_T_5 = _GEN_48 | _f_io_in_bits_0_bits_tin_data_T_4; // @[VLd.scala 63:44]
+ wire [32:0] _GEN_48 = {{1'd0}, _f_io_in_bits_0_bits_tin_data_T_1}; // @[VLd.scala 64:44]
+ wire [32:0] _f_io_in_bits_0_bits_tin_data_T_5 = _GEN_48 | _f_io_in_bits_0_bits_tin_data_T_4; // @[VLd.scala 64:44]
wire [33:0] _f_io_in_bits_0_bits_tin_data_T_7 = {io_in_bits_0_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
wire [33:0] _f_io_in_bits_0_bits_tin_data_T_8 = io_in_bits_0_bits_sz[2] ? _f_io_in_bits_0_bits_tin_data_T_7 : 34'h0; // @[Library.scala 8:8]
- wire [33:0] _GEN_49 = {{1'd0}, _f_io_in_bits_0_bits_tin_data_T_5}; // @[VLd.scala 64:59]
- wire [33:0] f_io_in_bits_0_bits_tin_data = _GEN_49 | _f_io_in_bits_0_bits_tin_data_T_8; // @[VLd.scala 64:59]
- wire f_io_in_bits_1_bits_tin_stride = io_in_bits_1_bits_f2[1]; // @[VLd.scala 56:23]
+ wire [33:0] _GEN_49 = {{1'd0}, _f_io_in_bits_0_bits_tin_data_T_5}; // @[VLd.scala 65:59]
+ wire [33:0] f_io_in_bits_0_bits_tin_data = _GEN_49 | _f_io_in_bits_0_bits_tin_data_T_8; // @[VLd.scala 65:59]
+ wire f_io_in_bits_1_bits_tin_stride = io_in_bits_1_bits_f2[1]; // @[VLd.scala 57:23]
wire [1:0] _f_io_in_bits_1_bits_tin_T_3 = io_in_bits_1_bits_sz[1] + io_in_bits_1_bits_sz[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_51 = {{1'd0}, io_in_bits_1_bits_sz[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _f_io_in_bits_1_bits_tin_T_5 = _GEN_51 + _f_io_in_bits_1_bits_tin_T_3; // @[Bitwise.scala 48:55]
wire [31:0] _f_io_in_bits_1_bits_tin_data_T_1 = io_in_bits_1_bits_sz[0] ? io_in_bits_1_bits_sv_data : 32'h0; // @[Library.scala 8:8]
wire [32:0] _f_io_in_bits_1_bits_tin_data_T_3 = {io_in_bits_1_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
wire [32:0] _f_io_in_bits_1_bits_tin_data_T_4 = io_in_bits_1_bits_sz[1] ? _f_io_in_bits_1_bits_tin_data_T_3 : 33'h0; // @[Library.scala 8:8]
- wire [32:0] _GEN_52 = {{1'd0}, _f_io_in_bits_1_bits_tin_data_T_1}; // @[VLd.scala 63:44]
- wire [32:0] _f_io_in_bits_1_bits_tin_data_T_5 = _GEN_52 | _f_io_in_bits_1_bits_tin_data_T_4; // @[VLd.scala 63:44]
+ wire [32:0] _GEN_52 = {{1'd0}, _f_io_in_bits_1_bits_tin_data_T_1}; // @[VLd.scala 64:44]
+ wire [32:0] _f_io_in_bits_1_bits_tin_data_T_5 = _GEN_52 | _f_io_in_bits_1_bits_tin_data_T_4; // @[VLd.scala 64:44]
wire [33:0] _f_io_in_bits_1_bits_tin_data_T_7 = {io_in_bits_1_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
wire [33:0] _f_io_in_bits_1_bits_tin_data_T_8 = io_in_bits_1_bits_sz[2] ? _f_io_in_bits_1_bits_tin_data_T_7 : 34'h0; // @[Library.scala 8:8]
- wire [33:0] _GEN_53 = {{1'd0}, _f_io_in_bits_1_bits_tin_data_T_5}; // @[VLd.scala 64:59]
- wire [33:0] f_io_in_bits_1_bits_tin_data = _GEN_53 | _f_io_in_bits_1_bits_tin_data_T_8; // @[VLd.scala 64:59]
- wire f_io_in_bits_2_bits_tin_stride = io_in_bits_2_bits_f2[1]; // @[VLd.scala 56:23]
+ wire [33:0] _GEN_53 = {{1'd0}, _f_io_in_bits_1_bits_tin_data_T_5}; // @[VLd.scala 65:59]
+ wire [33:0] f_io_in_bits_1_bits_tin_data = _GEN_53 | _f_io_in_bits_1_bits_tin_data_T_8; // @[VLd.scala 65:59]
+ wire f_io_in_bits_2_bits_tin_stride = io_in_bits_2_bits_f2[1]; // @[VLd.scala 57:23]
wire [1:0] _f_io_in_bits_2_bits_tin_T_3 = io_in_bits_2_bits_sz[1] + io_in_bits_2_bits_sz[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_55 = {{1'd0}, io_in_bits_2_bits_sz[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _f_io_in_bits_2_bits_tin_T_5 = _GEN_55 + _f_io_in_bits_2_bits_tin_T_3; // @[Bitwise.scala 48:55]
wire [31:0] _f_io_in_bits_2_bits_tin_data_T_1 = io_in_bits_2_bits_sz[0] ? io_in_bits_2_bits_sv_data : 32'h0; // @[Library.scala 8:8]
wire [32:0] _f_io_in_bits_2_bits_tin_data_T_3 = {io_in_bits_2_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
wire [32:0] _f_io_in_bits_2_bits_tin_data_T_4 = io_in_bits_2_bits_sz[1] ? _f_io_in_bits_2_bits_tin_data_T_3 : 33'h0; // @[Library.scala 8:8]
- wire [32:0] _GEN_56 = {{1'd0}, _f_io_in_bits_2_bits_tin_data_T_1}; // @[VLd.scala 63:44]
- wire [32:0] _f_io_in_bits_2_bits_tin_data_T_5 = _GEN_56 | _f_io_in_bits_2_bits_tin_data_T_4; // @[VLd.scala 63:44]
+ wire [32:0] _GEN_56 = {{1'd0}, _f_io_in_bits_2_bits_tin_data_T_1}; // @[VLd.scala 64:44]
+ wire [32:0] _f_io_in_bits_2_bits_tin_data_T_5 = _GEN_56 | _f_io_in_bits_2_bits_tin_data_T_4; // @[VLd.scala 64:44]
wire [33:0] _f_io_in_bits_2_bits_tin_data_T_7 = {io_in_bits_2_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
wire [33:0] _f_io_in_bits_2_bits_tin_data_T_8 = io_in_bits_2_bits_sz[2] ? _f_io_in_bits_2_bits_tin_data_T_7 : 34'h0; // @[Library.scala 8:8]
- wire [33:0] _GEN_57 = {{1'd0}, _f_io_in_bits_2_bits_tin_data_T_5}; // @[VLd.scala 64:59]
- wire [33:0] f_io_in_bits_2_bits_tin_data = _GEN_57 | _f_io_in_bits_2_bits_tin_data_T_8; // @[VLd.scala 64:59]
- wire f_io_in_bits_3_bits_tin_stride = io_in_bits_3_bits_f2[1]; // @[VLd.scala 56:23]
+ wire [33:0] _GEN_57 = {{1'd0}, _f_io_in_bits_2_bits_tin_data_T_5}; // @[VLd.scala 65:59]
+ wire [33:0] f_io_in_bits_2_bits_tin_data = _GEN_57 | _f_io_in_bits_2_bits_tin_data_T_8; // @[VLd.scala 65:59]
+ wire f_io_in_bits_3_bits_tin_stride = io_in_bits_3_bits_f2[1]; // @[VLd.scala 57:23]
wire [1:0] _f_io_in_bits_3_bits_tin_T_3 = io_in_bits_3_bits_sz[1] + io_in_bits_3_bits_sz[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_59 = {{1'd0}, io_in_bits_3_bits_sz[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _f_io_in_bits_3_bits_tin_T_5 = _GEN_59 + _f_io_in_bits_3_bits_tin_T_3; // @[Bitwise.scala 48:55]
wire [31:0] _f_io_in_bits_3_bits_tin_data_T_1 = io_in_bits_3_bits_sz[0] ? io_in_bits_3_bits_sv_data : 32'h0; // @[Library.scala 8:8]
wire [32:0] _f_io_in_bits_3_bits_tin_data_T_3 = {io_in_bits_3_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
wire [32:0] _f_io_in_bits_3_bits_tin_data_T_4 = io_in_bits_3_bits_sz[1] ? _f_io_in_bits_3_bits_tin_data_T_3 : 33'h0; // @[Library.scala 8:8]
- wire [32:0] _GEN_60 = {{1'd0}, _f_io_in_bits_3_bits_tin_data_T_1}; // @[VLd.scala 63:44]
- wire [32:0] _f_io_in_bits_3_bits_tin_data_T_5 = _GEN_60 | _f_io_in_bits_3_bits_tin_data_T_4; // @[VLd.scala 63:44]
+ wire [32:0] _GEN_60 = {{1'd0}, _f_io_in_bits_3_bits_tin_data_T_1}; // @[VLd.scala 64:44]
+ wire [32:0] _f_io_in_bits_3_bits_tin_data_T_5 = _GEN_60 | _f_io_in_bits_3_bits_tin_data_T_4; // @[VLd.scala 64:44]
wire [33:0] _f_io_in_bits_3_bits_tin_data_T_7 = {io_in_bits_3_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
wire [33:0] _f_io_in_bits_3_bits_tin_data_T_8 = io_in_bits_3_bits_sz[2] ? _f_io_in_bits_3_bits_tin_data_T_7 : 34'h0; // @[Library.scala 8:8]
- wire [33:0] _GEN_61 = {{1'd0}, _f_io_in_bits_3_bits_tin_data_T_5}; // @[VLd.scala 64:59]
- wire [33:0] f_io_in_bits_3_bits_tin_data = _GEN_61 | _f_io_in_bits_3_bits_tin_data_T_8; // @[VLd.scala 64:59]
+ wire [33:0] _GEN_61 = {{1'd0}, _f_io_in_bits_3_bits_tin_data_T_5}; // @[VLd.scala 65:59]
+ wire [33:0] f_io_in_bits_3_bits_tin_data = _GEN_61 | _f_io_in_bits_3_bits_tin_data_T_8; // @[VLd.scala 65:59]
wire _T_16 = ~last; // @[VCmdq.scala 66:11]
wire [4:0] _step_T_1 = step + 5'h1; // @[VCmdq.scala 70:20]
wire _GEN_10 = ~last & value_m; // @[VCmdq.scala 66:18 69:15 75:15]
@@ -102622,28 +102435,28 @@
assign f_reset = reset;
assign f_io_in_valid = io_in_valid; // @[VCmdq.scala 48:17]
assign f_io_in_bits_0_valid = io_in_bits_0_valid; // @[VCmdq.scala 52:27]
- assign f_io_in_bits_0_bits_tin_op = io_in_bits_0_bits_op; // @[VLd.scala 55:19 72:12]
- assign f_io_in_bits_0_bits_tin_addr = io_in_bits_0_bits_sv_addr; // @[VLd.scala 55:19 75:14]
- assign f_io_in_bits_0_bits_tin_offset = f_io_in_bits_0_bits_tin_stride ? f_io_in_bits_0_bits_tin_data[31:0] : 32'h20; // @[VLd.scala 76:22]
- assign f_io_in_bits_0_bits_tin_vd_addr = io_in_bits_0_bits_vd_addr; // @[VLd.scala 55:19 78:12]
+ assign f_io_in_bits_0_bits_tin_op = io_in_bits_0_bits_op; // @[VLd.scala 56:19 73:12]
+ assign f_io_in_bits_0_bits_tin_addr = io_in_bits_0_bits_sv_addr; // @[VLd.scala 56:19 76:14]
+ assign f_io_in_bits_0_bits_tin_offset = f_io_in_bits_0_bits_tin_stride ? f_io_in_bits_0_bits_tin_data[31:0] : 32'h20; // @[VLd.scala 77:22]
+ assign f_io_in_bits_0_bits_tin_vd_addr = io_in_bits_0_bits_vd_addr; // @[VLd.scala 56:19 79:12]
assign f_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VCmdq.scala 54:28]
assign f_io_in_bits_1_valid = io_in_bits_1_valid; // @[VCmdq.scala 52:27]
- assign f_io_in_bits_1_bits_tin_op = io_in_bits_1_bits_op; // @[VLd.scala 55:19 72:12]
- assign f_io_in_bits_1_bits_tin_addr = io_in_bits_1_bits_sv_addr; // @[VLd.scala 55:19 75:14]
- assign f_io_in_bits_1_bits_tin_offset = f_io_in_bits_1_bits_tin_stride ? f_io_in_bits_1_bits_tin_data[31:0] : 32'h20; // @[VLd.scala 76:22]
- assign f_io_in_bits_1_bits_tin_vd_addr = io_in_bits_1_bits_vd_addr; // @[VLd.scala 55:19 78:12]
+ assign f_io_in_bits_1_bits_tin_op = io_in_bits_1_bits_op; // @[VLd.scala 56:19 73:12]
+ assign f_io_in_bits_1_bits_tin_addr = io_in_bits_1_bits_sv_addr; // @[VLd.scala 56:19 76:14]
+ assign f_io_in_bits_1_bits_tin_offset = f_io_in_bits_1_bits_tin_stride ? f_io_in_bits_1_bits_tin_data[31:0] : 32'h20; // @[VLd.scala 77:22]
+ assign f_io_in_bits_1_bits_tin_vd_addr = io_in_bits_1_bits_vd_addr; // @[VLd.scala 56:19 79:12]
assign f_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VCmdq.scala 54:28]
assign f_io_in_bits_2_valid = io_in_bits_2_valid; // @[VCmdq.scala 52:27]
- assign f_io_in_bits_2_bits_tin_op = io_in_bits_2_bits_op; // @[VLd.scala 55:19 72:12]
- assign f_io_in_bits_2_bits_tin_addr = io_in_bits_2_bits_sv_addr; // @[VLd.scala 55:19 75:14]
- assign f_io_in_bits_2_bits_tin_offset = f_io_in_bits_2_bits_tin_stride ? f_io_in_bits_2_bits_tin_data[31:0] : 32'h20; // @[VLd.scala 76:22]
- assign f_io_in_bits_2_bits_tin_vd_addr = io_in_bits_2_bits_vd_addr; // @[VLd.scala 55:19 78:12]
+ assign f_io_in_bits_2_bits_tin_op = io_in_bits_2_bits_op; // @[VLd.scala 56:19 73:12]
+ assign f_io_in_bits_2_bits_tin_addr = io_in_bits_2_bits_sv_addr; // @[VLd.scala 56:19 76:14]
+ assign f_io_in_bits_2_bits_tin_offset = f_io_in_bits_2_bits_tin_stride ? f_io_in_bits_2_bits_tin_data[31:0] : 32'h20; // @[VLd.scala 77:22]
+ assign f_io_in_bits_2_bits_tin_vd_addr = io_in_bits_2_bits_vd_addr; // @[VLd.scala 56:19 79:12]
assign f_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VCmdq.scala 54:28]
assign f_io_in_bits_3_valid = io_in_bits_3_valid; // @[VCmdq.scala 52:27]
- assign f_io_in_bits_3_bits_tin_op = io_in_bits_3_bits_op; // @[VLd.scala 55:19 72:12]
- assign f_io_in_bits_3_bits_tin_addr = io_in_bits_3_bits_sv_addr; // @[VLd.scala 55:19 75:14]
- assign f_io_in_bits_3_bits_tin_offset = f_io_in_bits_3_bits_tin_stride ? f_io_in_bits_3_bits_tin_data[31:0] : 32'h20; // @[VLd.scala 76:22]
- assign f_io_in_bits_3_bits_tin_vd_addr = io_in_bits_3_bits_vd_addr; // @[VLd.scala 55:19 78:12]
+ assign f_io_in_bits_3_bits_tin_op = io_in_bits_3_bits_op; // @[VLd.scala 56:19 73:12]
+ assign f_io_in_bits_3_bits_tin_addr = io_in_bits_3_bits_sv_addr; // @[VLd.scala 56:19 76:14]
+ assign f_io_in_bits_3_bits_tin_offset = f_io_in_bits_3_bits_tin_stride ? f_io_in_bits_3_bits_tin_data[31:0] : 32'h20; // @[VLd.scala 77:22]
+ assign f_io_in_bits_3_bits_tin_vd_addr = io_in_bits_3_bits_vd_addr; // @[VLd.scala 56:19 79:12]
assign f_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VCmdq.scala 54:28]
assign f_io_out_ready = _T_8 | io_out_ready & last; // @[VCmdq.scala 57:28]
always @(posedge clock) begin
@@ -102699,28 +102512,6 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(addrAlign == 5'h0)) begin
- $fatal; // @[VLd.scala 88:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(addrAlign == 5'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:88 assert(addrAlign === 0.U)\n"); // @[VLd.scala 88:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(offsAlign == 5'h0)) begin
$fatal; // @[VLd.scala 89:11]
end
`ifdef STOP_COND
@@ -102731,8 +102522,8 @@
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
- if (_T_2 & ~(offsAlign == 5'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:89 assert(offsAlign === 0.U)\n"); // @[VLd.scala 89:11]
+ if (~reset & ~(addrAlign == 5'h0)) begin
+ $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:89 assert(addrAlign === 0.U)\n"); // @[VLd.scala 89:11]
end
`ifdef PRINTF_COND
end
@@ -102742,7 +102533,7 @@
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
- if (_T_2 & ~(~valid | value_tin_op == 7'h2)) begin
+ if (_T_2 & ~(offsAlign == 5'h0)) begin
$fatal; // @[VLd.scala 90:11]
end
`ifdef STOP_COND
@@ -102753,8 +102544,30 @@
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
+ if (_T_2 & ~(offsAlign == 5'h0)) begin
+ $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:90 assert(offsAlign === 0.U)\n"); // @[VLd.scala 90:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
if (_T_2 & ~(~valid | value_tin_op == 7'h2)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:90 assert(!valid || in.op === e.vld.U)\n"); // @[VLd.scala 90:11]
+ $fatal; // @[VLd.scala 91:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~(~valid | value_tin_op == 7'h2)) begin
+ $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:91 assert(!valid || in.op === e.vld.U)\n"); // @[VLd.scala 91:11]
end
`ifdef PRINTF_COND
end
@@ -102765,7 +102578,7 @@
if (`STOP_COND) begin
`endif
if (_T_2 & ~(_f_io_in_bits_0_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VLd.scala 58:11]
+ $fatal; // @[VLd.scala 59:11]
end
`ifdef STOP_COND
end
@@ -102776,7 +102589,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_2 & ~(_f_io_in_bits_0_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:58 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLd.scala 58:11]
+ $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:59 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLd.scala 59:11]
end
`ifdef PRINTF_COND
end
@@ -102788,7 +102601,7 @@
`endif
if (_T_2 & ~(~(io_in_bits_0_bits_op == 7'h2 & (~io_in_bits_0_bits_vd_valid | io_in_bits_0_bits_vs_valid)))
) begin
- $fatal; // @[VLd.scala 59:11]
+ $fatal; // @[VLd.scala 60:11]
end
`ifdef STOP_COND
end
@@ -102801,7 +102614,7 @@
if (_T_2 & ~(~(io_in_bits_0_bits_op == 7'h2 & (~io_in_bits_0_bits_vd_valid | io_in_bits_0_bits_vs_valid)))
) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VLd.scala:59 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"); // @[VLd.scala 59:11]
+ "Assertion failed\n at VLd.scala:60 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"); // @[VLd.scala 60:11]
end
`ifdef PRINTF_COND
end
@@ -102812,7 +102625,7 @@
if (`STOP_COND) begin
`endif
if (_T_2 & ~(_f_io_in_bits_1_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VLd.scala 58:11]
+ $fatal; // @[VLd.scala 59:11]
end
`ifdef STOP_COND
end
@@ -102823,7 +102636,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_2 & ~(_f_io_in_bits_1_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:58 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLd.scala 58:11]
+ $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:59 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLd.scala 59:11]
end
`ifdef PRINTF_COND
end
@@ -102835,7 +102648,7 @@
`endif
if (_T_2 & ~(~(io_in_bits_1_bits_op == 7'h2 & (~io_in_bits_1_bits_vd_valid | io_in_bits_1_bits_vs_valid)))
) begin
- $fatal; // @[VLd.scala 59:11]
+ $fatal; // @[VLd.scala 60:11]
end
`ifdef STOP_COND
end
@@ -102848,7 +102661,7 @@
if (_T_2 & ~(~(io_in_bits_1_bits_op == 7'h2 & (~io_in_bits_1_bits_vd_valid | io_in_bits_1_bits_vs_valid)))
) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VLd.scala:59 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"); // @[VLd.scala 59:11]
+ "Assertion failed\n at VLd.scala:60 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"); // @[VLd.scala 60:11]
end
`ifdef PRINTF_COND
end
@@ -102859,7 +102672,7 @@
if (`STOP_COND) begin
`endif
if (_T_2 & ~(_f_io_in_bits_2_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VLd.scala 58:11]
+ $fatal; // @[VLd.scala 59:11]
end
`ifdef STOP_COND
end
@@ -102870,7 +102683,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_2 & ~(_f_io_in_bits_2_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:58 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLd.scala 58:11]
+ $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:59 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLd.scala 59:11]
end
`ifdef PRINTF_COND
end
@@ -102882,7 +102695,7 @@
`endif
if (_T_2 & ~(~(io_in_bits_2_bits_op == 7'h2 & (~io_in_bits_2_bits_vd_valid | io_in_bits_2_bits_vs_valid)))
) begin
- $fatal; // @[VLd.scala 59:11]
+ $fatal; // @[VLd.scala 60:11]
end
`ifdef STOP_COND
end
@@ -102895,7 +102708,7 @@
if (_T_2 & ~(~(io_in_bits_2_bits_op == 7'h2 & (~io_in_bits_2_bits_vd_valid | io_in_bits_2_bits_vs_valid)))
) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VLd.scala:59 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"); // @[VLd.scala 59:11]
+ "Assertion failed\n at VLd.scala:60 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"); // @[VLd.scala 60:11]
end
`ifdef PRINTF_COND
end
@@ -102906,7 +102719,7 @@
if (`STOP_COND) begin
`endif
if (_T_2 & ~(_f_io_in_bits_3_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VLd.scala 58:11]
+ $fatal; // @[VLd.scala 59:11]
end
`ifdef STOP_COND
end
@@ -102917,7 +102730,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_2 & ~(_f_io_in_bits_3_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:58 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLd.scala 58:11]
+ $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:59 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLd.scala 59:11]
end
`ifdef PRINTF_COND
end
@@ -102929,7 +102742,7 @@
`endif
if (_T_2 & ~(~(io_in_bits_3_bits_op == 7'h2 & (~io_in_bits_3_bits_vd_valid | io_in_bits_3_bits_vs_valid)))
) begin
- $fatal; // @[VLd.scala 59:11]
+ $fatal; // @[VLd.scala 60:11]
end
`ifdef STOP_COND
end
@@ -102942,7 +102755,7 @@
if (_T_2 & ~(~(io_in_bits_3_bits_op == 7'h2 & (~io_in_bits_3_bits_vd_valid | io_in_bits_3_bits_vs_valid)))
) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VLd.scala:59 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"); // @[VLd.scala 59:11]
+ "Assertion failed\n at VLd.scala:60 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"); // @[VLd.scala 60:11]
end
`ifdef PRINTF_COND
end
@@ -103144,16 +102957,16 @@
wire [31:0] q_io_out_bits_addr; // @[VCmdq.scala 14:11]
wire [5:0] q_io_out_bits_vd_addr; // @[VCmdq.scala 14:11]
wire q_io_nempty; // @[VCmdq.scala 14:11]
- wire _T_5 = ~reset; // @[VLd.scala 125:9]
- reg nempty; // @[VLd.scala 140:23]
- reg [6:0] count; // @[VLd.scala 141:22]
- wire inc = io_axi_addr_valid & io_axi_addr_ready; // @[VLd.scala 142:31]
- wire dec = io_axi_data_valid & io_axi_data_ready; // @[VLd.scala 143:31]
- wire _T_13 = inc | dec; // @[VLd.scala 145:13]
- wire [6:0] _GEN_2 = {{6'd0}, inc}; // @[VLd.scala 146:26]
- wire [6:0] _nxtcount_T_1 = count + _GEN_2; // @[VLd.scala 146:26]
- wire [6:0] _GEN_3 = {{6'd0}, dec}; // @[VLd.scala 146:32]
- wire [6:0] nxtcount = _nxtcount_T_1 - _GEN_3; // @[VLd.scala 146:32]
+ wire _T_5 = ~reset; // @[VLd.scala 126:9]
+ reg nempty; // @[VLd.scala 141:23]
+ reg [6:0] count; // @[VLd.scala 142:22]
+ wire inc = io_axi_addr_valid & io_axi_addr_ready; // @[VLd.scala 143:31]
+ wire dec = io_axi_data_valid & io_axi_data_ready; // @[VLd.scala 144:31]
+ wire _T_13 = inc | dec; // @[VLd.scala 146:13]
+ wire [6:0] _GEN_2 = {{6'd0}, inc}; // @[VLd.scala 147:26]
+ wire [6:0] _nxtcount_T_1 = count + _GEN_2; // @[VLd.scala 147:26]
+ wire [6:0] _GEN_3 = {{6'd0}, dec}; // @[VLd.scala 147:32]
+ wire [6:0] nxtcount = _nxtcount_T_1 - _GEN_3; // @[VLd.scala 147:32]
VCmdq_4 q ( // @[VCmdq.scala 14:11]
.clock(q_clock),
.reset(q_reset),
@@ -103205,88 +103018,65 @@
.io_out_bits_vd_addr(q_io_out_bits_vd_addr),
.io_nempty(q_io_nempty)
);
- assign io_in_ready = q_io_in_ready; // @[VLd.scala 118:11]
- assign io_write_valid = io_axi_data_valid; // @[VLd.scala 132:18]
- assign io_write_addr = io_axi_data_bits_id; // @[VLd.scala 134:17]
- assign io_write_data = io_axi_data_bits_data; // @[VLd.scala 133:17]
- assign io_axi_addr_valid = q_io_out_valid; // @[VLd.scala 122:21]
+ assign io_in_ready = q_io_in_ready; // @[VLd.scala 119:11]
+ assign io_write_valid = io_axi_data_valid; // @[VLd.scala 133:18]
+ assign io_write_addr = io_axi_data_bits_id; // @[VLd.scala 135:17]
+ assign io_write_data = io_axi_data_bits_data; // @[VLd.scala 134:17]
+ assign io_axi_addr_valid = q_io_out_valid; // @[VLd.scala 123:21]
assign io_axi_addr_bits_addr = {1'h0,q_io_out_bits_addr[30:0]}; // @[Cat.scala 31:58]
- assign io_axi_addr_bits_id = q_io_out_bits_vd_addr; // @[VLd.scala 124:23]
- assign io_axi_data_ready = 1'h1; // @[VLd.scala 136:21]
- assign io_nempty = q_io_nempty | nempty; // @[VLd.scala 152:28]
+ assign io_axi_addr_bits_id = q_io_out_bits_vd_addr; // @[VLd.scala 125:23]
+ assign io_axi_data_ready = 1'h1; // @[VLd.scala 137:21]
+ assign io_nempty = q_io_nempty | nempty; // @[VLd.scala 153:28]
assign q_clock = clock;
assign q_reset = reset;
- assign q_io_in_valid = io_in_valid; // @[VLd.scala 118:11]
- assign q_io_in_bits_0_valid = io_in_bits_0_valid; // @[VLd.scala 118:11]
- assign q_io_in_bits_0_bits_op = io_in_bits_0_bits_op; // @[VLd.scala 118:11]
- assign q_io_in_bits_0_bits_f2 = io_in_bits_0_bits_f2; // @[VLd.scala 118:11]
- assign q_io_in_bits_0_bits_sz = io_in_bits_0_bits_sz; // @[VLd.scala 118:11]
- assign q_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VLd.scala 118:11]
- assign q_io_in_bits_0_bits_vd_valid = io_in_bits_0_bits_vd_valid; // @[VLd.scala 118:11]
- assign q_io_in_bits_0_bits_vd_addr = io_in_bits_0_bits_vd_addr; // @[VLd.scala 118:11]
- assign q_io_in_bits_0_bits_vs_valid = io_in_bits_0_bits_vs_valid; // @[VLd.scala 118:11]
- assign q_io_in_bits_0_bits_sv_addr = io_in_bits_0_bits_sv_addr; // @[VLd.scala 118:11]
- assign q_io_in_bits_0_bits_sv_data = io_in_bits_0_bits_sv_data; // @[VLd.scala 118:11]
- assign q_io_in_bits_1_valid = io_in_bits_1_valid; // @[VLd.scala 118:11]
- assign q_io_in_bits_1_bits_op = io_in_bits_1_bits_op; // @[VLd.scala 118:11]
- assign q_io_in_bits_1_bits_f2 = io_in_bits_1_bits_f2; // @[VLd.scala 118:11]
- assign q_io_in_bits_1_bits_sz = io_in_bits_1_bits_sz; // @[VLd.scala 118:11]
- assign q_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VLd.scala 118:11]
- assign q_io_in_bits_1_bits_vd_valid = io_in_bits_1_bits_vd_valid; // @[VLd.scala 118:11]
- assign q_io_in_bits_1_bits_vd_addr = io_in_bits_1_bits_vd_addr; // @[VLd.scala 118:11]
- assign q_io_in_bits_1_bits_vs_valid = io_in_bits_1_bits_vs_valid; // @[VLd.scala 118:11]
- assign q_io_in_bits_1_bits_sv_addr = io_in_bits_1_bits_sv_addr; // @[VLd.scala 118:11]
- assign q_io_in_bits_1_bits_sv_data = io_in_bits_1_bits_sv_data; // @[VLd.scala 118:11]
- assign q_io_in_bits_2_valid = io_in_bits_2_valid; // @[VLd.scala 118:11]
- assign q_io_in_bits_2_bits_op = io_in_bits_2_bits_op; // @[VLd.scala 118:11]
- assign q_io_in_bits_2_bits_f2 = io_in_bits_2_bits_f2; // @[VLd.scala 118:11]
- assign q_io_in_bits_2_bits_sz = io_in_bits_2_bits_sz; // @[VLd.scala 118:11]
- assign q_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VLd.scala 118:11]
- assign q_io_in_bits_2_bits_vd_valid = io_in_bits_2_bits_vd_valid; // @[VLd.scala 118:11]
- assign q_io_in_bits_2_bits_vd_addr = io_in_bits_2_bits_vd_addr; // @[VLd.scala 118:11]
- assign q_io_in_bits_2_bits_vs_valid = io_in_bits_2_bits_vs_valid; // @[VLd.scala 118:11]
- assign q_io_in_bits_2_bits_sv_addr = io_in_bits_2_bits_sv_addr; // @[VLd.scala 118:11]
- assign q_io_in_bits_2_bits_sv_data = io_in_bits_2_bits_sv_data; // @[VLd.scala 118:11]
- assign q_io_in_bits_3_valid = io_in_bits_3_valid; // @[VLd.scala 118:11]
- assign q_io_in_bits_3_bits_op = io_in_bits_3_bits_op; // @[VLd.scala 118:11]
- assign q_io_in_bits_3_bits_f2 = io_in_bits_3_bits_f2; // @[VLd.scala 118:11]
- assign q_io_in_bits_3_bits_sz = io_in_bits_3_bits_sz; // @[VLd.scala 118:11]
- assign q_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VLd.scala 118:11]
- assign q_io_in_bits_3_bits_vd_valid = io_in_bits_3_bits_vd_valid; // @[VLd.scala 118:11]
- assign q_io_in_bits_3_bits_vd_addr = io_in_bits_3_bits_vd_addr; // @[VLd.scala 118:11]
- assign q_io_in_bits_3_bits_vs_valid = io_in_bits_3_bits_vs_valid; // @[VLd.scala 118:11]
- assign q_io_in_bits_3_bits_sv_addr = io_in_bits_3_bits_sv_addr; // @[VLd.scala 118:11]
- assign q_io_in_bits_3_bits_sv_data = io_in_bits_3_bits_sv_data; // @[VLd.scala 118:11]
- assign q_io_out_ready = io_axi_addr_ready; // @[VLd.scala 128:18]
+ assign q_io_in_valid = io_in_valid; // @[VLd.scala 119:11]
+ assign q_io_in_bits_0_valid = io_in_bits_0_valid; // @[VLd.scala 119:11]
+ assign q_io_in_bits_0_bits_op = io_in_bits_0_bits_op; // @[VLd.scala 119:11]
+ assign q_io_in_bits_0_bits_f2 = io_in_bits_0_bits_f2; // @[VLd.scala 119:11]
+ assign q_io_in_bits_0_bits_sz = io_in_bits_0_bits_sz; // @[VLd.scala 119:11]
+ assign q_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VLd.scala 119:11]
+ assign q_io_in_bits_0_bits_vd_valid = io_in_bits_0_bits_vd_valid; // @[VLd.scala 119:11]
+ assign q_io_in_bits_0_bits_vd_addr = io_in_bits_0_bits_vd_addr; // @[VLd.scala 119:11]
+ assign q_io_in_bits_0_bits_vs_valid = io_in_bits_0_bits_vs_valid; // @[VLd.scala 119:11]
+ assign q_io_in_bits_0_bits_sv_addr = io_in_bits_0_bits_sv_addr; // @[VLd.scala 119:11]
+ assign q_io_in_bits_0_bits_sv_data = io_in_bits_0_bits_sv_data; // @[VLd.scala 119:11]
+ assign q_io_in_bits_1_valid = io_in_bits_1_valid; // @[VLd.scala 119:11]
+ assign q_io_in_bits_1_bits_op = io_in_bits_1_bits_op; // @[VLd.scala 119:11]
+ assign q_io_in_bits_1_bits_f2 = io_in_bits_1_bits_f2; // @[VLd.scala 119:11]
+ assign q_io_in_bits_1_bits_sz = io_in_bits_1_bits_sz; // @[VLd.scala 119:11]
+ assign q_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VLd.scala 119:11]
+ assign q_io_in_bits_1_bits_vd_valid = io_in_bits_1_bits_vd_valid; // @[VLd.scala 119:11]
+ assign q_io_in_bits_1_bits_vd_addr = io_in_bits_1_bits_vd_addr; // @[VLd.scala 119:11]
+ assign q_io_in_bits_1_bits_vs_valid = io_in_bits_1_bits_vs_valid; // @[VLd.scala 119:11]
+ assign q_io_in_bits_1_bits_sv_addr = io_in_bits_1_bits_sv_addr; // @[VLd.scala 119:11]
+ assign q_io_in_bits_1_bits_sv_data = io_in_bits_1_bits_sv_data; // @[VLd.scala 119:11]
+ assign q_io_in_bits_2_valid = io_in_bits_2_valid; // @[VLd.scala 119:11]
+ assign q_io_in_bits_2_bits_op = io_in_bits_2_bits_op; // @[VLd.scala 119:11]
+ assign q_io_in_bits_2_bits_f2 = io_in_bits_2_bits_f2; // @[VLd.scala 119:11]
+ assign q_io_in_bits_2_bits_sz = io_in_bits_2_bits_sz; // @[VLd.scala 119:11]
+ assign q_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VLd.scala 119:11]
+ assign q_io_in_bits_2_bits_vd_valid = io_in_bits_2_bits_vd_valid; // @[VLd.scala 119:11]
+ assign q_io_in_bits_2_bits_vd_addr = io_in_bits_2_bits_vd_addr; // @[VLd.scala 119:11]
+ assign q_io_in_bits_2_bits_vs_valid = io_in_bits_2_bits_vs_valid; // @[VLd.scala 119:11]
+ assign q_io_in_bits_2_bits_sv_addr = io_in_bits_2_bits_sv_addr; // @[VLd.scala 119:11]
+ assign q_io_in_bits_2_bits_sv_data = io_in_bits_2_bits_sv_data; // @[VLd.scala 119:11]
+ assign q_io_in_bits_3_valid = io_in_bits_3_valid; // @[VLd.scala 119:11]
+ assign q_io_in_bits_3_bits_op = io_in_bits_3_bits_op; // @[VLd.scala 119:11]
+ assign q_io_in_bits_3_bits_f2 = io_in_bits_3_bits_f2; // @[VLd.scala 119:11]
+ assign q_io_in_bits_3_bits_sz = io_in_bits_3_bits_sz; // @[VLd.scala 119:11]
+ assign q_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VLd.scala 119:11]
+ assign q_io_in_bits_3_bits_vd_valid = io_in_bits_3_bits_vd_valid; // @[VLd.scala 119:11]
+ assign q_io_in_bits_3_bits_vd_addr = io_in_bits_3_bits_vd_addr; // @[VLd.scala 119:11]
+ assign q_io_in_bits_3_bits_vs_valid = io_in_bits_3_bits_vs_valid; // @[VLd.scala 119:11]
+ assign q_io_in_bits_3_bits_sv_addr = io_in_bits_3_bits_sv_addr; // @[VLd.scala 119:11]
+ assign q_io_in_bits_3_bits_sv_data = io_in_bits_3_bits_sv_data; // @[VLd.scala 119:11]
+ assign q_io_out_ready = io_axi_addr_ready; // @[VLd.scala 129:18]
always @(posedge clock) begin
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (~reset & ~(~(q_io_out_valid & ~q_io_out_bits_addr[31]))) begin
- $fatal; // @[VLd.scala 125:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~(q_io_out_valid & ~q_io_out_bits_addr[31]))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLd.scala:125 assert(!(q.io.out.valid && !q.io.out.bits.addr(31)))\n"); // @[VLd.scala 125:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_5 & ~(~(io_axi_addr_valid & io_axi_addr_bits_addr[31]))) begin
$fatal; // @[VLd.scala 126:9]
end
`ifdef STOP_COND
@@ -103297,9 +103087,32 @@
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
+ if (~reset & ~(~(q_io_out_valid & ~q_io_out_bits_addr[31]))) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at VLd.scala:126 assert(!(q.io.out.valid && !q.io.out.bits.addr(31)))\n"); // @[VLd.scala 126:9]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & ~(~(io_axi_addr_valid & io_axi_addr_bits_addr[31]))) begin
+ $fatal; // @[VLd.scala 127:9]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
if (_T_5 & ~(~(io_axi_addr_valid & io_axi_addr_bits_addr[31]))) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VLd.scala:126 assert(!(io.axi.addr.valid && io.axi.addr.bits.addr(31)))\n"); // @[VLd.scala 126:9]
+ "Assertion failed\n at VLd.scala:127 assert(!(io.axi.addr.valid && io.axi.addr.bits.addr(31)))\n"); // @[VLd.scala 127:9]
end
`ifdef PRINTF_COND
end
@@ -103310,7 +103123,7 @@
if (`STOP_COND) begin
`endif
if (_T_13 & _T_5 & ~(count <= 7'h40)) begin
- $fatal; // @[VLd.scala 149:11]
+ $fatal; // @[VLd.scala 150:11]
end
`ifdef STOP_COND
end
@@ -103321,7 +103134,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_13 & _T_5 & ~(count <= 7'h40)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:149 assert(count <= 64.U)\n"); // @[VLd.scala 149:11]
+ $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:150 assert(count <= 64.U)\n"); // @[VLd.scala 150:11]
end
`ifdef PRINTF_COND
end
@@ -103329,16 +103142,16 @@
`endif // SYNTHESIS
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VLd.scala 145:21]
- nempty <= 1'h0; // @[VLd.scala 148:12]
- end else if (inc | dec) begin // @[VLd.scala 140:23]
+ if (reset) begin // @[VLd.scala 146:21]
+ nempty <= 1'h0; // @[VLd.scala 149:12]
+ end else if (inc | dec) begin // @[VLd.scala 141:23]
nempty <= nxtcount != 7'h0;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VLd.scala 145:21]
- count <= 7'h0; // @[VLd.scala 147:11]
- end else if (inc | dec) begin // @[VLd.scala 141:22]
+ if (reset) begin // @[VLd.scala 146:21]
+ count <= 7'h0; // @[VLd.scala 148:11]
+ end else if (inc | dec) begin // @[VLd.scala 142:22]
count <= nxtcount;
end
end
@@ -107837,115 +107650,115 @@
reg [1:0] value_tin_quad; // @[VCmdq.scala 37:18]
reg value_m; // @[VCmdq.scala 37:18]
reg [4:0] step; // @[VCmdq.scala 42:21]
- wire _addrAlign_T = value_tin_op == 7'h4; // @[VSt.scala 109:31]
- wire [4:0] addrAlign = value_tin_op == 7'h4 ? {{2'd0}, value_tin_addr[2:0]} : value_tin_addr[4:0]; // @[VSt.scala 109:24]
- wire [4:0] offsAlign = _addrAlign_T ? {{2'd0}, value_tin_offset[2:0]} : value_tin_offset[4:0]; // @[VSt.scala 110:24]
- wire _T_2 = ~reset; // @[VSt.scala 111:11]
- wire _T_8 = ~valid; // @[VSt.scala 113:12]
- wire [7:0] fmaxvlb = _addrAlign_T ? 8'h8 : 8'h20; // @[VSt.scala 119:22]
- wire _outlast1_T = ~value_m; // @[VSt.scala 121:20]
- wire _last1_T_1 = step == 5'h3; // @[VSt.scala 125:28]
- wire last1 = _outlast1_T | step == 5'h3; // @[VSt.scala 125:20]
- wire last2 = value_m ? step == 5'hf : _last1_T_1; // @[VSt.scala 126:20]
- wire last = _addrAlign_T ? last2 : last1; // @[VSt.scala 127:19]
- wire [5:0] _out_vs_addr_T_4 = value_tin_vs_addr + 6'h1; // @[VSt.scala 131:74]
- wire [5:0] tin_vs_addr = _addrAlign_T & step[1:0] != 2'h3 ? value_tin_vs_addr : _out_vs_addr_T_4; // @[VSt.scala 131:23]
- wire [31:0] tin_addr = value_tin_addr + value_tin_offset; // @[VSt.scala 133:27]
- wire [7:0] _out_remain_T_2 = value_tin_remain - fmaxvlb; // @[VSt.scala 134:60]
- wire [7:0] tin_remain = value_tin_remain <= fmaxvlb ? 8'h0 : _out_remain_T_2; // @[VSt.scala 134:22]
- wire [4:0] _out_quad_T_2 = step + 5'h1; // @[VSt.scala 138:46]
- wire [4:0] _out_quad_T_3 = _addrAlign_T ? _out_quad_T_2 : 5'h0; // @[VSt.scala 138:20]
- wire f_io_in_bits_0_bits_tin_stride = io_in_bits_0_bits_f2[1]; // @[VSt.scala 77:23]
- wire f_io_in_bits_0_bits_tin_length = io_in_bits_0_bits_f2[0]; // @[VSt.scala 78:23]
+ wire _addrAlign_T = value_tin_op == 7'h4; // @[VSt.scala 110:31]
+ wire [4:0] addrAlign = value_tin_op == 7'h4 ? {{2'd0}, value_tin_addr[2:0]} : value_tin_addr[4:0]; // @[VSt.scala 110:24]
+ wire [4:0] offsAlign = _addrAlign_T ? {{2'd0}, value_tin_offset[2:0]} : value_tin_offset[4:0]; // @[VSt.scala 111:24]
+ wire _T_2 = ~reset; // @[VSt.scala 112:11]
+ wire _T_8 = ~valid; // @[VSt.scala 114:12]
+ wire [7:0] fmaxvlb = _addrAlign_T ? 8'h8 : 8'h20; // @[VSt.scala 120:22]
+ wire _outlast1_T = ~value_m; // @[VSt.scala 122:20]
+ wire _last1_T_1 = step == 5'h3; // @[VSt.scala 126:28]
+ wire last1 = _outlast1_T | step == 5'h3; // @[VSt.scala 126:20]
+ wire last2 = value_m ? step == 5'hf : _last1_T_1; // @[VSt.scala 127:20]
+ wire last = _addrAlign_T ? last2 : last1; // @[VSt.scala 128:19]
+ wire [5:0] _out_vs_addr_T_4 = value_tin_vs_addr + 6'h1; // @[VSt.scala 132:74]
+ wire [5:0] tin_vs_addr = _addrAlign_T & step[1:0] != 2'h3 ? value_tin_vs_addr : _out_vs_addr_T_4; // @[VSt.scala 132:23]
+ wire [31:0] tin_addr = value_tin_addr + value_tin_offset; // @[VSt.scala 134:27]
+ wire [7:0] _out_remain_T_2 = value_tin_remain - fmaxvlb; // @[VSt.scala 135:60]
+ wire [7:0] tin_remain = value_tin_remain <= fmaxvlb ? 8'h0 : _out_remain_T_2; // @[VSt.scala 135:22]
+ wire [4:0] _out_quad_T_2 = step + 5'h1; // @[VSt.scala 139:46]
+ wire [4:0] _out_quad_T_3 = _addrAlign_T ? _out_quad_T_2 : 5'h0; // @[VSt.scala 139:20]
+ wire f_io_in_bits_0_bits_tin_stride = io_in_bits_0_bits_f2[1]; // @[VSt.scala 78:23]
+ wire f_io_in_bits_0_bits_tin_length = io_in_bits_0_bits_f2[0]; // @[VSt.scala 79:23]
wire [1:0] _f_io_in_bits_0_bits_tin_T_3 = io_in_bits_0_bits_sz[1] + io_in_bits_0_bits_sz[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_55 = {{1'd0}, io_in_bits_0_bits_sz[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _f_io_in_bits_0_bits_tin_T_5 = _GEN_55 + _f_io_in_bits_0_bits_tin_T_3; // @[Bitwise.scala 48:55]
- wire _f_io_in_bits_0_bits_tin_T_12 = ~io_in_bits_0_bits_vs_valid; // @[VSt.scala 80:36]
- wire _f_io_in_bits_0_bits_tin_T_18 = io_in_bits_0_bits_op == 7'h4; // @[VSt.scala 81:20]
- wire [7:0] f_io_in_bits_0_bits_tin_limit = io_in_bits_0_bits_m ? 8'h80 : 8'h20; // @[VSt.scala 83:20]
+ wire _f_io_in_bits_0_bits_tin_T_12 = ~io_in_bits_0_bits_vs_valid; // @[VSt.scala 81:36]
+ wire _f_io_in_bits_0_bits_tin_T_18 = io_in_bits_0_bits_op == 7'h4; // @[VSt.scala 82:20]
+ wire [7:0] f_io_in_bits_0_bits_tin_limit = io_in_bits_0_bits_m ? 8'h80 : 8'h20; // @[VSt.scala 84:20]
wire [31:0] _f_io_in_bits_0_bits_tin_data_T_1 = io_in_bits_0_bits_sz[0] ? io_in_bits_0_bits_sv_data : 32'h0; // @[Library.scala 8:8]
wire [32:0] _f_io_in_bits_0_bits_tin_data_T_3 = {io_in_bits_0_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
wire [32:0] _f_io_in_bits_0_bits_tin_data_T_4 = io_in_bits_0_bits_sz[1] ? _f_io_in_bits_0_bits_tin_data_T_3 : 33'h0; // @[Library.scala 8:8]
- wire [32:0] _GEN_56 = {{1'd0}, _f_io_in_bits_0_bits_tin_data_T_1}; // @[VSt.scala 85:44]
- wire [32:0] _f_io_in_bits_0_bits_tin_data_T_5 = _GEN_56 | _f_io_in_bits_0_bits_tin_data_T_4; // @[VSt.scala 85:44]
+ wire [32:0] _GEN_56 = {{1'd0}, _f_io_in_bits_0_bits_tin_data_T_1}; // @[VSt.scala 86:44]
+ wire [32:0] _f_io_in_bits_0_bits_tin_data_T_5 = _GEN_56 | _f_io_in_bits_0_bits_tin_data_T_4; // @[VSt.scala 86:44]
wire [33:0] _f_io_in_bits_0_bits_tin_data_T_7 = {io_in_bits_0_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
wire [33:0] _f_io_in_bits_0_bits_tin_data_T_8 = io_in_bits_0_bits_sz[2] ? _f_io_in_bits_0_bits_tin_data_T_7 : 34'h0; // @[Library.scala 8:8]
- wire [33:0] _GEN_57 = {{1'd0}, _f_io_in_bits_0_bits_tin_data_T_5}; // @[VSt.scala 86:59]
- wire [33:0] f_io_in_bits_0_bits_tin_data = _GEN_57 | _f_io_in_bits_0_bits_tin_data_T_8; // @[VSt.scala 86:59]
- wire [33:0] _GEN_58 = {{26'd0}, f_io_in_bits_0_bits_tin_limit}; // @[VSt.scala 90:28]
+ wire [33:0] _GEN_57 = {{1'd0}, _f_io_in_bits_0_bits_tin_data_T_5}; // @[VSt.scala 87:59]
+ wire [33:0] f_io_in_bits_0_bits_tin_data = _GEN_57 | _f_io_in_bits_0_bits_tin_data_T_8; // @[VSt.scala 87:59]
+ wire [33:0] _GEN_58 = {{26'd0}, f_io_in_bits_0_bits_tin_limit}; // @[VSt.scala 91:28]
wire [33:0] _f_io_in_bits_0_bits_tin_remain1_T_1 = f_io_in_bits_0_bits_tin_data > _GEN_58 ? {{26'd0},
- f_io_in_bits_0_bits_tin_limit} : f_io_in_bits_0_bits_tin_data; // @[VSt.scala 90:22]
- wire [7:0] f_io_in_bits_0_bits_tin_remain1 = _f_io_in_bits_0_bits_tin_remain1_T_1[7:0]; // @[VSt.scala 90:49]
- wire [7:0] _f_io_in_bits_0_bits_tin_out_offset_T_3 = _f_io_in_bits_0_bits_tin_T_18 ? 8'h8 : 8'h20; // @[VSt.scala 98:46]
- wire f_io_in_bits_1_bits_tin_stride = io_in_bits_1_bits_f2[1]; // @[VSt.scala 77:23]
- wire f_io_in_bits_1_bits_tin_length = io_in_bits_1_bits_f2[0]; // @[VSt.scala 78:23]
+ f_io_in_bits_0_bits_tin_limit} : f_io_in_bits_0_bits_tin_data; // @[VSt.scala 91:22]
+ wire [7:0] f_io_in_bits_0_bits_tin_remain1 = _f_io_in_bits_0_bits_tin_remain1_T_1[7:0]; // @[VSt.scala 91:49]
+ wire [7:0] _f_io_in_bits_0_bits_tin_out_offset_T_3 = _f_io_in_bits_0_bits_tin_T_18 ? 8'h8 : 8'h20; // @[VSt.scala 99:46]
+ wire f_io_in_bits_1_bits_tin_stride = io_in_bits_1_bits_f2[1]; // @[VSt.scala 78:23]
+ wire f_io_in_bits_1_bits_tin_length = io_in_bits_1_bits_f2[0]; // @[VSt.scala 79:23]
wire [1:0] _f_io_in_bits_1_bits_tin_T_3 = io_in_bits_1_bits_sz[1] + io_in_bits_1_bits_sz[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_59 = {{1'd0}, io_in_bits_1_bits_sz[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _f_io_in_bits_1_bits_tin_T_5 = _GEN_59 + _f_io_in_bits_1_bits_tin_T_3; // @[Bitwise.scala 48:55]
- wire _f_io_in_bits_1_bits_tin_T_12 = ~io_in_bits_1_bits_vs_valid; // @[VSt.scala 80:36]
- wire _f_io_in_bits_1_bits_tin_T_18 = io_in_bits_1_bits_op == 7'h4; // @[VSt.scala 81:20]
- wire [7:0] f_io_in_bits_1_bits_tin_limit = io_in_bits_1_bits_m ? 8'h80 : 8'h20; // @[VSt.scala 83:20]
+ wire _f_io_in_bits_1_bits_tin_T_12 = ~io_in_bits_1_bits_vs_valid; // @[VSt.scala 81:36]
+ wire _f_io_in_bits_1_bits_tin_T_18 = io_in_bits_1_bits_op == 7'h4; // @[VSt.scala 82:20]
+ wire [7:0] f_io_in_bits_1_bits_tin_limit = io_in_bits_1_bits_m ? 8'h80 : 8'h20; // @[VSt.scala 84:20]
wire [31:0] _f_io_in_bits_1_bits_tin_data_T_1 = io_in_bits_1_bits_sz[0] ? io_in_bits_1_bits_sv_data : 32'h0; // @[Library.scala 8:8]
wire [32:0] _f_io_in_bits_1_bits_tin_data_T_3 = {io_in_bits_1_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
wire [32:0] _f_io_in_bits_1_bits_tin_data_T_4 = io_in_bits_1_bits_sz[1] ? _f_io_in_bits_1_bits_tin_data_T_3 : 33'h0; // @[Library.scala 8:8]
- wire [32:0] _GEN_60 = {{1'd0}, _f_io_in_bits_1_bits_tin_data_T_1}; // @[VSt.scala 85:44]
- wire [32:0] _f_io_in_bits_1_bits_tin_data_T_5 = _GEN_60 | _f_io_in_bits_1_bits_tin_data_T_4; // @[VSt.scala 85:44]
+ wire [32:0] _GEN_60 = {{1'd0}, _f_io_in_bits_1_bits_tin_data_T_1}; // @[VSt.scala 86:44]
+ wire [32:0] _f_io_in_bits_1_bits_tin_data_T_5 = _GEN_60 | _f_io_in_bits_1_bits_tin_data_T_4; // @[VSt.scala 86:44]
wire [33:0] _f_io_in_bits_1_bits_tin_data_T_7 = {io_in_bits_1_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
wire [33:0] _f_io_in_bits_1_bits_tin_data_T_8 = io_in_bits_1_bits_sz[2] ? _f_io_in_bits_1_bits_tin_data_T_7 : 34'h0; // @[Library.scala 8:8]
- wire [33:0] _GEN_61 = {{1'd0}, _f_io_in_bits_1_bits_tin_data_T_5}; // @[VSt.scala 86:59]
- wire [33:0] f_io_in_bits_1_bits_tin_data = _GEN_61 | _f_io_in_bits_1_bits_tin_data_T_8; // @[VSt.scala 86:59]
- wire [33:0] _GEN_62 = {{26'd0}, f_io_in_bits_1_bits_tin_limit}; // @[VSt.scala 90:28]
+ wire [33:0] _GEN_61 = {{1'd0}, _f_io_in_bits_1_bits_tin_data_T_5}; // @[VSt.scala 87:59]
+ wire [33:0] f_io_in_bits_1_bits_tin_data = _GEN_61 | _f_io_in_bits_1_bits_tin_data_T_8; // @[VSt.scala 87:59]
+ wire [33:0] _GEN_62 = {{26'd0}, f_io_in_bits_1_bits_tin_limit}; // @[VSt.scala 91:28]
wire [33:0] _f_io_in_bits_1_bits_tin_remain1_T_1 = f_io_in_bits_1_bits_tin_data > _GEN_62 ? {{26'd0},
- f_io_in_bits_1_bits_tin_limit} : f_io_in_bits_1_bits_tin_data; // @[VSt.scala 90:22]
- wire [7:0] f_io_in_bits_1_bits_tin_remain1 = _f_io_in_bits_1_bits_tin_remain1_T_1[7:0]; // @[VSt.scala 90:49]
- wire [7:0] _f_io_in_bits_1_bits_tin_out_offset_T_3 = _f_io_in_bits_1_bits_tin_T_18 ? 8'h8 : 8'h20; // @[VSt.scala 98:46]
- wire f_io_in_bits_2_bits_tin_stride = io_in_bits_2_bits_f2[1]; // @[VSt.scala 77:23]
- wire f_io_in_bits_2_bits_tin_length = io_in_bits_2_bits_f2[0]; // @[VSt.scala 78:23]
+ f_io_in_bits_1_bits_tin_limit} : f_io_in_bits_1_bits_tin_data; // @[VSt.scala 91:22]
+ wire [7:0] f_io_in_bits_1_bits_tin_remain1 = _f_io_in_bits_1_bits_tin_remain1_T_1[7:0]; // @[VSt.scala 91:49]
+ wire [7:0] _f_io_in_bits_1_bits_tin_out_offset_T_3 = _f_io_in_bits_1_bits_tin_T_18 ? 8'h8 : 8'h20; // @[VSt.scala 99:46]
+ wire f_io_in_bits_2_bits_tin_stride = io_in_bits_2_bits_f2[1]; // @[VSt.scala 78:23]
+ wire f_io_in_bits_2_bits_tin_length = io_in_bits_2_bits_f2[0]; // @[VSt.scala 79:23]
wire [1:0] _f_io_in_bits_2_bits_tin_T_3 = io_in_bits_2_bits_sz[1] + io_in_bits_2_bits_sz[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_63 = {{1'd0}, io_in_bits_2_bits_sz[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _f_io_in_bits_2_bits_tin_T_5 = _GEN_63 + _f_io_in_bits_2_bits_tin_T_3; // @[Bitwise.scala 48:55]
- wire _f_io_in_bits_2_bits_tin_T_12 = ~io_in_bits_2_bits_vs_valid; // @[VSt.scala 80:36]
- wire _f_io_in_bits_2_bits_tin_T_18 = io_in_bits_2_bits_op == 7'h4; // @[VSt.scala 81:20]
- wire [7:0] f_io_in_bits_2_bits_tin_limit = io_in_bits_2_bits_m ? 8'h80 : 8'h20; // @[VSt.scala 83:20]
+ wire _f_io_in_bits_2_bits_tin_T_12 = ~io_in_bits_2_bits_vs_valid; // @[VSt.scala 81:36]
+ wire _f_io_in_bits_2_bits_tin_T_18 = io_in_bits_2_bits_op == 7'h4; // @[VSt.scala 82:20]
+ wire [7:0] f_io_in_bits_2_bits_tin_limit = io_in_bits_2_bits_m ? 8'h80 : 8'h20; // @[VSt.scala 84:20]
wire [31:0] _f_io_in_bits_2_bits_tin_data_T_1 = io_in_bits_2_bits_sz[0] ? io_in_bits_2_bits_sv_data : 32'h0; // @[Library.scala 8:8]
wire [32:0] _f_io_in_bits_2_bits_tin_data_T_3 = {io_in_bits_2_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
wire [32:0] _f_io_in_bits_2_bits_tin_data_T_4 = io_in_bits_2_bits_sz[1] ? _f_io_in_bits_2_bits_tin_data_T_3 : 33'h0; // @[Library.scala 8:8]
- wire [32:0] _GEN_64 = {{1'd0}, _f_io_in_bits_2_bits_tin_data_T_1}; // @[VSt.scala 85:44]
- wire [32:0] _f_io_in_bits_2_bits_tin_data_T_5 = _GEN_64 | _f_io_in_bits_2_bits_tin_data_T_4; // @[VSt.scala 85:44]
+ wire [32:0] _GEN_64 = {{1'd0}, _f_io_in_bits_2_bits_tin_data_T_1}; // @[VSt.scala 86:44]
+ wire [32:0] _f_io_in_bits_2_bits_tin_data_T_5 = _GEN_64 | _f_io_in_bits_2_bits_tin_data_T_4; // @[VSt.scala 86:44]
wire [33:0] _f_io_in_bits_2_bits_tin_data_T_7 = {io_in_bits_2_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
wire [33:0] _f_io_in_bits_2_bits_tin_data_T_8 = io_in_bits_2_bits_sz[2] ? _f_io_in_bits_2_bits_tin_data_T_7 : 34'h0; // @[Library.scala 8:8]
- wire [33:0] _GEN_65 = {{1'd0}, _f_io_in_bits_2_bits_tin_data_T_5}; // @[VSt.scala 86:59]
- wire [33:0] f_io_in_bits_2_bits_tin_data = _GEN_65 | _f_io_in_bits_2_bits_tin_data_T_8; // @[VSt.scala 86:59]
- wire [33:0] _GEN_66 = {{26'd0}, f_io_in_bits_2_bits_tin_limit}; // @[VSt.scala 90:28]
+ wire [33:0] _GEN_65 = {{1'd0}, _f_io_in_bits_2_bits_tin_data_T_5}; // @[VSt.scala 87:59]
+ wire [33:0] f_io_in_bits_2_bits_tin_data = _GEN_65 | _f_io_in_bits_2_bits_tin_data_T_8; // @[VSt.scala 87:59]
+ wire [33:0] _GEN_66 = {{26'd0}, f_io_in_bits_2_bits_tin_limit}; // @[VSt.scala 91:28]
wire [33:0] _f_io_in_bits_2_bits_tin_remain1_T_1 = f_io_in_bits_2_bits_tin_data > _GEN_66 ? {{26'd0},
- f_io_in_bits_2_bits_tin_limit} : f_io_in_bits_2_bits_tin_data; // @[VSt.scala 90:22]
- wire [7:0] f_io_in_bits_2_bits_tin_remain1 = _f_io_in_bits_2_bits_tin_remain1_T_1[7:0]; // @[VSt.scala 90:49]
- wire [7:0] _f_io_in_bits_2_bits_tin_out_offset_T_3 = _f_io_in_bits_2_bits_tin_T_18 ? 8'h8 : 8'h20; // @[VSt.scala 98:46]
- wire f_io_in_bits_3_bits_tin_stride = io_in_bits_3_bits_f2[1]; // @[VSt.scala 77:23]
- wire f_io_in_bits_3_bits_tin_length = io_in_bits_3_bits_f2[0]; // @[VSt.scala 78:23]
+ f_io_in_bits_2_bits_tin_limit} : f_io_in_bits_2_bits_tin_data; // @[VSt.scala 91:22]
+ wire [7:0] f_io_in_bits_2_bits_tin_remain1 = _f_io_in_bits_2_bits_tin_remain1_T_1[7:0]; // @[VSt.scala 91:49]
+ wire [7:0] _f_io_in_bits_2_bits_tin_out_offset_T_3 = _f_io_in_bits_2_bits_tin_T_18 ? 8'h8 : 8'h20; // @[VSt.scala 99:46]
+ wire f_io_in_bits_3_bits_tin_stride = io_in_bits_3_bits_f2[1]; // @[VSt.scala 78:23]
+ wire f_io_in_bits_3_bits_tin_length = io_in_bits_3_bits_f2[0]; // @[VSt.scala 79:23]
wire [1:0] _f_io_in_bits_3_bits_tin_T_3 = io_in_bits_3_bits_sz[1] + io_in_bits_3_bits_sz[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_67 = {{1'd0}, io_in_bits_3_bits_sz[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _f_io_in_bits_3_bits_tin_T_5 = _GEN_67 + _f_io_in_bits_3_bits_tin_T_3; // @[Bitwise.scala 48:55]
- wire _f_io_in_bits_3_bits_tin_T_12 = ~io_in_bits_3_bits_vs_valid; // @[VSt.scala 80:36]
- wire _f_io_in_bits_3_bits_tin_T_18 = io_in_bits_3_bits_op == 7'h4; // @[VSt.scala 81:20]
- wire [7:0] f_io_in_bits_3_bits_tin_limit = io_in_bits_3_bits_m ? 8'h80 : 8'h20; // @[VSt.scala 83:20]
+ wire _f_io_in_bits_3_bits_tin_T_12 = ~io_in_bits_3_bits_vs_valid; // @[VSt.scala 81:36]
+ wire _f_io_in_bits_3_bits_tin_T_18 = io_in_bits_3_bits_op == 7'h4; // @[VSt.scala 82:20]
+ wire [7:0] f_io_in_bits_3_bits_tin_limit = io_in_bits_3_bits_m ? 8'h80 : 8'h20; // @[VSt.scala 84:20]
wire [31:0] _f_io_in_bits_3_bits_tin_data_T_1 = io_in_bits_3_bits_sz[0] ? io_in_bits_3_bits_sv_data : 32'h0; // @[Library.scala 8:8]
wire [32:0] _f_io_in_bits_3_bits_tin_data_T_3 = {io_in_bits_3_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
wire [32:0] _f_io_in_bits_3_bits_tin_data_T_4 = io_in_bits_3_bits_sz[1] ? _f_io_in_bits_3_bits_tin_data_T_3 : 33'h0; // @[Library.scala 8:8]
- wire [32:0] _GEN_68 = {{1'd0}, _f_io_in_bits_3_bits_tin_data_T_1}; // @[VSt.scala 85:44]
- wire [32:0] _f_io_in_bits_3_bits_tin_data_T_5 = _GEN_68 | _f_io_in_bits_3_bits_tin_data_T_4; // @[VSt.scala 85:44]
+ wire [32:0] _GEN_68 = {{1'd0}, _f_io_in_bits_3_bits_tin_data_T_1}; // @[VSt.scala 86:44]
+ wire [32:0] _f_io_in_bits_3_bits_tin_data_T_5 = _GEN_68 | _f_io_in_bits_3_bits_tin_data_T_4; // @[VSt.scala 86:44]
wire [33:0] _f_io_in_bits_3_bits_tin_data_T_7 = {io_in_bits_3_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
wire [33:0] _f_io_in_bits_3_bits_tin_data_T_8 = io_in_bits_3_bits_sz[2] ? _f_io_in_bits_3_bits_tin_data_T_7 : 34'h0; // @[Library.scala 8:8]
- wire [33:0] _GEN_69 = {{1'd0}, _f_io_in_bits_3_bits_tin_data_T_5}; // @[VSt.scala 86:59]
- wire [33:0] f_io_in_bits_3_bits_tin_data = _GEN_69 | _f_io_in_bits_3_bits_tin_data_T_8; // @[VSt.scala 86:59]
- wire [33:0] _GEN_70 = {{26'd0}, f_io_in_bits_3_bits_tin_limit}; // @[VSt.scala 90:28]
+ wire [33:0] _GEN_69 = {{1'd0}, _f_io_in_bits_3_bits_tin_data_T_5}; // @[VSt.scala 87:59]
+ wire [33:0] f_io_in_bits_3_bits_tin_data = _GEN_69 | _f_io_in_bits_3_bits_tin_data_T_8; // @[VSt.scala 87:59]
+ wire [33:0] _GEN_70 = {{26'd0}, f_io_in_bits_3_bits_tin_limit}; // @[VSt.scala 91:28]
wire [33:0] _f_io_in_bits_3_bits_tin_remain1_T_1 = f_io_in_bits_3_bits_tin_data > _GEN_70 ? {{26'd0},
- f_io_in_bits_3_bits_tin_limit} : f_io_in_bits_3_bits_tin_data; // @[VSt.scala 90:22]
- wire [7:0] f_io_in_bits_3_bits_tin_remain1 = _f_io_in_bits_3_bits_tin_remain1_T_1[7:0]; // @[VSt.scala 90:49]
- wire [7:0] _f_io_in_bits_3_bits_tin_out_offset_T_3 = _f_io_in_bits_3_bits_tin_T_18 ? 8'h8 : 8'h20; // @[VSt.scala 98:46]
+ f_io_in_bits_3_bits_tin_limit} : f_io_in_bits_3_bits_tin_data; // @[VSt.scala 91:22]
+ wire [7:0] f_io_in_bits_3_bits_tin_remain1 = _f_io_in_bits_3_bits_tin_remain1_T_1[7:0]; // @[VSt.scala 91:49]
+ wire [7:0] _f_io_in_bits_3_bits_tin_out_offset_T_3 = _f_io_in_bits_3_bits_tin_T_18 ? 8'h8 : 8'h20; // @[VSt.scala 99:46]
wire _T_17 = io_out_valid & io_out_ready; // @[VCmdq.scala 65:29]
wire _T_18 = ~last; // @[VCmdq.scala 66:11]
- wire [1:0] tin_quad = _out_quad_T_3[1:0]; // @[VSt.scala 115:19 138:14]
+ wire [1:0] tin_quad = _out_quad_T_3[1:0]; // @[VSt.scala 116:19 139:14]
wire _GEN_5 = ~last & value_tin_vs_valid; // @[VCmdq.scala 66:18 68:17 74:17]
wire _GEN_12 = ~last & value_m; // @[VCmdq.scala 66:18 69:15 75:15]
wire _GEN_14 = io_out_valid & io_out_ready ? _T_18 : valid; // @[VCmdq.scala 35:22 65:46]
@@ -108819,7 +108632,7 @@
wire [63:0] active_active_11 = f_io_entry_7_valid ? active_active_active_11 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_18 = _active_T_17 | active_active_11; // @[VCmdq.scala 91:24]
wire [5:0] _active_active0_T = {{1'd0}, step}; // @[VCmdq.scala 94:48]
- wire [2:0] active_active0_stepq = _addrAlign_T ? _active_active0_T[4:2] : _active_active0_T[2:0]; // @[VSt.scala 146:20]
+ wire [2:0] active_active0_stepq = _addrAlign_T ? _active_active0_T[4:2] : _active_active0_T[2:0]; // @[VSt.scala 147:20]
wire [3:0] active_active0_active_oh_shiftAmount = value_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active0_active_oh = 16'h1 << active_active0_active_oh_shiftAmount; // @[OneHot.scala 64:12]
wire [15:0] active_active0_active_oh0_lo_lo = {3'h0,active_active0_active_oh[3],3'h0,active_active0_active_oh[2],3'h0,
@@ -108894,7 +108707,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active0_active_active = _active_active0_active_active_T_22 | _active_active0_active_active_T_29; // @[VCommon.scala 93:68]
wire [63:0] active_active0 = value_tin_vs_valid ? active_active0_active_active : 64'h0; // @[Library.scala 8:8]
- wire [2:0] active_active1_stepq = _addrAlign_T ? _out_quad_T_2[4:2] : _out_quad_T_2[2:0]; // @[VSt.scala 146:20]
+ wire [2:0] active_active1_stepq = _addrAlign_T ? _out_quad_T_2[4:2] : _out_quad_T_2[2:0]; // @[VSt.scala 147:20]
wire _active_active1_active_active_T_5 = _outlast1_T & active_active0_active_idx == 2'h0 | value_m &
active_active1_stepq <= 3'h0; // @[VCommon.scala 91:42]
wire [63:0] _active_active1_active_active_T_6 = _active_active1_active_active_T_5 ? active_active0_active_oh0 : 64'h0; // @[Library.scala 18:8]
@@ -109023,44 +108836,44 @@
assign f_reset = reset;
assign f_io_in_valid = io_in_valid; // @[VCmdq.scala 48:17]
assign f_io_in_bits_0_valid = io_in_bits_0_valid; // @[VCmdq.scala 52:27]
- assign f_io_in_bits_0_bits_tin_op = io_in_bits_0_bits_op; // @[VSt.scala 76:19 94:12]
- assign f_io_in_bits_0_bits_tin_addr = io_in_bits_0_bits_sv_addr; // @[VSt.scala 76:19 97:14]
+ assign f_io_in_bits_0_bits_tin_op = io_in_bits_0_bits_op; // @[VSt.scala 77:19 95:12]
+ assign f_io_in_bits_0_bits_tin_addr = io_in_bits_0_bits_sv_addr; // @[VSt.scala 77:19 98:14]
assign f_io_in_bits_0_bits_tin_offset = f_io_in_bits_0_bits_tin_stride ? f_io_in_bits_0_bits_tin_data[31:0] : {{24
- 'd0}, _f_io_in_bits_0_bits_tin_out_offset_T_3}; // @[VSt.scala 98:22]
- assign f_io_in_bits_0_bits_tin_remain = f_io_in_bits_0_bits_tin_length ? f_io_in_bits_0_bits_tin_remain1 : 8'h80; // @[VSt.scala 99:22]
- assign f_io_in_bits_0_bits_tin_vs_valid = io_in_bits_0_bits_vs_valid; // @[VSt.scala 100:12 76:19]
- assign f_io_in_bits_0_bits_tin_vs_addr = io_in_bits_0_bits_vs_addr; // @[VSt.scala 100:12 76:19]
- assign f_io_in_bits_0_bits_tin_vs_tag = io_in_bits_0_bits_vs_tag; // @[VSt.scala 100:12 76:19]
+ 'd0}, _f_io_in_bits_0_bits_tin_out_offset_T_3}; // @[VSt.scala 99:22]
+ assign f_io_in_bits_0_bits_tin_remain = f_io_in_bits_0_bits_tin_length ? f_io_in_bits_0_bits_tin_remain1 : 8'h80; // @[VSt.scala 100:22]
+ assign f_io_in_bits_0_bits_tin_vs_valid = io_in_bits_0_bits_vs_valid; // @[VSt.scala 101:12 77:19]
+ assign f_io_in_bits_0_bits_tin_vs_addr = io_in_bits_0_bits_vs_addr; // @[VSt.scala 101:12 77:19]
+ assign f_io_in_bits_0_bits_tin_vs_tag = io_in_bits_0_bits_vs_tag; // @[VSt.scala 101:12 77:19]
assign f_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VCmdq.scala 54:28]
assign f_io_in_bits_1_valid = io_in_bits_1_valid; // @[VCmdq.scala 52:27]
- assign f_io_in_bits_1_bits_tin_op = io_in_bits_1_bits_op; // @[VSt.scala 76:19 94:12]
- assign f_io_in_bits_1_bits_tin_addr = io_in_bits_1_bits_sv_addr; // @[VSt.scala 76:19 97:14]
+ assign f_io_in_bits_1_bits_tin_op = io_in_bits_1_bits_op; // @[VSt.scala 77:19 95:12]
+ assign f_io_in_bits_1_bits_tin_addr = io_in_bits_1_bits_sv_addr; // @[VSt.scala 77:19 98:14]
assign f_io_in_bits_1_bits_tin_offset = f_io_in_bits_1_bits_tin_stride ? f_io_in_bits_1_bits_tin_data[31:0] : {{24
- 'd0}, _f_io_in_bits_1_bits_tin_out_offset_T_3}; // @[VSt.scala 98:22]
- assign f_io_in_bits_1_bits_tin_remain = f_io_in_bits_1_bits_tin_length ? f_io_in_bits_1_bits_tin_remain1 : 8'h80; // @[VSt.scala 99:22]
- assign f_io_in_bits_1_bits_tin_vs_valid = io_in_bits_1_bits_vs_valid; // @[VSt.scala 100:12 76:19]
- assign f_io_in_bits_1_bits_tin_vs_addr = io_in_bits_1_bits_vs_addr; // @[VSt.scala 100:12 76:19]
- assign f_io_in_bits_1_bits_tin_vs_tag = io_in_bits_1_bits_vs_tag; // @[VSt.scala 100:12 76:19]
+ 'd0}, _f_io_in_bits_1_bits_tin_out_offset_T_3}; // @[VSt.scala 99:22]
+ assign f_io_in_bits_1_bits_tin_remain = f_io_in_bits_1_bits_tin_length ? f_io_in_bits_1_bits_tin_remain1 : 8'h80; // @[VSt.scala 100:22]
+ assign f_io_in_bits_1_bits_tin_vs_valid = io_in_bits_1_bits_vs_valid; // @[VSt.scala 101:12 77:19]
+ assign f_io_in_bits_1_bits_tin_vs_addr = io_in_bits_1_bits_vs_addr; // @[VSt.scala 101:12 77:19]
+ assign f_io_in_bits_1_bits_tin_vs_tag = io_in_bits_1_bits_vs_tag; // @[VSt.scala 101:12 77:19]
assign f_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VCmdq.scala 54:28]
assign f_io_in_bits_2_valid = io_in_bits_2_valid; // @[VCmdq.scala 52:27]
- assign f_io_in_bits_2_bits_tin_op = io_in_bits_2_bits_op; // @[VSt.scala 76:19 94:12]
- assign f_io_in_bits_2_bits_tin_addr = io_in_bits_2_bits_sv_addr; // @[VSt.scala 76:19 97:14]
+ assign f_io_in_bits_2_bits_tin_op = io_in_bits_2_bits_op; // @[VSt.scala 77:19 95:12]
+ assign f_io_in_bits_2_bits_tin_addr = io_in_bits_2_bits_sv_addr; // @[VSt.scala 77:19 98:14]
assign f_io_in_bits_2_bits_tin_offset = f_io_in_bits_2_bits_tin_stride ? f_io_in_bits_2_bits_tin_data[31:0] : {{24
- 'd0}, _f_io_in_bits_2_bits_tin_out_offset_T_3}; // @[VSt.scala 98:22]
- assign f_io_in_bits_2_bits_tin_remain = f_io_in_bits_2_bits_tin_length ? f_io_in_bits_2_bits_tin_remain1 : 8'h80; // @[VSt.scala 99:22]
- assign f_io_in_bits_2_bits_tin_vs_valid = io_in_bits_2_bits_vs_valid; // @[VSt.scala 100:12 76:19]
- assign f_io_in_bits_2_bits_tin_vs_addr = io_in_bits_2_bits_vs_addr; // @[VSt.scala 100:12 76:19]
- assign f_io_in_bits_2_bits_tin_vs_tag = io_in_bits_2_bits_vs_tag; // @[VSt.scala 100:12 76:19]
+ 'd0}, _f_io_in_bits_2_bits_tin_out_offset_T_3}; // @[VSt.scala 99:22]
+ assign f_io_in_bits_2_bits_tin_remain = f_io_in_bits_2_bits_tin_length ? f_io_in_bits_2_bits_tin_remain1 : 8'h80; // @[VSt.scala 100:22]
+ assign f_io_in_bits_2_bits_tin_vs_valid = io_in_bits_2_bits_vs_valid; // @[VSt.scala 101:12 77:19]
+ assign f_io_in_bits_2_bits_tin_vs_addr = io_in_bits_2_bits_vs_addr; // @[VSt.scala 101:12 77:19]
+ assign f_io_in_bits_2_bits_tin_vs_tag = io_in_bits_2_bits_vs_tag; // @[VSt.scala 101:12 77:19]
assign f_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VCmdq.scala 54:28]
assign f_io_in_bits_3_valid = io_in_bits_3_valid; // @[VCmdq.scala 52:27]
- assign f_io_in_bits_3_bits_tin_op = io_in_bits_3_bits_op; // @[VSt.scala 76:19 94:12]
- assign f_io_in_bits_3_bits_tin_addr = io_in_bits_3_bits_sv_addr; // @[VSt.scala 76:19 97:14]
+ assign f_io_in_bits_3_bits_tin_op = io_in_bits_3_bits_op; // @[VSt.scala 77:19 95:12]
+ assign f_io_in_bits_3_bits_tin_addr = io_in_bits_3_bits_sv_addr; // @[VSt.scala 77:19 98:14]
assign f_io_in_bits_3_bits_tin_offset = f_io_in_bits_3_bits_tin_stride ? f_io_in_bits_3_bits_tin_data[31:0] : {{24
- 'd0}, _f_io_in_bits_3_bits_tin_out_offset_T_3}; // @[VSt.scala 98:22]
- assign f_io_in_bits_3_bits_tin_remain = f_io_in_bits_3_bits_tin_length ? f_io_in_bits_3_bits_tin_remain1 : 8'h80; // @[VSt.scala 99:22]
- assign f_io_in_bits_3_bits_tin_vs_valid = io_in_bits_3_bits_vs_valid; // @[VSt.scala 100:12 76:19]
- assign f_io_in_bits_3_bits_tin_vs_addr = io_in_bits_3_bits_vs_addr; // @[VSt.scala 100:12 76:19]
- assign f_io_in_bits_3_bits_tin_vs_tag = io_in_bits_3_bits_vs_tag; // @[VSt.scala 100:12 76:19]
+ 'd0}, _f_io_in_bits_3_bits_tin_out_offset_T_3}; // @[VSt.scala 99:22]
+ assign f_io_in_bits_3_bits_tin_remain = f_io_in_bits_3_bits_tin_length ? f_io_in_bits_3_bits_tin_remain1 : 8'h80; // @[VSt.scala 100:22]
+ assign f_io_in_bits_3_bits_tin_vs_valid = io_in_bits_3_bits_vs_valid; // @[VSt.scala 101:12 77:19]
+ assign f_io_in_bits_3_bits_tin_vs_addr = io_in_bits_3_bits_vs_addr; // @[VSt.scala 101:12 77:19]
+ assign f_io_in_bits_3_bits_tin_vs_tag = io_in_bits_3_bits_vs_tag; // @[VSt.scala 101:12 77:19]
assign f_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VCmdq.scala 54:28]
assign f_io_out_ready = _T_8 | io_out_ready & last; // @[VCmdq.scala 57:28]
always @(posedge clock) begin
@@ -109154,28 +108967,6 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(addrAlign == 5'h0)) begin
- $fatal; // @[VSt.scala 111:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(addrAlign == 5'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:111 assert(addrAlign === 0.U)\n"); // @[VSt.scala 111:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(offsAlign == 5'h0)) begin
$fatal; // @[VSt.scala 112:11]
end
`ifdef STOP_COND
@@ -109186,8 +108977,30 @@
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
+ if (~reset & ~(addrAlign == 5'h0)) begin
+ $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:112 assert(addrAlign === 0.U)\n"); // @[VSt.scala 112:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
if (_T_2 & ~(offsAlign == 5'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:112 assert(offsAlign === 0.U)\n"); // @[VSt.scala 112:11]
+ $fatal; // @[VSt.scala 113:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~(offsAlign == 5'h0)) begin
+ $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:113 assert(offsAlign === 0.U)\n"); // @[VSt.scala 113:11]
end
`ifdef PRINTF_COND
end
@@ -109198,7 +109011,7 @@
if (`STOP_COND) begin
`endif
if (_T_2 & ~(~valid | value_tin_op == 7'h3 | _addrAlign_T)) begin
- $fatal; // @[VSt.scala 113:11]
+ $fatal; // @[VSt.scala 114:11]
end
`ifdef STOP_COND
end
@@ -109210,7 +109023,7 @@
`endif
if (_T_2 & ~(~valid | value_tin_op == 7'h3 | _addrAlign_T)) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VSt.scala:113 assert(!valid || in.op === e.vst.U || in.op === e.vstq.U)\n"); // @[VSt.scala 113:11]
+ "Assertion failed\n at VSt.scala:114 assert(!valid || in.op === e.vst.U || in.op === e.vstq.U)\n"); // @[VSt.scala 114:11]
end
`ifdef PRINTF_COND
end
@@ -109221,7 +109034,7 @@
if (`STOP_COND) begin
`endif
if (_T_2 & ~(_f_io_in_bits_0_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VSt.scala 79:11]
+ $fatal; // @[VSt.scala 80:11]
end
`ifdef STOP_COND
end
@@ -109232,7 +109045,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_2 & ~(_f_io_in_bits_0_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:79 assert(PopCount(in.sz) <= 1.U)\n"); // @[VSt.scala 79:11]
+ $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:80 assert(PopCount(in.sz) <= 1.U)\n"); // @[VSt.scala 80:11]
end
`ifdef PRINTF_COND
end
@@ -109243,7 +109056,7 @@
if (`STOP_COND) begin
`endif
if (_T_2 & ~(~(io_in_bits_0_bits_op == 7'h3 & ~io_in_bits_0_bits_vs_valid))) begin
- $fatal; // @[VSt.scala 80:11]
+ $fatal; // @[VSt.scala 81:11]
end
`ifdef STOP_COND
end
@@ -109254,7 +109067,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_2 & ~(~(io_in_bits_0_bits_op == 7'h3 & ~io_in_bits_0_bits_vs_valid))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:80 assert(!(in.op === e.vst.U && !in.vs.valid))\n"); // @[VSt.scala 80:11]
+ $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:81 assert(!(in.op === e.vst.U && !in.vs.valid))\n"); // @[VSt.scala 81:11]
end
`ifdef PRINTF_COND
end
@@ -109265,7 +109078,7 @@
if (`STOP_COND) begin
`endif
if (_T_2 & ~(~(io_in_bits_0_bits_op == 7'h4 & _f_io_in_bits_0_bits_tin_T_12))) begin
- $fatal; // @[VSt.scala 81:11]
+ $fatal; // @[VSt.scala 82:11]
end
`ifdef STOP_COND
end
@@ -109276,7 +109089,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_2 & ~(~(io_in_bits_0_bits_op == 7'h4 & _f_io_in_bits_0_bits_tin_T_12))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:81 assert(!(in.op === e.vstq.U && !in.vs.valid))\n"); // @[VSt.scala 81:11]
+ $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:82 assert(!(in.op === e.vstq.U && !in.vs.valid))\n"); // @[VSt.scala 82:11]
end
`ifdef PRINTF_COND
end
@@ -109287,7 +109100,7 @@
if (`STOP_COND) begin
`endif
if (_T_2 & ~(_f_io_in_bits_1_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VSt.scala 79:11]
+ $fatal; // @[VSt.scala 80:11]
end
`ifdef STOP_COND
end
@@ -109298,7 +109111,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_2 & ~(_f_io_in_bits_1_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:79 assert(PopCount(in.sz) <= 1.U)\n"); // @[VSt.scala 79:11]
+ $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:80 assert(PopCount(in.sz) <= 1.U)\n"); // @[VSt.scala 80:11]
end
`ifdef PRINTF_COND
end
@@ -109309,7 +109122,7 @@
if (`STOP_COND) begin
`endif
if (_T_2 & ~(~(io_in_bits_1_bits_op == 7'h3 & ~io_in_bits_1_bits_vs_valid))) begin
- $fatal; // @[VSt.scala 80:11]
+ $fatal; // @[VSt.scala 81:11]
end
`ifdef STOP_COND
end
@@ -109320,7 +109133,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_2 & ~(~(io_in_bits_1_bits_op == 7'h3 & ~io_in_bits_1_bits_vs_valid))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:80 assert(!(in.op === e.vst.U && !in.vs.valid))\n"); // @[VSt.scala 80:11]
+ $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:81 assert(!(in.op === e.vst.U && !in.vs.valid))\n"); // @[VSt.scala 81:11]
end
`ifdef PRINTF_COND
end
@@ -109331,7 +109144,7 @@
if (`STOP_COND) begin
`endif
if (_T_2 & ~(~(io_in_bits_1_bits_op == 7'h4 & _f_io_in_bits_1_bits_tin_T_12))) begin
- $fatal; // @[VSt.scala 81:11]
+ $fatal; // @[VSt.scala 82:11]
end
`ifdef STOP_COND
end
@@ -109342,7 +109155,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_2 & ~(~(io_in_bits_1_bits_op == 7'h4 & _f_io_in_bits_1_bits_tin_T_12))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:81 assert(!(in.op === e.vstq.U && !in.vs.valid))\n"); // @[VSt.scala 81:11]
+ $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:82 assert(!(in.op === e.vstq.U && !in.vs.valid))\n"); // @[VSt.scala 82:11]
end
`ifdef PRINTF_COND
end
@@ -109353,7 +109166,7 @@
if (`STOP_COND) begin
`endif
if (_T_2 & ~(_f_io_in_bits_2_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VSt.scala 79:11]
+ $fatal; // @[VSt.scala 80:11]
end
`ifdef STOP_COND
end
@@ -109364,7 +109177,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_2 & ~(_f_io_in_bits_2_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:79 assert(PopCount(in.sz) <= 1.U)\n"); // @[VSt.scala 79:11]
+ $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:80 assert(PopCount(in.sz) <= 1.U)\n"); // @[VSt.scala 80:11]
end
`ifdef PRINTF_COND
end
@@ -109375,7 +109188,7 @@
if (`STOP_COND) begin
`endif
if (_T_2 & ~(~(io_in_bits_2_bits_op == 7'h3 & ~io_in_bits_2_bits_vs_valid))) begin
- $fatal; // @[VSt.scala 80:11]
+ $fatal; // @[VSt.scala 81:11]
end
`ifdef STOP_COND
end
@@ -109386,7 +109199,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_2 & ~(~(io_in_bits_2_bits_op == 7'h3 & ~io_in_bits_2_bits_vs_valid))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:80 assert(!(in.op === e.vst.U && !in.vs.valid))\n"); // @[VSt.scala 80:11]
+ $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:81 assert(!(in.op === e.vst.U && !in.vs.valid))\n"); // @[VSt.scala 81:11]
end
`ifdef PRINTF_COND
end
@@ -109397,7 +109210,7 @@
if (`STOP_COND) begin
`endif
if (_T_2 & ~(~(io_in_bits_2_bits_op == 7'h4 & _f_io_in_bits_2_bits_tin_T_12))) begin
- $fatal; // @[VSt.scala 81:11]
+ $fatal; // @[VSt.scala 82:11]
end
`ifdef STOP_COND
end
@@ -109408,7 +109221,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_2 & ~(~(io_in_bits_2_bits_op == 7'h4 & _f_io_in_bits_2_bits_tin_T_12))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:81 assert(!(in.op === e.vstq.U && !in.vs.valid))\n"); // @[VSt.scala 81:11]
+ $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:82 assert(!(in.op === e.vstq.U && !in.vs.valid))\n"); // @[VSt.scala 82:11]
end
`ifdef PRINTF_COND
end
@@ -109419,28 +109232,6 @@
if (`STOP_COND) begin
`endif
if (_T_2 & ~(_f_io_in_bits_3_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VSt.scala 79:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(_f_io_in_bits_3_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:79 assert(PopCount(in.sz) <= 1.U)\n"); // @[VSt.scala 79:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_3_bits_op == 7'h3 & ~io_in_bits_3_bits_vs_valid))) begin
$fatal; // @[VSt.scala 80:11]
end
`ifdef STOP_COND
@@ -109451,8 +109242,8 @@
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
- if (_T_2 & ~(~(io_in_bits_3_bits_op == 7'h3 & ~io_in_bits_3_bits_vs_valid))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:80 assert(!(in.op === e.vst.U && !in.vs.valid))\n"); // @[VSt.scala 80:11]
+ if (_T_2 & ~(_f_io_in_bits_3_bits_tin_T_5[1:0] <= 2'h1)) begin
+ $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:80 assert(PopCount(in.sz) <= 1.U)\n"); // @[VSt.scala 80:11]
end
`ifdef PRINTF_COND
end
@@ -109462,7 +109253,7 @@
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
- if (_T_2 & ~(~(io_in_bits_3_bits_op == 7'h4 & _f_io_in_bits_3_bits_tin_T_12))) begin
+ if (_T_2 & ~(~(io_in_bits_3_bits_op == 7'h3 & ~io_in_bits_3_bits_vs_valid))) begin
$fatal; // @[VSt.scala 81:11]
end
`ifdef STOP_COND
@@ -109473,8 +109264,30 @@
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
+ if (_T_2 & ~(~(io_in_bits_3_bits_op == 7'h3 & ~io_in_bits_3_bits_vs_valid))) begin
+ $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:81 assert(!(in.op === e.vst.U && !in.vs.valid))\n"); // @[VSt.scala 81:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
if (_T_2 & ~(~(io_in_bits_3_bits_op == 7'h4 & _f_io_in_bits_3_bits_tin_T_12))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:81 assert(!(in.op === e.vstq.U && !in.vs.valid))\n"); // @[VSt.scala 81:11]
+ $fatal; // @[VSt.scala 82:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~(~(io_in_bits_3_bits_op == 7'h4 & _f_io_in_bits_3_bits_tin_T_12))) begin
+ $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:82 assert(!(in.op === e.vstq.U && !in.vs.valid))\n"); // @[VSt.scala 82:11]
end
`ifdef PRINTF_COND
end
@@ -109666,28 +109479,28 @@
wire empty = ipos == opos; // @[Slice.scala 29:20]
wire ivalid = io_in_valid & io_in_ready; // @[Slice.scala 31:28]
wire ovalid = io_out_valid & io_out_ready; // @[Slice.scala 32:29]
- assign io_in_ready = empty | io_out_ready; // @[Slice.scala 93:28]
- assign io_out_valid = ~empty; // @[Slice.scala 107:21]
- assign io_out_bits_addr = mem_0_addr; // @[Slice.scala 108:18]
- assign io_out_bits_id = mem_0_id; // @[Slice.scala 108:18]
- assign io_out_bits_size = mem_0_size; // @[Slice.scala 108:18]
- assign io_out_bits_vstq = mem_0_vstq; // @[Slice.scala 108:18]
- assign io_out_bits_quad = mem_0_quad; // @[Slice.scala 108:18]
+ assign io_in_ready = empty | io_out_ready; // @[Slice.scala 74:28]
+ assign io_out_valid = ~empty; // @[Slice.scala 88:21]
+ assign io_out_bits_addr = mem_0_addr; // @[Slice.scala 89:18]
+ assign io_out_bits_id = mem_0_id; // @[Slice.scala 89:18]
+ assign io_out_bits_size = mem_0_size; // @[Slice.scala 89:18]
+ assign io_out_bits_vstq = mem_0_vstq; // @[Slice.scala 89:18]
+ assign io_out_bits_quad = mem_0_quad; // @[Slice.scala 89:18]
always @(posedge clock) begin
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0_addr <= io_in_bits_addr; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0_addr <= io_in_bits_addr; // @[Slice.scala 80:14]
end
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0_id <= io_in_bits_id; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0_id <= io_in_bits_id; // @[Slice.scala 80:14]
end
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0_size <= io_in_bits_size; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0_size <= io_in_bits_size; // @[Slice.scala 80:14]
end
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0_vstq <= io_in_bits_vstq; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0_vstq <= io_in_bits_vstq; // @[Slice.scala 80:14]
end
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0_quad <= io_in_bits_quad; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0_quad <= io_in_bits_quad; // @[Slice.scala 80:14]
end
end
always @(posedge clock or posedge reset) begin
@@ -109795,17 +109608,17 @@
wire _ivalid_T_1 = ~bypass; // @[Slice.scala 31:46]
wire ivalid = io_in_valid & io_in_ready & ~bypass; // @[Slice.scala 31:43]
wire ovalid = io_out_valid & io_out_ready & _ivalid_T_1; // @[Slice.scala 32:45]
- wire _io_value_0_valid_T = ~empty; // @[Slice.scala 102:26]
- assign io_in_ready = empty | io_out_ready; // @[Slice.scala 93:28]
- assign io_out_valid = _io_value_0_valid_T | io_in_valid; // @[Slice.scala 110:28]
- assign io_out_bits_data = _io_value_0_valid_T ? mem_0_data : io_in_bits_data; // @[Slice.scala 111:24]
- assign io_out_bits_strb = _io_value_0_valid_T ? mem_0_strb : io_in_bits_strb; // @[Slice.scala 111:24]
+ wire _io_value_0_valid_T = ~empty; // @[Slice.scala 83:26]
+ assign io_in_ready = empty | io_out_ready; // @[Slice.scala 74:28]
+ assign io_out_valid = _io_value_0_valid_T | io_in_valid; // @[Slice.scala 91:28]
+ assign io_out_bits_data = _io_value_0_valid_T ? mem_0_data : io_in_bits_data; // @[Slice.scala 92:24]
+ assign io_out_bits_strb = _io_value_0_valid_T ? mem_0_strb : io_in_bits_strb; // @[Slice.scala 92:24]
always @(posedge clock) begin
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0_data <= io_in_bits_data; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0_data <= io_in_bits_data; // @[Slice.scala 80:14]
end
- if (ivalid) begin // @[Slice.scala 98:19]
- mem_0_strb <= io_in_bits_strb; // @[Slice.scala 99:14]
+ if (ivalid) begin // @[Slice.scala 79:19]
+ mem_0_strb <= io_in_bits_strb; // @[Slice.scala 80:14]
end
end
always @(posedge clock or posedge reset) begin
@@ -110029,128 +109842,128 @@
wire data_io_out_valid; // @[Slice.scala 9:11]
wire [255:0] data_io_out_bits_data; // @[Slice.scala 9:11]
wire [31:0] data_io_out_bits_strb; // @[Slice.scala 9:11]
- reg dataEn; // @[VSt.scala 170:23]
+ reg dataEn; // @[VSt.scala 171:23]
wire [3:0] _q_io_out_ready_tag_T_1 = q_io_out_bits_vs_tag >> q_io_out_bits_vs_addr[1:0]; // @[VCommon.scala 119:20]
wire q_io_out_ready_tag = _q_io_out_ready_tag_T_1[0]; // @[VCommon.scala 119:20]
wire [6:0] q_io_out_ready_idx = {q_io_out_ready_tag,q_io_out_bits_vs_addr}; // @[Cat.scala 31:58]
wire [127:0] _q_io_out_ready_T_1 = io_vrfsb >> q_io_out_ready_idx; // @[VCommon.scala 122:21]
wire _q_io_out_ready_T_4 = ~q_io_out_bits_vs_valid | ~_q_io_out_ready_T_1[0]; // @[VCommon.scala 122:15]
- wire ctrlready = ctrl_io_in_ready & data_io_in_ready; // @[VSt.scala 265:50]
- wire [7:0] qmaxvlb = q_io_out_bits_op == 7'h4 ? 8'h8 : 8'h20; // @[VSt.scala 231:20]
- wire [7:0] qsize = q_io_out_bits_remain > qmaxvlb ? qmaxvlb : q_io_out_bits_remain; // @[VSt.scala 232:18]
- wire _T_4 = ~reset; // @[VSt.scala 246:9]
- wire [63:0] data_io_in_bits_data_d0 = io_read_data[63:0]; // @[VSt.scala 182:18]
- wire [63:0] data_io_in_bits_data_d1 = io_read_data[127:64]; // @[VSt.scala 183:18]
- wire [63:0] data_io_in_bits_data_d2 = io_read_data[191:128]; // @[VSt.scala 184:18]
- wire [63:0] data_io_in_bits_data_d3 = io_read_data[255:192]; // @[VSt.scala 185:18]
- wire _data_io_in_bits_data_dataout_T = ~ctrl_io_out_bits_vstq; // @[VSt.scala 187:25]
+ wire ctrlready = ctrl_io_in_ready & data_io_in_ready; // @[VSt.scala 266:50]
+ wire [7:0] qmaxvlb = q_io_out_bits_op == 7'h4 ? 8'h8 : 8'h20; // @[VSt.scala 232:20]
+ wire [7:0] qsize = q_io_out_bits_remain > qmaxvlb ? qmaxvlb : q_io_out_bits_remain; // @[VSt.scala 233:18]
+ wire _T_4 = ~reset; // @[VSt.scala 247:9]
+ wire [63:0] data_io_in_bits_data_d0 = io_read_data[63:0]; // @[VSt.scala 183:18]
+ wire [63:0] data_io_in_bits_data_d1 = io_read_data[127:64]; // @[VSt.scala 184:18]
+ wire [63:0] data_io_in_bits_data_d2 = io_read_data[191:128]; // @[VSt.scala 185:18]
+ wire [63:0] data_io_in_bits_data_d3 = io_read_data[255:192]; // @[VSt.scala 186:18]
+ wire _data_io_in_bits_data_dataout_T = ~ctrl_io_out_bits_vstq; // @[VSt.scala 188:25]
wire [255:0] _data_io_in_bits_data_dataout_T_1 = _data_io_in_bits_data_dataout_T ? io_read_data : 256'h0; // @[Library.scala 8:8]
- wire _data_io_in_bits_data_dataout_T_3 = ctrl_io_out_bits_vstq & ctrl_io_out_bits_quad == 2'h0; // @[VSt.scala 188:30]
+ wire _data_io_in_bits_data_dataout_T_3 = ctrl_io_out_bits_vstq & ctrl_io_out_bits_quad == 2'h0; // @[VSt.scala 189:30]
wire [255:0] _data_io_in_bits_data_dataout_T_4 = {data_io_in_bits_data_d0,data_io_in_bits_data_d0,
data_io_in_bits_data_d0,data_io_in_bits_data_d0}; // @[Cat.scala 31:58]
wire [255:0] _data_io_in_bits_data_dataout_T_5 = _data_io_in_bits_data_dataout_T_3 ? _data_io_in_bits_data_dataout_T_4
: 256'h0; // @[Library.scala 8:8]
wire [255:0] _data_io_in_bits_data_dataout_T_6 = _data_io_in_bits_data_dataout_T_1 | _data_io_in_bits_data_dataout_T_5
- ; // @[VSt.scala 187:38]
- wire _data_io_in_bits_data_dataout_T_8 = ctrl_io_out_bits_vstq & ctrl_io_out_bits_quad == 2'h1; // @[VSt.scala 189:30]
+ ; // @[VSt.scala 188:38]
+ wire _data_io_in_bits_data_dataout_T_8 = ctrl_io_out_bits_vstq & ctrl_io_out_bits_quad == 2'h1; // @[VSt.scala 190:30]
wire [255:0] _data_io_in_bits_data_dataout_T_9 = {data_io_in_bits_data_d1,data_io_in_bits_data_d1,
data_io_in_bits_data_d1,data_io_in_bits_data_d1}; // @[Cat.scala 31:58]
wire [255:0] _data_io_in_bits_data_dataout_T_10 = _data_io_in_bits_data_dataout_T_8 ?
_data_io_in_bits_data_dataout_T_9 : 256'h0; // @[Library.scala 8:8]
wire [255:0] _data_io_in_bits_data_dataout_T_11 = _data_io_in_bits_data_dataout_T_6 |
- _data_io_in_bits_data_dataout_T_10; // @[VSt.scala 188:68]
- wire _data_io_in_bits_data_dataout_T_13 = ctrl_io_out_bits_vstq & ctrl_io_out_bits_quad == 2'h2; // @[VSt.scala 190:30]
+ _data_io_in_bits_data_dataout_T_10; // @[VSt.scala 189:68]
+ wire _data_io_in_bits_data_dataout_T_13 = ctrl_io_out_bits_vstq & ctrl_io_out_bits_quad == 2'h2; // @[VSt.scala 191:30]
wire [255:0] _data_io_in_bits_data_dataout_T_14 = {data_io_in_bits_data_d2,data_io_in_bits_data_d2,
data_io_in_bits_data_d2,data_io_in_bits_data_d2}; // @[Cat.scala 31:58]
wire [255:0] _data_io_in_bits_data_dataout_T_15 = _data_io_in_bits_data_dataout_T_13 ?
_data_io_in_bits_data_dataout_T_14 : 256'h0; // @[Library.scala 8:8]
wire [255:0] _data_io_in_bits_data_dataout_T_16 = _data_io_in_bits_data_dataout_T_11 |
- _data_io_in_bits_data_dataout_T_15; // @[VSt.scala 189:68]
- wire _data_io_in_bits_data_dataout_T_18 = ctrl_io_out_bits_vstq & ctrl_io_out_bits_quad == 2'h3; // @[VSt.scala 191:30]
+ _data_io_in_bits_data_dataout_T_15; // @[VSt.scala 190:68]
+ wire _data_io_in_bits_data_dataout_T_18 = ctrl_io_out_bits_vstq & ctrl_io_out_bits_quad == 2'h3; // @[VSt.scala 192:30]
wire [255:0] _data_io_in_bits_data_dataout_T_19 = {data_io_in_bits_data_d3,data_io_in_bits_data_d3,
data_io_in_bits_data_d3,data_io_in_bits_data_d3}; // @[Cat.scala 31:58]
wire [255:0] _data_io_in_bits_data_dataout_T_20 = _data_io_in_bits_data_dataout_T_18 ?
_data_io_in_bits_data_dataout_T_19 : 256'h0; // @[Library.scala 8:8]
- wire data_io_in_bits_strb_strbB_1 = ctrl_io_out_bits_size > 6'h1; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_0 = ctrl_io_out_bits_size > 6'h0; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_3 = ctrl_io_out_bits_size > 6'h3; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_2 = ctrl_io_out_bits_size > 6'h2; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_5 = ctrl_io_out_bits_size > 6'h5; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_4 = ctrl_io_out_bits_size > 6'h4; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_7 = ctrl_io_out_bits_size > 6'h7; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_6 = ctrl_io_out_bits_size > 6'h6; // @[VSt.scala 211:24]
+ wire data_io_in_bits_strb_strbB_1 = ctrl_io_out_bits_size > 6'h1; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_0 = ctrl_io_out_bits_size > 6'h0; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_3 = ctrl_io_out_bits_size > 6'h3; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_2 = ctrl_io_out_bits_size > 6'h2; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_5 = ctrl_io_out_bits_size > 6'h5; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_4 = ctrl_io_out_bits_size > 6'h4; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_7 = ctrl_io_out_bits_size > 6'h7; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_6 = ctrl_io_out_bits_size > 6'h6; // @[VSt.scala 212:24]
wire [7:0] data_io_in_bits_strb_strb_lo_lo = {data_io_in_bits_strb_strbB_7,data_io_in_bits_strb_strbB_6,
data_io_in_bits_strb_strbB_5,data_io_in_bits_strb_strbB_4,data_io_in_bits_strb_strbB_3,data_io_in_bits_strb_strbB_2,
- data_io_in_bits_strb_strbB_1,data_io_in_bits_strb_strbB_0}; // @[VSt.scala 202:22]
- wire data_io_in_bits_strb_strbB_9 = ctrl_io_out_bits_size > 6'h9; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_8 = ctrl_io_out_bits_size > 6'h8; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_11 = ctrl_io_out_bits_size > 6'hb; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_10 = ctrl_io_out_bits_size > 6'ha; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_13 = ctrl_io_out_bits_size > 6'hd; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_12 = ctrl_io_out_bits_size > 6'hc; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_15 = ctrl_io_out_bits_size > 6'hf; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_14 = ctrl_io_out_bits_size > 6'he; // @[VSt.scala 211:24]
+ data_io_in_bits_strb_strbB_1,data_io_in_bits_strb_strbB_0}; // @[VSt.scala 203:22]
+ wire data_io_in_bits_strb_strbB_9 = ctrl_io_out_bits_size > 6'h9; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_8 = ctrl_io_out_bits_size > 6'h8; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_11 = ctrl_io_out_bits_size > 6'hb; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_10 = ctrl_io_out_bits_size > 6'ha; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_13 = ctrl_io_out_bits_size > 6'hd; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_12 = ctrl_io_out_bits_size > 6'hc; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_15 = ctrl_io_out_bits_size > 6'hf; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_14 = ctrl_io_out_bits_size > 6'he; // @[VSt.scala 212:24]
wire [15:0] data_io_in_bits_strb_strb_lo = {data_io_in_bits_strb_strbB_15,data_io_in_bits_strb_strbB_14,
data_io_in_bits_strb_strbB_13,data_io_in_bits_strb_strbB_12,data_io_in_bits_strb_strbB_11,
data_io_in_bits_strb_strbB_10,data_io_in_bits_strb_strbB_9,data_io_in_bits_strb_strbB_8,
- data_io_in_bits_strb_strb_lo_lo}; // @[VSt.scala 202:22]
- wire data_io_in_bits_strb_strbB_17 = ctrl_io_out_bits_size > 6'h11; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_16 = ctrl_io_out_bits_size > 6'h10; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_19 = ctrl_io_out_bits_size > 6'h13; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_18 = ctrl_io_out_bits_size > 6'h12; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_21 = ctrl_io_out_bits_size > 6'h15; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_20 = ctrl_io_out_bits_size > 6'h14; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_23 = ctrl_io_out_bits_size > 6'h17; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_22 = ctrl_io_out_bits_size > 6'h16; // @[VSt.scala 211:24]
+ data_io_in_bits_strb_strb_lo_lo}; // @[VSt.scala 203:22]
+ wire data_io_in_bits_strb_strbB_17 = ctrl_io_out_bits_size > 6'h11; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_16 = ctrl_io_out_bits_size > 6'h10; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_19 = ctrl_io_out_bits_size > 6'h13; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_18 = ctrl_io_out_bits_size > 6'h12; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_21 = ctrl_io_out_bits_size > 6'h15; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_20 = ctrl_io_out_bits_size > 6'h14; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_23 = ctrl_io_out_bits_size > 6'h17; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_22 = ctrl_io_out_bits_size > 6'h16; // @[VSt.scala 212:24]
wire [7:0] data_io_in_bits_strb_strb_hi_lo = {data_io_in_bits_strb_strbB_23,data_io_in_bits_strb_strbB_22,
data_io_in_bits_strb_strbB_21,data_io_in_bits_strb_strbB_20,data_io_in_bits_strb_strbB_19,
- data_io_in_bits_strb_strbB_18,data_io_in_bits_strb_strbB_17,data_io_in_bits_strb_strbB_16}; // @[VSt.scala 202:22]
- wire data_io_in_bits_strb_strbB_25 = ctrl_io_out_bits_size > 6'h19; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_24 = ctrl_io_out_bits_size > 6'h18; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_27 = ctrl_io_out_bits_size > 6'h1b; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_26 = ctrl_io_out_bits_size > 6'h1a; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_29 = ctrl_io_out_bits_size > 6'h1d; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_28 = ctrl_io_out_bits_size > 6'h1c; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_31 = ctrl_io_out_bits_size > 6'h1f; // @[VSt.scala 211:24]
- wire data_io_in_bits_strb_strbB_30 = ctrl_io_out_bits_size > 6'h1e; // @[VSt.scala 211:24]
+ data_io_in_bits_strb_strbB_18,data_io_in_bits_strb_strbB_17,data_io_in_bits_strb_strbB_16}; // @[VSt.scala 203:22]
+ wire data_io_in_bits_strb_strbB_25 = ctrl_io_out_bits_size > 6'h19; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_24 = ctrl_io_out_bits_size > 6'h18; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_27 = ctrl_io_out_bits_size > 6'h1b; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_26 = ctrl_io_out_bits_size > 6'h1a; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_29 = ctrl_io_out_bits_size > 6'h1d; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_28 = ctrl_io_out_bits_size > 6'h1c; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_31 = ctrl_io_out_bits_size > 6'h1f; // @[VSt.scala 212:24]
+ wire data_io_in_bits_strb_strbB_30 = ctrl_io_out_bits_size > 6'h1e; // @[VSt.scala 212:24]
wire [31:0] data_io_in_bits_strb_strb = {data_io_in_bits_strb_strbB_31,data_io_in_bits_strb_strbB_30,
data_io_in_bits_strb_strbB_29,data_io_in_bits_strb_strbB_28,data_io_in_bits_strb_strbB_27,
data_io_in_bits_strb_strbB_26,data_io_in_bits_strb_strbB_25,data_io_in_bits_strb_strbB_24,
- data_io_in_bits_strb_strb_hi_lo,data_io_in_bits_strb_strb_lo}; // @[VSt.scala 202:22]
- wire [7:0] data_io_in_bits_strb_strbq = data_io_in_bits_strb_strb[7:0]; // @[VSt.scala 203:21]
- wire [1:0] data_io_in_bits_strb_quad = ctrl_io_out_bits_addr[4:3]; // @[VSt.scala 207:20]
+ data_io_in_bits_strb_strb_hi_lo,data_io_in_bits_strb_strb_lo}; // @[VSt.scala 203:22]
+ wire [7:0] data_io_in_bits_strb_strbq = data_io_in_bits_strb_strb[7:0]; // @[VSt.scala 204:21]
+ wire [1:0] data_io_in_bits_strb_quad = ctrl_io_out_bits_addr[4:3]; // @[VSt.scala 208:20]
wire [31:0] _data_io_in_bits_strb_strbout_T_1 = _data_io_in_bits_data_dataout_T ? data_io_in_bits_strb_strb : 32'h0; // @[Library.scala 8:8]
- wire _data_io_in_bits_strb_strbout_T_3 = ctrl_io_out_bits_vstq & data_io_in_bits_strb_quad == 2'h0; // @[VSt.scala 215:19]
+ wire _data_io_in_bits_strb_strbout_T_3 = ctrl_io_out_bits_vstq & data_io_in_bits_strb_quad == 2'h0; // @[VSt.scala 216:19]
wire [31:0] _data_io_in_bits_strb_strbout_T_4 = {16'h0,8'h0,data_io_in_bits_strb_strbq}; // @[Cat.scala 31:58]
wire [31:0] _data_io_in_bits_strb_strbout_T_5 = _data_io_in_bits_strb_strbout_T_3 ? _data_io_in_bits_strb_strbout_T_4
: 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_io_in_bits_strb_strbout_T_6 = _data_io_in_bits_strb_strbout_T_1 | _data_io_in_bits_strb_strbout_T_5; // @[VSt.scala 214:38]
- wire _data_io_in_bits_strb_strbout_T_8 = ctrl_io_out_bits_vstq & data_io_in_bits_strb_quad == 2'h1; // @[VSt.scala 216:19]
+ wire [31:0] _data_io_in_bits_strb_strbout_T_6 = _data_io_in_bits_strb_strbout_T_1 | _data_io_in_bits_strb_strbout_T_5; // @[VSt.scala 215:38]
+ wire _data_io_in_bits_strb_strbout_T_8 = ctrl_io_out_bits_vstq & data_io_in_bits_strb_quad == 2'h1; // @[VSt.scala 217:19]
wire [31:0] _data_io_in_bits_strb_strbout_T_9 = {16'h0,data_io_in_bits_strb_strbq,8'h0}; // @[Cat.scala 31:58]
wire [31:0] _data_io_in_bits_strb_strbout_T_10 = _data_io_in_bits_strb_strbout_T_8 ? _data_io_in_bits_strb_strbout_T_9
: 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_io_in_bits_strb_strbout_T_11 = _data_io_in_bits_strb_strbout_T_6 |
- _data_io_in_bits_strb_strbout_T_10; // @[VSt.scala 215:69]
- wire _data_io_in_bits_strb_strbout_T_13 = ctrl_io_out_bits_vstq & data_io_in_bits_strb_quad == 2'h2; // @[VSt.scala 217:19]
+ _data_io_in_bits_strb_strbout_T_10; // @[VSt.scala 216:69]
+ wire _data_io_in_bits_strb_strbout_T_13 = ctrl_io_out_bits_vstq & data_io_in_bits_strb_quad == 2'h2; // @[VSt.scala 218:19]
wire [31:0] _data_io_in_bits_strb_strbout_T_14 = {8'h0,data_io_in_bits_strb_strbq,16'h0}; // @[Cat.scala 31:58]
wire [31:0] _data_io_in_bits_strb_strbout_T_15 = _data_io_in_bits_strb_strbout_T_13 ?
_data_io_in_bits_strb_strbout_T_14 : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_io_in_bits_strb_strbout_T_16 = _data_io_in_bits_strb_strbout_T_11 |
- _data_io_in_bits_strb_strbout_T_15; // @[VSt.scala 216:69]
- wire _data_io_in_bits_strb_strbout_T_18 = ctrl_io_out_bits_vstq & data_io_in_bits_strb_quad == 2'h3; // @[VSt.scala 218:19]
+ _data_io_in_bits_strb_strbout_T_15; // @[VSt.scala 217:69]
+ wire _data_io_in_bits_strb_strbout_T_18 = ctrl_io_out_bits_vstq & data_io_in_bits_strb_quad == 2'h3; // @[VSt.scala 219:19]
wire [31:0] _data_io_in_bits_strb_strbout_T_19 = {data_io_in_bits_strb_strbq,8'h0,16'h0}; // @[Cat.scala 31:58]
wire [31:0] _data_io_in_bits_strb_strbout_T_20 = _data_io_in_bits_strb_strbout_T_18 ?
_data_io_in_bits_strb_strbout_T_19 : 32'h0; // @[Library.scala 8:8]
wire [26:0] io_axi_addr_bits_addr_hi = {1'h0,ctrl_io_out_bits_addr[30:5]}; // @[Cat.scala 31:58]
- reg nempty; // @[VSt.scala 290:23]
- reg [8:0] count; // @[VSt.scala 291:22]
- wire inc = io_axi_addr_valid & io_axi_addr_ready; // @[VSt.scala 292:31]
- wire dec = io_axi_resp_valid & io_axi_resp_ready; // @[VSt.scala 293:31]
- wire _T_27 = inc | dec; // @[VSt.scala 295:13]
- wire [8:0] _GEN_2 = {{8'd0}, inc}; // @[VSt.scala 296:26]
- wire [8:0] _nxtcount_T_1 = count + _GEN_2; // @[VSt.scala 296:26]
- wire [8:0] _GEN_3 = {{8'd0}, dec}; // @[VSt.scala 296:32]
- wire [8:0] nxtcount = _nxtcount_T_1 - _GEN_3; // @[VSt.scala 296:32]
+ reg nempty; // @[VSt.scala 291:23]
+ reg [8:0] count; // @[VSt.scala 292:22]
+ wire inc = io_axi_addr_valid & io_axi_addr_ready; // @[VSt.scala 293:31]
+ wire dec = io_axi_resp_valid & io_axi_resp_ready; // @[VSt.scala 294:31]
+ wire _T_27 = inc | dec; // @[VSt.scala 296:13]
+ wire [8:0] _GEN_2 = {{8'd0}, inc}; // @[VSt.scala 297:26]
+ wire [8:0] _nxtcount_T_1 = count + _GEN_2; // @[VSt.scala 297:26]
+ wire [8:0] _GEN_3 = {{8'd0}, dec}; // @[VSt.scala 297:32]
+ wire [8:0] nxtcount = _nxtcount_T_1 - _GEN_3; // @[VSt.scala 297:32]
VCmdq_5 q ( // @[VCmdq.scala 14:11]
.clock(q_clock),
.reset(q_reset),
@@ -110238,84 +110051,84 @@
.io_out_bits_data(data_io_out_bits_data),
.io_out_bits_strb(data_io_out_bits_strb)
);
- assign io_in_ready = q_io_in_ready; // @[VSt.scala 226:11]
- assign io_active = q_io_active; // @[VSt.scala 286:13]
- assign io_read_valid = q_io_out_valid & q_io_out_bits_vs_valid; // @[VSt.scala 238:35]
- assign io_read_addr = q_io_out_bits_vs_addr; // @[VSt.scala 240:16]
- assign io_axi_addr_valid = ctrl_io_out_valid; // @[VSt.scala 269:21]
+ assign io_in_ready = q_io_in_ready; // @[VSt.scala 227:11]
+ assign io_active = q_io_active; // @[VSt.scala 287:13]
+ assign io_read_valid = q_io_out_valid & q_io_out_bits_vs_valid; // @[VSt.scala 239:35]
+ assign io_read_addr = q_io_out_bits_vs_addr; // @[VSt.scala 241:16]
+ assign io_axi_addr_valid = ctrl_io_out_valid; // @[VSt.scala 270:21]
assign io_axi_addr_bits_addr = {io_axi_addr_bits_addr_hi,5'h0}; // @[Cat.scala 31:58]
- assign io_axi_addr_bits_id = ctrl_io_out_bits_id; // @[VSt.scala 271:23]
- assign io_axi_data_valid = ctrl_io_out_valid; // @[VSt.scala 275:21]
- assign io_axi_data_bits_data = data_io_out_bits_data; // @[VSt.scala 276:25]
- assign io_axi_data_bits_strb = data_io_out_bits_strb; // @[VSt.scala 277:25]
- assign io_axi_resp_ready = 1'h1; // @[VSt.scala 279:21]
- assign io_nempty = q_io_nempty | ctrl_io_out_valid | nempty; // @[VSt.scala 302:49]
+ assign io_axi_addr_bits_id = ctrl_io_out_bits_id; // @[VSt.scala 272:23]
+ assign io_axi_data_valid = ctrl_io_out_valid; // @[VSt.scala 276:21]
+ assign io_axi_data_bits_data = data_io_out_bits_data; // @[VSt.scala 277:25]
+ assign io_axi_data_bits_strb = data_io_out_bits_strb; // @[VSt.scala 278:25]
+ assign io_axi_resp_ready = 1'h1; // @[VSt.scala 280:21]
+ assign io_nempty = q_io_nempty | ctrl_io_out_valid | nempty; // @[VSt.scala 303:49]
assign q_clock = clock;
assign q_reset = reset;
- assign q_io_in_valid = io_in_valid; // @[VSt.scala 226:11]
- assign q_io_in_bits_0_valid = io_in_bits_0_valid; // @[VSt.scala 226:11]
- assign q_io_in_bits_0_bits_op = io_in_bits_0_bits_op; // @[VSt.scala 226:11]
- assign q_io_in_bits_0_bits_f2 = io_in_bits_0_bits_f2; // @[VSt.scala 226:11]
- assign q_io_in_bits_0_bits_sz = io_in_bits_0_bits_sz; // @[VSt.scala 226:11]
- assign q_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VSt.scala 226:11]
- assign q_io_in_bits_0_bits_vs_valid = io_in_bits_0_bits_vs_valid; // @[VSt.scala 226:11]
- assign q_io_in_bits_0_bits_vs_addr = io_in_bits_0_bits_vs_addr; // @[VSt.scala 226:11]
- assign q_io_in_bits_0_bits_vs_tag = io_in_bits_0_bits_vs_tag; // @[VSt.scala 226:11]
- assign q_io_in_bits_0_bits_sv_addr = io_in_bits_0_bits_sv_addr; // @[VSt.scala 226:11]
- assign q_io_in_bits_0_bits_sv_data = io_in_bits_0_bits_sv_data; // @[VSt.scala 226:11]
- assign q_io_in_bits_1_valid = io_in_bits_1_valid; // @[VSt.scala 226:11]
- assign q_io_in_bits_1_bits_op = io_in_bits_1_bits_op; // @[VSt.scala 226:11]
- assign q_io_in_bits_1_bits_f2 = io_in_bits_1_bits_f2; // @[VSt.scala 226:11]
- assign q_io_in_bits_1_bits_sz = io_in_bits_1_bits_sz; // @[VSt.scala 226:11]
- assign q_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VSt.scala 226:11]
- assign q_io_in_bits_1_bits_vs_valid = io_in_bits_1_bits_vs_valid; // @[VSt.scala 226:11]
- assign q_io_in_bits_1_bits_vs_addr = io_in_bits_1_bits_vs_addr; // @[VSt.scala 226:11]
- assign q_io_in_bits_1_bits_vs_tag = io_in_bits_1_bits_vs_tag; // @[VSt.scala 226:11]
- assign q_io_in_bits_1_bits_sv_addr = io_in_bits_1_bits_sv_addr; // @[VSt.scala 226:11]
- assign q_io_in_bits_1_bits_sv_data = io_in_bits_1_bits_sv_data; // @[VSt.scala 226:11]
- assign q_io_in_bits_2_valid = io_in_bits_2_valid; // @[VSt.scala 226:11]
- assign q_io_in_bits_2_bits_op = io_in_bits_2_bits_op; // @[VSt.scala 226:11]
- assign q_io_in_bits_2_bits_f2 = io_in_bits_2_bits_f2; // @[VSt.scala 226:11]
- assign q_io_in_bits_2_bits_sz = io_in_bits_2_bits_sz; // @[VSt.scala 226:11]
- assign q_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VSt.scala 226:11]
- assign q_io_in_bits_2_bits_vs_valid = io_in_bits_2_bits_vs_valid; // @[VSt.scala 226:11]
- assign q_io_in_bits_2_bits_vs_addr = io_in_bits_2_bits_vs_addr; // @[VSt.scala 226:11]
- assign q_io_in_bits_2_bits_vs_tag = io_in_bits_2_bits_vs_tag; // @[VSt.scala 226:11]
- assign q_io_in_bits_2_bits_sv_addr = io_in_bits_2_bits_sv_addr; // @[VSt.scala 226:11]
- assign q_io_in_bits_2_bits_sv_data = io_in_bits_2_bits_sv_data; // @[VSt.scala 226:11]
- assign q_io_in_bits_3_valid = io_in_bits_3_valid; // @[VSt.scala 226:11]
- assign q_io_in_bits_3_bits_op = io_in_bits_3_bits_op; // @[VSt.scala 226:11]
- assign q_io_in_bits_3_bits_f2 = io_in_bits_3_bits_f2; // @[VSt.scala 226:11]
- assign q_io_in_bits_3_bits_sz = io_in_bits_3_bits_sz; // @[VSt.scala 226:11]
- assign q_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VSt.scala 226:11]
- assign q_io_in_bits_3_bits_vs_valid = io_in_bits_3_bits_vs_valid; // @[VSt.scala 226:11]
- assign q_io_in_bits_3_bits_vs_addr = io_in_bits_3_bits_vs_addr; // @[VSt.scala 226:11]
- assign q_io_in_bits_3_bits_vs_tag = io_in_bits_3_bits_vs_tag; // @[VSt.scala 226:11]
- assign q_io_in_bits_3_bits_sv_addr = io_in_bits_3_bits_sv_addr; // @[VSt.scala 226:11]
- assign q_io_in_bits_3_bits_sv_data = io_in_bits_3_bits_sv_data; // @[VSt.scala 226:11]
- assign q_io_out_ready = _q_io_out_ready_T_4 & ctrlready; // @[VSt.scala 229:65]
+ assign q_io_in_valid = io_in_valid; // @[VSt.scala 227:11]
+ assign q_io_in_bits_0_valid = io_in_bits_0_valid; // @[VSt.scala 227:11]
+ assign q_io_in_bits_0_bits_op = io_in_bits_0_bits_op; // @[VSt.scala 227:11]
+ assign q_io_in_bits_0_bits_f2 = io_in_bits_0_bits_f2; // @[VSt.scala 227:11]
+ assign q_io_in_bits_0_bits_sz = io_in_bits_0_bits_sz; // @[VSt.scala 227:11]
+ assign q_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VSt.scala 227:11]
+ assign q_io_in_bits_0_bits_vs_valid = io_in_bits_0_bits_vs_valid; // @[VSt.scala 227:11]
+ assign q_io_in_bits_0_bits_vs_addr = io_in_bits_0_bits_vs_addr; // @[VSt.scala 227:11]
+ assign q_io_in_bits_0_bits_vs_tag = io_in_bits_0_bits_vs_tag; // @[VSt.scala 227:11]
+ assign q_io_in_bits_0_bits_sv_addr = io_in_bits_0_bits_sv_addr; // @[VSt.scala 227:11]
+ assign q_io_in_bits_0_bits_sv_data = io_in_bits_0_bits_sv_data; // @[VSt.scala 227:11]
+ assign q_io_in_bits_1_valid = io_in_bits_1_valid; // @[VSt.scala 227:11]
+ assign q_io_in_bits_1_bits_op = io_in_bits_1_bits_op; // @[VSt.scala 227:11]
+ assign q_io_in_bits_1_bits_f2 = io_in_bits_1_bits_f2; // @[VSt.scala 227:11]
+ assign q_io_in_bits_1_bits_sz = io_in_bits_1_bits_sz; // @[VSt.scala 227:11]
+ assign q_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VSt.scala 227:11]
+ assign q_io_in_bits_1_bits_vs_valid = io_in_bits_1_bits_vs_valid; // @[VSt.scala 227:11]
+ assign q_io_in_bits_1_bits_vs_addr = io_in_bits_1_bits_vs_addr; // @[VSt.scala 227:11]
+ assign q_io_in_bits_1_bits_vs_tag = io_in_bits_1_bits_vs_tag; // @[VSt.scala 227:11]
+ assign q_io_in_bits_1_bits_sv_addr = io_in_bits_1_bits_sv_addr; // @[VSt.scala 227:11]
+ assign q_io_in_bits_1_bits_sv_data = io_in_bits_1_bits_sv_data; // @[VSt.scala 227:11]
+ assign q_io_in_bits_2_valid = io_in_bits_2_valid; // @[VSt.scala 227:11]
+ assign q_io_in_bits_2_bits_op = io_in_bits_2_bits_op; // @[VSt.scala 227:11]
+ assign q_io_in_bits_2_bits_f2 = io_in_bits_2_bits_f2; // @[VSt.scala 227:11]
+ assign q_io_in_bits_2_bits_sz = io_in_bits_2_bits_sz; // @[VSt.scala 227:11]
+ assign q_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VSt.scala 227:11]
+ assign q_io_in_bits_2_bits_vs_valid = io_in_bits_2_bits_vs_valid; // @[VSt.scala 227:11]
+ assign q_io_in_bits_2_bits_vs_addr = io_in_bits_2_bits_vs_addr; // @[VSt.scala 227:11]
+ assign q_io_in_bits_2_bits_vs_tag = io_in_bits_2_bits_vs_tag; // @[VSt.scala 227:11]
+ assign q_io_in_bits_2_bits_sv_addr = io_in_bits_2_bits_sv_addr; // @[VSt.scala 227:11]
+ assign q_io_in_bits_2_bits_sv_data = io_in_bits_2_bits_sv_data; // @[VSt.scala 227:11]
+ assign q_io_in_bits_3_valid = io_in_bits_3_valid; // @[VSt.scala 227:11]
+ assign q_io_in_bits_3_bits_op = io_in_bits_3_bits_op; // @[VSt.scala 227:11]
+ assign q_io_in_bits_3_bits_f2 = io_in_bits_3_bits_f2; // @[VSt.scala 227:11]
+ assign q_io_in_bits_3_bits_sz = io_in_bits_3_bits_sz; // @[VSt.scala 227:11]
+ assign q_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VSt.scala 227:11]
+ assign q_io_in_bits_3_bits_vs_valid = io_in_bits_3_bits_vs_valid; // @[VSt.scala 227:11]
+ assign q_io_in_bits_3_bits_vs_addr = io_in_bits_3_bits_vs_addr; // @[VSt.scala 227:11]
+ assign q_io_in_bits_3_bits_vs_tag = io_in_bits_3_bits_vs_tag; // @[VSt.scala 227:11]
+ assign q_io_in_bits_3_bits_sv_addr = io_in_bits_3_bits_sv_addr; // @[VSt.scala 227:11]
+ assign q_io_in_bits_3_bits_sv_data = io_in_bits_3_bits_sv_data; // @[VSt.scala 227:11]
+ assign q_io_out_ready = _q_io_out_ready_T_4 & ctrlready; // @[VSt.scala 230:65]
assign ctrl_clock = clock;
assign ctrl_reset = reset;
- assign ctrl_io_in_valid = q_io_out_valid & q_io_out_ready; // @[VSt.scala 234:31]
- assign ctrl_io_in_bits_addr = q_io_out_bits_addr; // @[VSt.scala 257:24]
- assign ctrl_io_in_bits_id = q_io_out_bits_vs_addr; // @[VSt.scala 258:24]
- assign ctrl_io_in_bits_size = qsize[5:0]; // @[VSt.scala 259:24]
- assign ctrl_io_in_bits_vstq = q_io_out_bits_op == 7'h4; // @[VSt.scala 260:44]
- assign ctrl_io_in_bits_quad = q_io_out_bits_quad; // @[VSt.scala 261:24]
- assign ctrl_io_out_ready = io_axi_addr_ready; // @[VSt.scala 263:21]
+ assign ctrl_io_in_valid = q_io_out_valid & q_io_out_ready; // @[VSt.scala 235:31]
+ assign ctrl_io_in_bits_addr = q_io_out_bits_addr; // @[VSt.scala 258:24]
+ assign ctrl_io_in_bits_id = q_io_out_bits_vs_addr; // @[VSt.scala 259:24]
+ assign ctrl_io_in_bits_size = qsize[5:0]; // @[VSt.scala 260:24]
+ assign ctrl_io_in_bits_vstq = q_io_out_bits_op == 7'h4; // @[VSt.scala 261:44]
+ assign ctrl_io_in_bits_quad = q_io_out_bits_quad; // @[VSt.scala 262:24]
+ assign ctrl_io_out_ready = io_axi_addr_ready; // @[VSt.scala 264:21]
assign data_clock = clock;
assign data_reset = reset;
- assign data_io_in_valid = dataEn; // @[VSt.scala 245:20]
- assign data_io_in_bits_data = _data_io_in_bits_data_dataout_T_16 | _data_io_in_bits_data_dataout_T_20; // @[VSt.scala 190:68]
- assign data_io_in_bits_strb = _data_io_in_bits_strb_strbout_T_16 | _data_io_in_bits_strb_strbout_T_20; // @[VSt.scala 217:69]
- assign data_io_out_ready = io_axi_addr_ready; // @[VSt.scala 248:21]
+ assign data_io_in_valid = dataEn; // @[VSt.scala 246:20]
+ assign data_io_in_bits_data = _data_io_in_bits_data_dataout_T_16 | _data_io_in_bits_data_dataout_T_20; // @[VSt.scala 191:68]
+ assign data_io_in_bits_strb = _data_io_in_bits_strb_strbout_T_16 | _data_io_in_bits_strb_strbout_T_20; // @[VSt.scala 218:69]
+ assign data_io_out_ready = io_axi_addr_ready; // @[VSt.scala 249:21]
always @(posedge clock) begin
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (~reset & ~(~(data_io_in_valid & ~data_io_in_ready))) begin
- $fatal; // @[VSt.scala 246:9]
+ $fatal; // @[VSt.scala 247:9]
end
`ifdef STOP_COND
end
@@ -110327,7 +110140,7 @@
`endif
if (~reset & ~(~(data_io_in_valid & ~data_io_in_ready))) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VSt.scala:246 assert(!(data.io.in.valid && !data.io.in.ready))\n"); // @[VSt.scala 246:9]
+ "Assertion failed\n at VSt.scala:247 assert(!(data.io.in.valid && !data.io.in.ready))\n"); // @[VSt.scala 247:9]
end
`ifdef PRINTF_COND
end
@@ -110338,29 +110151,6 @@
if (`STOP_COND) begin
`endif
if (_T_4 & ~(~(ctrl_io_out_valid & ~ctrl_io_out_bits_addr[31]))) begin
- $fatal; // @[VSt.scala 272:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(~(ctrl_io_out_valid & ~ctrl_io_out_bits_addr[31]))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VSt.scala:272 assert(!(ctrl.io.out.valid && !ctrl.io.out.bits.addr(31)))\n"); // @[VSt.scala 272:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(~(io_axi_addr_valid & io_axi_addr_bits_addr[31]))) begin
$fatal; // @[VSt.scala 273:9]
end
`ifdef STOP_COND
@@ -110371,9 +110161,9 @@
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
- if (_T_4 & ~(~(io_axi_addr_valid & io_axi_addr_bits_addr[31]))) begin
+ if (_T_4 & ~(~(ctrl_io_out_valid & ~ctrl_io_out_bits_addr[31]))) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VSt.scala:273 assert(!(io.axi.addr.valid && io.axi.addr.bits.addr(31)))\n"); // @[VSt.scala 273:9]
+ "Assertion failed\n at VSt.scala:273 assert(!(ctrl.io.out.valid && !ctrl.io.out.bits.addr(31)))\n"); // @[VSt.scala 273:9]
end
`ifdef PRINTF_COND
end
@@ -110383,8 +110173,8 @@
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
- if (_T_4 & ~(io_axi_addr_valid == io_axi_data_valid)) begin
- $fatal; // @[VSt.scala 281:9]
+ if (_T_4 & ~(~(io_axi_addr_valid & io_axi_addr_bits_addr[31]))) begin
+ $fatal; // @[VSt.scala 274:9]
end
`ifdef STOP_COND
end
@@ -110394,9 +110184,9 @@
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
- if (_T_4 & ~(io_axi_addr_valid == io_axi_data_valid)) begin
+ if (_T_4 & ~(~(io_axi_addr_valid & io_axi_addr_bits_addr[31]))) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VSt.scala:281 assert(io.axi.addr.valid === io.axi.data.valid)\n"); // @[VSt.scala 281:9]
+ "Assertion failed\n at VSt.scala:274 assert(!(io.axi.addr.valid && io.axi.addr.bits.addr(31)))\n"); // @[VSt.scala 274:9]
end
`ifdef PRINTF_COND
end
@@ -110406,7 +110196,7 @@
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
- if (_T_4 & ~(io_axi_addr_ready == io_axi_data_ready)) begin
+ if (_T_4 & ~(io_axi_addr_valid == io_axi_data_valid)) begin
$fatal; // @[VSt.scala 282:9]
end
`ifdef STOP_COND
@@ -110417,9 +110207,32 @@
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
+ if (_T_4 & ~(io_axi_addr_valid == io_axi_data_valid)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at VSt.scala:282 assert(io.axi.addr.valid === io.axi.data.valid)\n"); // @[VSt.scala 282:9]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_4 & ~(io_axi_addr_ready == io_axi_data_ready)) begin
+ $fatal; // @[VSt.scala 283:9]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
if (_T_4 & ~(io_axi_addr_ready == io_axi_data_ready)) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VSt.scala:282 assert(io.axi.addr.ready === io.axi.data.ready)\n"); // @[VSt.scala 282:9]
+ "Assertion failed\n at VSt.scala:283 assert(io.axi.addr.ready === io.axi.data.ready)\n"); // @[VSt.scala 283:9]
end
`ifdef PRINTF_COND
end
@@ -110430,7 +110243,7 @@
if (`STOP_COND) begin
`endif
if (_T_27 & _T_4 & ~(count <= 9'h100)) begin
- $fatal; // @[VSt.scala 299:11]
+ $fatal; // @[VSt.scala 300:11]
end
`ifdef STOP_COND
end
@@ -110441,7 +110254,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_27 & _T_4 & ~(count <= 9'h100)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:299 assert(count <= 256.U)\n"); // @[VSt.scala 299:11]
+ $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:300 assert(count <= 256.U)\n"); // @[VSt.scala 300:11]
end
`ifdef PRINTF_COND
end
@@ -110449,23 +110262,23 @@
`endif // SYNTHESIS
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VSt.scala 234:31]
+ if (reset) begin // @[VSt.scala 235:31]
dataEn <= 1'h0;
end else begin
dataEn <= q_io_out_valid & q_io_out_ready;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VSt.scala 295:21]
- nempty <= 1'h0; // @[VSt.scala 298:12]
- end else if (inc | dec) begin // @[VSt.scala 290:23]
+ if (reset) begin // @[VSt.scala 296:21]
+ nempty <= 1'h0; // @[VSt.scala 299:12]
+ end else if (inc | dec) begin // @[VSt.scala 291:23]
nempty <= nxtcount != 9'h0;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VSt.scala 295:21]
- count <= 9'h0; // @[VSt.scala 297:11]
- end else if (inc | dec) begin // @[VSt.scala 291:22]
+ if (reset) begin // @[VSt.scala 296:21]
+ count <= 9'h0; // @[VSt.scala 298:11]
+ end else if (inc | dec) begin // @[VSt.scala 292:22]
count <= nxtcount;
end
end
@@ -121079,8 +120892,7 @@
`endif
if (_T_18 & ~(~(_convClear_T_1 & _T_457 != 79'h0))) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VRegfile.scala:342 assert(!(convClear0 && (writePrev & convmaska) =/= 0.U)) // TODO: may need to delete, and retain next comments.\n"
- ); // @[VRegfile.scala 342:9]
+ "Assertion failed\n at VRegfile.scala:342 assert(!(convClear0 && (writePrev & convmaska) =/= 0.U))\n"); // @[VRegfile.scala 342:9]
end
`ifdef PRINTF_COND
end
@@ -122221,51 +122033,51 @@
wire _aluready_T_2 = valu_io_in_ready & vdec_io_cmdq_1_alu; // @[VCore.scala 129:39]
wire _aluready_T_3 = valu_io_in_ready & vdec_io_cmdq_0_alu; // @[VCore.scala 130:39]
wire [3:0] aluready = {_aluready_T,_aluready_T_1,_aluready_T_2,_aluready_T_3}; // @[Cat.scala 31:58]
- wire _convvalid_T = vdec_io_out_3_valid & vdec_io_cmdq_3_conv; // @[VCore.scala 170:44]
- wire _convvalid_T_1 = vdec_io_out_2_valid & vdec_io_cmdq_2_conv; // @[VCore.scala 171:44]
- wire _convvalid_T_2 = vdec_io_out_1_valid & vdec_io_cmdq_1_conv; // @[VCore.scala 172:44]
- wire _convvalid_T_3 = vdec_io_out_0_valid & vdec_io_cmdq_0_conv; // @[VCore.scala 173:44]
+ wire _convvalid_T = vdec_io_out_3_valid & vdec_io_cmdq_3_conv; // @[VCore.scala 167:44]
+ wire _convvalid_T_1 = vdec_io_out_2_valid & vdec_io_cmdq_2_conv; // @[VCore.scala 168:44]
+ wire _convvalid_T_2 = vdec_io_out_1_valid & vdec_io_cmdq_1_conv; // @[VCore.scala 169:44]
+ wire _convvalid_T_3 = vdec_io_out_0_valid & vdec_io_cmdq_0_conv; // @[VCore.scala 170:44]
wire [3:0] convvalid = {_convvalid_T,_convvalid_T_1,_convvalid_T_2,_convvalid_T_3}; // @[Cat.scala 31:58]
- wire _convready_T = vconv_io_in_ready & vdec_io_cmdq_3_conv; // @[VCore.scala 175:41]
- wire _convready_T_1 = vconv_io_in_ready & vdec_io_cmdq_2_conv; // @[VCore.scala 176:41]
- wire _convready_T_2 = vconv_io_in_ready & vdec_io_cmdq_1_conv; // @[VCore.scala 177:41]
- wire _convready_T_3 = vconv_io_in_ready & vdec_io_cmdq_0_conv; // @[VCore.scala 178:41]
+ wire _convready_T = vconv_io_in_ready & vdec_io_cmdq_3_conv; // @[VCore.scala 172:41]
+ wire _convready_T_1 = vconv_io_in_ready & vdec_io_cmdq_2_conv; // @[VCore.scala 173:41]
+ wire _convready_T_2 = vconv_io_in_ready & vdec_io_cmdq_1_conv; // @[VCore.scala 174:41]
+ wire _convready_T_3 = vconv_io_in_ready & vdec_io_cmdq_0_conv; // @[VCore.scala 175:41]
wire [3:0] convready = {_convready_T,_convready_T_1,_convready_T_2,_convready_T_3}; // @[Cat.scala 31:58]
- wire _ldstvalid_T = vdec_io_out_3_valid & vdec_io_cmdq_3_ldst; // @[VCore.scala 193:44]
- wire _ldstvalid_T_1 = vdec_io_out_2_valid & vdec_io_cmdq_2_ldst; // @[VCore.scala 194:44]
- wire _ldstvalid_T_2 = vdec_io_out_1_valid & vdec_io_cmdq_1_ldst; // @[VCore.scala 195:44]
- wire _ldstvalid_T_3 = vdec_io_out_0_valid & vdec_io_cmdq_0_ldst; // @[VCore.scala 196:44]
+ wire _ldstvalid_T = vdec_io_out_3_valid & vdec_io_cmdq_3_ldst; // @[VCore.scala 190:44]
+ wire _ldstvalid_T_1 = vdec_io_out_2_valid & vdec_io_cmdq_2_ldst; // @[VCore.scala 191:44]
+ wire _ldstvalid_T_2 = vdec_io_out_1_valid & vdec_io_cmdq_1_ldst; // @[VCore.scala 192:44]
+ wire _ldstvalid_T_3 = vdec_io_out_0_valid & vdec_io_cmdq_0_ldst; // @[VCore.scala 193:44]
wire [3:0] ldstvalid = {_ldstvalid_T,_ldstvalid_T_1,_ldstvalid_T_2,_ldstvalid_T_3}; // @[Cat.scala 31:58]
- wire _ldstready_T = vldst_io_in_ready & vdec_io_cmdq_3_ldst; // @[VCore.scala 198:41]
- wire _ldstready_T_1 = vldst_io_in_ready & vdec_io_cmdq_2_ldst; // @[VCore.scala 199:41]
- wire _ldstready_T_2 = vldst_io_in_ready & vdec_io_cmdq_1_ldst; // @[VCore.scala 200:41]
- wire _ldstready_T_3 = vldst_io_in_ready & vdec_io_cmdq_0_ldst; // @[VCore.scala 201:41]
+ wire _ldstready_T = vldst_io_in_ready & vdec_io_cmdq_3_ldst; // @[VCore.scala 195:41]
+ wire _ldstready_T_1 = vldst_io_in_ready & vdec_io_cmdq_2_ldst; // @[VCore.scala 196:41]
+ wire _ldstready_T_2 = vldst_io_in_ready & vdec_io_cmdq_1_ldst; // @[VCore.scala 197:41]
+ wire _ldstready_T_3 = vldst_io_in_ready & vdec_io_cmdq_0_ldst; // @[VCore.scala 198:41]
wire [3:0] ldstready = {_ldstready_T,_ldstready_T_1,_ldstready_T_2,_ldstready_T_3}; // @[Cat.scala 31:58]
- wire _ldvalid_T = vdec_io_cmdq_3_ld & vdec_io_out_3_valid; // @[VCore.scala 223:37]
- wire _ldvalid_T_1 = vdec_io_cmdq_2_ld & vdec_io_out_2_valid; // @[VCore.scala 224:37]
- wire _ldvalid_T_2 = vdec_io_cmdq_1_ld & vdec_io_out_1_valid; // @[VCore.scala 225:37]
- wire _ldvalid_T_3 = vdec_io_cmdq_0_ld & vdec_io_out_0_valid; // @[VCore.scala 226:37]
+ wire _ldvalid_T = vdec_io_cmdq_3_ld & vdec_io_out_3_valid; // @[VCore.scala 220:37]
+ wire _ldvalid_T_1 = vdec_io_cmdq_2_ld & vdec_io_out_2_valid; // @[VCore.scala 221:37]
+ wire _ldvalid_T_2 = vdec_io_cmdq_1_ld & vdec_io_out_1_valid; // @[VCore.scala 222:37]
+ wire _ldvalid_T_3 = vdec_io_cmdq_0_ld & vdec_io_out_0_valid; // @[VCore.scala 223:37]
wire [3:0] ldvalid = {_ldvalid_T,_ldvalid_T_1,_ldvalid_T_2,_ldvalid_T_3}; // @[Cat.scala 31:58]
- wire _ldready_T = vdec_io_cmdq_3_ld & vld_io_in_ready; // @[VCore.scala 228:37]
- wire _ldready_T_1 = vdec_io_cmdq_2_ld & vld_io_in_ready; // @[VCore.scala 229:37]
- wire _ldready_T_2 = vdec_io_cmdq_1_ld & vld_io_in_ready; // @[VCore.scala 230:37]
- wire _ldready_T_3 = vdec_io_cmdq_0_ld & vld_io_in_ready; // @[VCore.scala 231:37]
+ wire _ldready_T = vdec_io_cmdq_3_ld & vld_io_in_ready; // @[VCore.scala 225:37]
+ wire _ldready_T_1 = vdec_io_cmdq_2_ld & vld_io_in_ready; // @[VCore.scala 226:37]
+ wire _ldready_T_2 = vdec_io_cmdq_1_ld & vld_io_in_ready; // @[VCore.scala 227:37]
+ wire _ldready_T_3 = vdec_io_cmdq_0_ld & vld_io_in_ready; // @[VCore.scala 228:37]
wire [3:0] ldready = {_ldready_T,_ldready_T_1,_ldready_T_2,_ldready_T_3}; // @[Cat.scala 31:58]
- wire _stvalid_T = vdec_io_out_3_valid & vdec_io_cmdq_3_st; // @[VCore.scala 247:39]
- wire _stvalid_T_1 = vdec_io_out_2_valid & vdec_io_cmdq_2_st; // @[VCore.scala 248:39]
- wire _stvalid_T_2 = vdec_io_out_1_valid & vdec_io_cmdq_1_st; // @[VCore.scala 249:39]
- wire _stvalid_T_3 = vdec_io_out_0_valid & vdec_io_cmdq_0_st; // @[VCore.scala 250:39]
+ wire _stvalid_T = vdec_io_out_3_valid & vdec_io_cmdq_3_st; // @[VCore.scala 244:39]
+ wire _stvalid_T_1 = vdec_io_out_2_valid & vdec_io_cmdq_2_st; // @[VCore.scala 245:39]
+ wire _stvalid_T_2 = vdec_io_out_1_valid & vdec_io_cmdq_1_st; // @[VCore.scala 246:39]
+ wire _stvalid_T_3 = vdec_io_out_0_valid & vdec_io_cmdq_0_st; // @[VCore.scala 247:39]
wire [3:0] stvalid = {_stvalid_T,_stvalid_T_1,_stvalid_T_2,_stvalid_T_3}; // @[Cat.scala 31:58]
- wire _stready_T = vst_io_in_ready & vdec_io_cmdq_3_st; // @[VCore.scala 252:34]
- wire _stready_T_1 = vst_io_in_ready & vdec_io_cmdq_2_st; // @[VCore.scala 253:34]
- wire _stready_T_2 = vst_io_in_ready & vdec_io_cmdq_1_st; // @[VCore.scala 254:34]
- wire _stready_T_3 = vst_io_in_ready & vdec_io_cmdq_0_st; // @[VCore.scala 255:34]
+ wire _stready_T = vst_io_in_ready & vdec_io_cmdq_3_st; // @[VCore.scala 249:34]
+ wire _stready_T_1 = vst_io_in_ready & vdec_io_cmdq_2_st; // @[VCore.scala 250:34]
+ wire _stready_T_2 = vst_io_in_ready & vdec_io_cmdq_1_st; // @[VCore.scala 251:34]
+ wire _stready_T_3 = vst_io_in_ready & vdec_io_cmdq_0_st; // @[VCore.scala 252:34]
wire [3:0] stready = {_stready_T,_stready_T_1,_stready_T_2,_stready_T_3}; // @[Cat.scala 31:58]
- wire _vdec_io_out_0_ready_T_6 = aluready[0] | convready[0] | ldstready[0] | ldready[0]; // @[VCore.scala 292:73]
- wire _vdec_io_out_1_ready_T_6 = aluready[1] | convready[1] | ldstready[1] | ldready[1]; // @[VCore.scala 292:73]
- wire _vdec_io_out_2_ready_T_6 = aluready[2] | convready[2] | ldstready[2] | ldready[2]; // @[VCore.scala 292:73]
- wire _vdec_io_out_3_ready_T_6 = aluready[3] | convready[3] | ldstready[3] | ldready[3]; // @[VCore.scala 292:73]
- wire _io_score_mactive_T_1 = vinst_io_nempty | vdec_io_nempty | vld_io_nempty; // @[VCore.scala 298:57]
+ wire _vdec_io_out_0_ready_T_6 = aluready[0] | convready[0] | ldstready[0] | ldready[0]; // @[VCore.scala 289:73]
+ wire _vdec_io_out_1_ready_T_6 = aluready[1] | convready[1] | ldstready[1] | ldready[1]; // @[VCore.scala 289:73]
+ wire _vdec_io_out_2_ready_T_6 = aluready[2] | convready[2] | ldstready[2] | ldready[2]; // @[VCore.scala 289:73]
+ wire _vdec_io_out_3_ready_T_6 = aluready[3] | convready[3] | ldstready[3] | ldready[3]; // @[VCore.scala 289:73]
+ wire _io_score_mactive_T_1 = vinst_io_nempty | vdec_io_nempty | vld_io_nempty; // @[VCore.scala 295:57]
VInst vinst ( // @[VInst.scala 9:18]
.clock(vinst_clock),
.reset(vinst_reset),
@@ -123014,25 +122826,25 @@
assign io_score_rd_3_valid = vinst_io_rd_3_valid; // @[VCore.scala 68:15]
assign io_score_rd_3_addr = vinst_io_rd_3_addr; // @[VCore.scala 68:15]
assign io_score_rd_3_data = vinst_io_rd_3_data; // @[VCore.scala 68:15]
- assign io_score_mactive = _io_score_mactive_T_1 | vst_io_nempty; // @[VCore.scala 299:37]
+ assign io_score_mactive = _io_score_mactive_T_1 | vst_io_nempty; // @[VCore.scala 296:37]
assign io_score_undef = vdec_io_undef; // @[VCore.scala 90:18]
- assign io_dbus_valid = vldst_io_dbus_valid; // @[VCore.scala 215:11]
- assign io_dbus_write = vldst_io_dbus_write; // @[VCore.scala 215:11]
- assign io_dbus_addr = vldst_io_dbus_addr; // @[VCore.scala 215:11]
- assign io_dbus_adrx = vldst_io_dbus_adrx; // @[VCore.scala 215:11]
- assign io_dbus_size = vldst_io_dbus_size; // @[VCore.scala 215:11]
- assign io_dbus_wdata = vldst_io_dbus_wdata; // @[VCore.scala 215:11]
- assign io_dbus_wmask = vldst_io_dbus_wmask; // @[VCore.scala 215:11]
- assign io_last = vldst_io_last; // @[VCore.scala 216:11]
- assign io_ld_addr_valid = vld_io_axi_addr_valid; // @[VCore.scala 240:9]
- assign io_ld_addr_bits_addr = vld_io_axi_addr_bits_addr; // @[VCore.scala 240:9]
- assign io_ld_addr_bits_id = vld_io_axi_addr_bits_id; // @[VCore.scala 240:9]
- assign io_st_addr_valid = vst_io_axi_addr_valid; // @[VCore.scala 264:9]
- assign io_st_addr_bits_addr = vst_io_axi_addr_bits_addr; // @[VCore.scala 264:9]
- assign io_st_addr_bits_id = vst_io_axi_addr_bits_id; // @[VCore.scala 264:9]
- assign io_st_data_valid = vst_io_axi_data_valid; // @[VCore.scala 264:9]
- assign io_st_data_bits_data = vst_io_axi_data_bits_data; // @[VCore.scala 264:9]
- assign io_st_data_bits_strb = vst_io_axi_data_bits_strb; // @[VCore.scala 264:9]
+ assign io_dbus_valid = vldst_io_dbus_valid; // @[VCore.scala 212:11]
+ assign io_dbus_write = vldst_io_dbus_write; // @[VCore.scala 212:11]
+ assign io_dbus_addr = vldst_io_dbus_addr; // @[VCore.scala 212:11]
+ assign io_dbus_adrx = vldst_io_dbus_adrx; // @[VCore.scala 212:11]
+ assign io_dbus_size = vldst_io_dbus_size; // @[VCore.scala 212:11]
+ assign io_dbus_wdata = vldst_io_dbus_wdata; // @[VCore.scala 212:11]
+ assign io_dbus_wmask = vldst_io_dbus_wmask; // @[VCore.scala 212:11]
+ assign io_last = vldst_io_last; // @[VCore.scala 213:11]
+ assign io_ld_addr_valid = vld_io_axi_addr_valid; // @[VCore.scala 237:9]
+ assign io_ld_addr_bits_addr = vld_io_axi_addr_bits_addr; // @[VCore.scala 237:9]
+ assign io_ld_addr_bits_id = vld_io_axi_addr_bits_id; // @[VCore.scala 237:9]
+ assign io_st_addr_valid = vst_io_axi_addr_valid; // @[VCore.scala 261:9]
+ assign io_st_addr_bits_addr = vst_io_axi_addr_bits_addr; // @[VCore.scala 261:9]
+ assign io_st_addr_bits_id = vst_io_axi_addr_bits_id; // @[VCore.scala 261:9]
+ assign io_st_data_valid = vst_io_axi_data_valid; // @[VCore.scala 261:9]
+ assign io_st_data_bits_data = vst_io_axi_data_bits_data; // @[VCore.scala 261:9]
+ assign io_st_data_bits_strb = vst_io_axi_data_bits_strb; // @[VCore.scala 261:9]
assign vinst_clock = clock;
assign vinst_reset = reset;
assign vinst_io_in_0_valid = io_score_vinst_0_valid; // @[VCore.scala 66:15]
@@ -123084,10 +122896,10 @@
assign vdec_io_in_bits_3_bits_inst = vinst_io_out_lane_3_bits_inst; // @[VCore.scala 87:24]
assign vdec_io_in_bits_3_bits_addr = vinst_io_out_lane_3_bits_addr; // @[VCore.scala 87:24]
assign vdec_io_in_bits_3_bits_data = vinst_io_out_lane_3_bits_data; // @[VCore.scala 87:24]
- assign vdec_io_out_0_ready = _vdec_io_out_0_ready_T_6 | stready[0]; // @[VCore.scala 293:40]
- assign vdec_io_out_1_ready = _vdec_io_out_1_ready_T_6 | stready[1]; // @[VCore.scala 293:40]
- assign vdec_io_out_2_ready = _vdec_io_out_2_ready_T_6 | stready[2]; // @[VCore.scala 293:40]
- assign vdec_io_out_3_ready = _vdec_io_out_3_ready_T_6 | stready[3]; // @[VCore.scala 293:40]
+ assign vdec_io_out_0_ready = _vdec_io_out_0_ready_T_6 | stready[0]; // @[VCore.scala 290:40]
+ assign vdec_io_out_1_ready = _vdec_io_out_1_ready_T_6 | stready[1]; // @[VCore.scala 290:40]
+ assign vdec_io_out_2_ready = _vdec_io_out_2_ready_T_6 | stready[2]; // @[VCore.scala 290:40]
+ assign vdec_io_out_3_ready = _vdec_io_out_3_ready_T_6 | stready[3]; // @[VCore.scala 290:40]
assign vdec_io_active = _vdec_io_active_T_1 | vst_io_active; // @[VCore.scala 78:72]
assign vdec_io_vrfsb_data = vrf_io_vrfsb_data; // @[VCore.scala 76:17]
assign valu_clock = clock;
@@ -123213,7 +123025,7 @@
assign valu_io_in_bits_3_bits_sv_valid = vdec_io_out_3_bits_sv_valid; // @[VCore.scala 136:29]
assign valu_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 136:29]
assign valu_io_in_bits_3_bits_cmdsync = vdec_io_out_3_bits_cmdsync; // @[VCore.scala 136:29]
- assign valu_io_vrfsb = vrf_io_vrfsb_data; // @[VCore.scala 166:17]
+ assign valu_io_vrfsb = vrf_io_vrfsb_data; // @[VCore.scala 163:17]
assign valu_io_read_0_data = vrf_io_read_0_data; // @[VCore.scala 146:26]
assign valu_io_read_1_data = vrf_io_read_1_data; // @[VCore.scala 146:26]
assign valu_io_read_2_data = vrf_io_read_2_data; // @[VCore.scala 146:26]
@@ -123222,184 +123034,184 @@
assign valu_io_read_5_data = vrf_io_read_5_data; // @[VCore.scala 146:26]
assign vconv_clock = clock;
assign vconv_reset = reset;
- assign vconv_io_in_valid = convvalid != 4'h0; // @[VCore.scala 180:34]
- assign vconv_io_in_bits_0_valid = convvalid[0]; // @[VCore.scala 183:43]
- assign vconv_io_in_bits_0_bits_op = vdec_io_out_0_bits_op; // @[VCore.scala 184:30]
- assign vconv_io_in_bits_0_bits_m = vdec_io_out_0_bits_m; // @[VCore.scala 184:30]
- assign vconv_io_in_bits_0_bits_vs_addr = vdec_io_out_0_bits_vs_addr; // @[VCore.scala 184:30]
- assign vconv_io_in_bits_0_bits_vu_addr = vdec_io_out_0_bits_vu_addr; // @[VCore.scala 184:30]
- assign vconv_io_in_bits_0_bits_sv_data = vdec_io_out_0_bits_sv_data; // @[VCore.scala 184:30]
- assign vconv_io_in_bits_1_valid = convvalid[1]; // @[VCore.scala 183:43]
- assign vconv_io_in_bits_1_bits_op = vdec_io_out_1_bits_op; // @[VCore.scala 184:30]
- assign vconv_io_in_bits_1_bits_m = vdec_io_out_1_bits_m; // @[VCore.scala 184:30]
- assign vconv_io_in_bits_1_bits_vs_addr = vdec_io_out_1_bits_vs_addr; // @[VCore.scala 184:30]
- assign vconv_io_in_bits_1_bits_vu_addr = vdec_io_out_1_bits_vu_addr; // @[VCore.scala 184:30]
- assign vconv_io_in_bits_1_bits_sv_data = vdec_io_out_1_bits_sv_data; // @[VCore.scala 184:30]
- assign vconv_io_in_bits_2_valid = convvalid[2]; // @[VCore.scala 183:43]
- assign vconv_io_in_bits_2_bits_op = vdec_io_out_2_bits_op; // @[VCore.scala 184:30]
- assign vconv_io_in_bits_2_bits_m = vdec_io_out_2_bits_m; // @[VCore.scala 184:30]
- assign vconv_io_in_bits_2_bits_vs_addr = vdec_io_out_2_bits_vs_addr; // @[VCore.scala 184:30]
- assign vconv_io_in_bits_2_bits_vu_addr = vdec_io_out_2_bits_vu_addr; // @[VCore.scala 184:30]
- assign vconv_io_in_bits_2_bits_sv_data = vdec_io_out_2_bits_sv_data; // @[VCore.scala 184:30]
- assign vconv_io_in_bits_3_valid = convvalid[3]; // @[VCore.scala 183:43]
- assign vconv_io_in_bits_3_bits_op = vdec_io_out_3_bits_op; // @[VCore.scala 184:30]
- assign vconv_io_in_bits_3_bits_m = vdec_io_out_3_bits_m; // @[VCore.scala 184:30]
- assign vconv_io_in_bits_3_bits_vs_addr = vdec_io_out_3_bits_vs_addr; // @[VCore.scala 184:30]
- assign vconv_io_in_bits_3_bits_vu_addr = vdec_io_out_3_bits_vu_addr; // @[VCore.scala 184:30]
- assign vconv_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 184:30]
- assign vconv_io_vrfsb = vrf_io_vrfsb_data; // @[VCore.scala 189:18]
+ assign vconv_io_in_valid = convvalid != 4'h0; // @[VCore.scala 177:34]
+ assign vconv_io_in_bits_0_valid = convvalid[0]; // @[VCore.scala 180:43]
+ assign vconv_io_in_bits_0_bits_op = vdec_io_out_0_bits_op; // @[VCore.scala 181:30]
+ assign vconv_io_in_bits_0_bits_m = vdec_io_out_0_bits_m; // @[VCore.scala 181:30]
+ assign vconv_io_in_bits_0_bits_vs_addr = vdec_io_out_0_bits_vs_addr; // @[VCore.scala 181:30]
+ assign vconv_io_in_bits_0_bits_vu_addr = vdec_io_out_0_bits_vu_addr; // @[VCore.scala 181:30]
+ assign vconv_io_in_bits_0_bits_sv_data = vdec_io_out_0_bits_sv_data; // @[VCore.scala 181:30]
+ assign vconv_io_in_bits_1_valid = convvalid[1]; // @[VCore.scala 180:43]
+ assign vconv_io_in_bits_1_bits_op = vdec_io_out_1_bits_op; // @[VCore.scala 181:30]
+ assign vconv_io_in_bits_1_bits_m = vdec_io_out_1_bits_m; // @[VCore.scala 181:30]
+ assign vconv_io_in_bits_1_bits_vs_addr = vdec_io_out_1_bits_vs_addr; // @[VCore.scala 181:30]
+ assign vconv_io_in_bits_1_bits_vu_addr = vdec_io_out_1_bits_vu_addr; // @[VCore.scala 181:30]
+ assign vconv_io_in_bits_1_bits_sv_data = vdec_io_out_1_bits_sv_data; // @[VCore.scala 181:30]
+ assign vconv_io_in_bits_2_valid = convvalid[2]; // @[VCore.scala 180:43]
+ assign vconv_io_in_bits_2_bits_op = vdec_io_out_2_bits_op; // @[VCore.scala 181:30]
+ assign vconv_io_in_bits_2_bits_m = vdec_io_out_2_bits_m; // @[VCore.scala 181:30]
+ assign vconv_io_in_bits_2_bits_vs_addr = vdec_io_out_2_bits_vs_addr; // @[VCore.scala 181:30]
+ assign vconv_io_in_bits_2_bits_vu_addr = vdec_io_out_2_bits_vu_addr; // @[VCore.scala 181:30]
+ assign vconv_io_in_bits_2_bits_sv_data = vdec_io_out_2_bits_sv_data; // @[VCore.scala 181:30]
+ assign vconv_io_in_bits_3_valid = convvalid[3]; // @[VCore.scala 180:43]
+ assign vconv_io_in_bits_3_bits_op = vdec_io_out_3_bits_op; // @[VCore.scala 181:30]
+ assign vconv_io_in_bits_3_bits_m = vdec_io_out_3_bits_m; // @[VCore.scala 181:30]
+ assign vconv_io_in_bits_3_bits_vs_addr = vdec_io_out_3_bits_vs_addr; // @[VCore.scala 181:30]
+ assign vconv_io_in_bits_3_bits_vu_addr = vdec_io_out_3_bits_vu_addr; // @[VCore.scala 181:30]
+ assign vconv_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 181:30]
+ assign vconv_io_vrfsb = vrf_io_vrfsb_data; // @[VCore.scala 186:18]
assign vldst_clock = clock;
assign vldst_reset = reset;
- assign vldst_io_in_valid = ldstvalid != 4'h0; // @[VCore.scala 203:34]
- assign vldst_io_in_bits_0_valid = ldstvalid[0]; // @[VCore.scala 206:43]
- assign vldst_io_in_bits_0_bits_op = vdec_io_out_0_bits_op; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_0_bits_f2 = vdec_io_out_0_bits_f2; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_0_bits_sz = vdec_io_out_0_bits_sz; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_0_bits_m = vdec_io_out_0_bits_m; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_0_bits_vd_valid = vdec_io_out_0_bits_vd_valid; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_0_bits_vd_addr = vdec_io_out_0_bits_vd_addr; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_0_bits_vs_valid = vdec_io_out_0_bits_vs_valid; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_0_bits_vs_addr = vdec_io_out_0_bits_vs_addr; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_0_bits_vs_tag = vdec_io_out_0_bits_vs_tag; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_0_bits_sv_addr = vdec_io_out_0_bits_sv_addr; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_0_bits_sv_data = vdec_io_out_0_bits_sv_data; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_1_valid = ldstvalid[1]; // @[VCore.scala 206:43]
- assign vldst_io_in_bits_1_bits_op = vdec_io_out_1_bits_op; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_1_bits_f2 = vdec_io_out_1_bits_f2; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_1_bits_sz = vdec_io_out_1_bits_sz; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_1_bits_m = vdec_io_out_1_bits_m; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_1_bits_vd_valid = vdec_io_out_1_bits_vd_valid; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_1_bits_vd_addr = vdec_io_out_1_bits_vd_addr; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_1_bits_vs_valid = vdec_io_out_1_bits_vs_valid; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_1_bits_vs_addr = vdec_io_out_1_bits_vs_addr; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_1_bits_vs_tag = vdec_io_out_1_bits_vs_tag; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_1_bits_sv_addr = vdec_io_out_1_bits_sv_addr; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_1_bits_sv_data = vdec_io_out_1_bits_sv_data; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_2_valid = ldstvalid[2]; // @[VCore.scala 206:43]
- assign vldst_io_in_bits_2_bits_op = vdec_io_out_2_bits_op; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_2_bits_f2 = vdec_io_out_2_bits_f2; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_2_bits_sz = vdec_io_out_2_bits_sz; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_2_bits_m = vdec_io_out_2_bits_m; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_2_bits_vd_valid = vdec_io_out_2_bits_vd_valid; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_2_bits_vd_addr = vdec_io_out_2_bits_vd_addr; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_2_bits_vs_valid = vdec_io_out_2_bits_vs_valid; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_2_bits_vs_addr = vdec_io_out_2_bits_vs_addr; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_2_bits_vs_tag = vdec_io_out_2_bits_vs_tag; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_2_bits_sv_addr = vdec_io_out_2_bits_sv_addr; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_2_bits_sv_data = vdec_io_out_2_bits_sv_data; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_3_valid = ldstvalid[3]; // @[VCore.scala 206:43]
- assign vldst_io_in_bits_3_bits_op = vdec_io_out_3_bits_op; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_3_bits_f2 = vdec_io_out_3_bits_f2; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_3_bits_sz = vdec_io_out_3_bits_sz; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_3_bits_m = vdec_io_out_3_bits_m; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_3_bits_vd_valid = vdec_io_out_3_bits_vd_valid; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_3_bits_vd_addr = vdec_io_out_3_bits_vd_addr; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_3_bits_vs_valid = vdec_io_out_3_bits_vs_valid; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_3_bits_vs_addr = vdec_io_out_3_bits_vs_addr; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_3_bits_vs_tag = vdec_io_out_3_bits_vs_tag; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_3_bits_sv_addr = vdec_io_out_3_bits_sv_addr; // @[VCore.scala 207:30]
- assign vldst_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 207:30]
- assign vldst_io_vrfsb = vrf_io_vrfsb_data; // @[VCore.scala 213:18]
- assign vldst_io_read_ready = ~vst_io_read_valid; // @[VCore.scala 210:26]
- assign vldst_io_read_data = vrf_io_read_6_data; // @[VCore.scala 211:22]
- assign vldst_io_dbus_ready = io_dbus_ready; // @[VCore.scala 215:11]
- assign vldst_io_dbus_rdata = io_dbus_rdata; // @[VCore.scala 215:11]
+ assign vldst_io_in_valid = ldstvalid != 4'h0; // @[VCore.scala 200:34]
+ assign vldst_io_in_bits_0_valid = ldstvalid[0]; // @[VCore.scala 203:43]
+ assign vldst_io_in_bits_0_bits_op = vdec_io_out_0_bits_op; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_0_bits_f2 = vdec_io_out_0_bits_f2; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_0_bits_sz = vdec_io_out_0_bits_sz; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_0_bits_m = vdec_io_out_0_bits_m; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_0_bits_vd_valid = vdec_io_out_0_bits_vd_valid; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_0_bits_vd_addr = vdec_io_out_0_bits_vd_addr; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_0_bits_vs_valid = vdec_io_out_0_bits_vs_valid; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_0_bits_vs_addr = vdec_io_out_0_bits_vs_addr; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_0_bits_vs_tag = vdec_io_out_0_bits_vs_tag; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_0_bits_sv_addr = vdec_io_out_0_bits_sv_addr; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_0_bits_sv_data = vdec_io_out_0_bits_sv_data; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_1_valid = ldstvalid[1]; // @[VCore.scala 203:43]
+ assign vldst_io_in_bits_1_bits_op = vdec_io_out_1_bits_op; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_1_bits_f2 = vdec_io_out_1_bits_f2; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_1_bits_sz = vdec_io_out_1_bits_sz; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_1_bits_m = vdec_io_out_1_bits_m; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_1_bits_vd_valid = vdec_io_out_1_bits_vd_valid; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_1_bits_vd_addr = vdec_io_out_1_bits_vd_addr; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_1_bits_vs_valid = vdec_io_out_1_bits_vs_valid; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_1_bits_vs_addr = vdec_io_out_1_bits_vs_addr; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_1_bits_vs_tag = vdec_io_out_1_bits_vs_tag; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_1_bits_sv_addr = vdec_io_out_1_bits_sv_addr; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_1_bits_sv_data = vdec_io_out_1_bits_sv_data; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_2_valid = ldstvalid[2]; // @[VCore.scala 203:43]
+ assign vldst_io_in_bits_2_bits_op = vdec_io_out_2_bits_op; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_2_bits_f2 = vdec_io_out_2_bits_f2; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_2_bits_sz = vdec_io_out_2_bits_sz; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_2_bits_m = vdec_io_out_2_bits_m; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_2_bits_vd_valid = vdec_io_out_2_bits_vd_valid; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_2_bits_vd_addr = vdec_io_out_2_bits_vd_addr; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_2_bits_vs_valid = vdec_io_out_2_bits_vs_valid; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_2_bits_vs_addr = vdec_io_out_2_bits_vs_addr; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_2_bits_vs_tag = vdec_io_out_2_bits_vs_tag; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_2_bits_sv_addr = vdec_io_out_2_bits_sv_addr; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_2_bits_sv_data = vdec_io_out_2_bits_sv_data; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_3_valid = ldstvalid[3]; // @[VCore.scala 203:43]
+ assign vldst_io_in_bits_3_bits_op = vdec_io_out_3_bits_op; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_3_bits_f2 = vdec_io_out_3_bits_f2; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_3_bits_sz = vdec_io_out_3_bits_sz; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_3_bits_m = vdec_io_out_3_bits_m; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_3_bits_vd_valid = vdec_io_out_3_bits_vd_valid; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_3_bits_vd_addr = vdec_io_out_3_bits_vd_addr; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_3_bits_vs_valid = vdec_io_out_3_bits_vs_valid; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_3_bits_vs_addr = vdec_io_out_3_bits_vs_addr; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_3_bits_vs_tag = vdec_io_out_3_bits_vs_tag; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_3_bits_sv_addr = vdec_io_out_3_bits_sv_addr; // @[VCore.scala 204:30]
+ assign vldst_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 204:30]
+ assign vldst_io_vrfsb = vrf_io_vrfsb_data; // @[VCore.scala 210:18]
+ assign vldst_io_read_ready = ~vst_io_read_valid; // @[VCore.scala 207:26]
+ assign vldst_io_read_data = vrf_io_read_6_data; // @[VCore.scala 208:22]
+ assign vldst_io_dbus_ready = io_dbus_ready; // @[VCore.scala 212:11]
+ assign vldst_io_dbus_rdata = io_dbus_rdata; // @[VCore.scala 212:11]
assign vld_clock = clock;
assign vld_reset = reset;
- assign vld_io_in_valid = ldvalid != 4'h0; // @[VCore.scala 233:30]
- assign vld_io_in_bits_0_valid = ldvalid[0]; // @[VCore.scala 236:39]
- assign vld_io_in_bits_0_bits_op = vdec_io_out_0_bits_op; // @[VCore.scala 237:28]
- assign vld_io_in_bits_0_bits_f2 = vdec_io_out_0_bits_f2; // @[VCore.scala 237:28]
- assign vld_io_in_bits_0_bits_sz = vdec_io_out_0_bits_sz; // @[VCore.scala 237:28]
- assign vld_io_in_bits_0_bits_m = vdec_io_out_0_bits_m; // @[VCore.scala 237:28]
- assign vld_io_in_bits_0_bits_vd_valid = vdec_io_out_0_bits_vd_valid; // @[VCore.scala 237:28]
- assign vld_io_in_bits_0_bits_vd_addr = vdec_io_out_0_bits_vd_addr; // @[VCore.scala 237:28]
- assign vld_io_in_bits_0_bits_vs_valid = vdec_io_out_0_bits_vs_valid; // @[VCore.scala 237:28]
- assign vld_io_in_bits_0_bits_sv_addr = vdec_io_out_0_bits_sv_addr; // @[VCore.scala 237:28]
- assign vld_io_in_bits_0_bits_sv_data = vdec_io_out_0_bits_sv_data; // @[VCore.scala 237:28]
- assign vld_io_in_bits_1_valid = ldvalid[1]; // @[VCore.scala 236:39]
- assign vld_io_in_bits_1_bits_op = vdec_io_out_1_bits_op; // @[VCore.scala 237:28]
- assign vld_io_in_bits_1_bits_f2 = vdec_io_out_1_bits_f2; // @[VCore.scala 237:28]
- assign vld_io_in_bits_1_bits_sz = vdec_io_out_1_bits_sz; // @[VCore.scala 237:28]
- assign vld_io_in_bits_1_bits_m = vdec_io_out_1_bits_m; // @[VCore.scala 237:28]
- assign vld_io_in_bits_1_bits_vd_valid = vdec_io_out_1_bits_vd_valid; // @[VCore.scala 237:28]
- assign vld_io_in_bits_1_bits_vd_addr = vdec_io_out_1_bits_vd_addr; // @[VCore.scala 237:28]
- assign vld_io_in_bits_1_bits_vs_valid = vdec_io_out_1_bits_vs_valid; // @[VCore.scala 237:28]
- assign vld_io_in_bits_1_bits_sv_addr = vdec_io_out_1_bits_sv_addr; // @[VCore.scala 237:28]
- assign vld_io_in_bits_1_bits_sv_data = vdec_io_out_1_bits_sv_data; // @[VCore.scala 237:28]
- assign vld_io_in_bits_2_valid = ldvalid[2]; // @[VCore.scala 236:39]
- assign vld_io_in_bits_2_bits_op = vdec_io_out_2_bits_op; // @[VCore.scala 237:28]
- assign vld_io_in_bits_2_bits_f2 = vdec_io_out_2_bits_f2; // @[VCore.scala 237:28]
- assign vld_io_in_bits_2_bits_sz = vdec_io_out_2_bits_sz; // @[VCore.scala 237:28]
- assign vld_io_in_bits_2_bits_m = vdec_io_out_2_bits_m; // @[VCore.scala 237:28]
- assign vld_io_in_bits_2_bits_vd_valid = vdec_io_out_2_bits_vd_valid; // @[VCore.scala 237:28]
- assign vld_io_in_bits_2_bits_vd_addr = vdec_io_out_2_bits_vd_addr; // @[VCore.scala 237:28]
- assign vld_io_in_bits_2_bits_vs_valid = vdec_io_out_2_bits_vs_valid; // @[VCore.scala 237:28]
- assign vld_io_in_bits_2_bits_sv_addr = vdec_io_out_2_bits_sv_addr; // @[VCore.scala 237:28]
- assign vld_io_in_bits_2_bits_sv_data = vdec_io_out_2_bits_sv_data; // @[VCore.scala 237:28]
- assign vld_io_in_bits_3_valid = ldvalid[3]; // @[VCore.scala 236:39]
- assign vld_io_in_bits_3_bits_op = vdec_io_out_3_bits_op; // @[VCore.scala 237:28]
- assign vld_io_in_bits_3_bits_f2 = vdec_io_out_3_bits_f2; // @[VCore.scala 237:28]
- assign vld_io_in_bits_3_bits_sz = vdec_io_out_3_bits_sz; // @[VCore.scala 237:28]
- assign vld_io_in_bits_3_bits_m = vdec_io_out_3_bits_m; // @[VCore.scala 237:28]
- assign vld_io_in_bits_3_bits_vd_valid = vdec_io_out_3_bits_vd_valid; // @[VCore.scala 237:28]
- assign vld_io_in_bits_3_bits_vd_addr = vdec_io_out_3_bits_vd_addr; // @[VCore.scala 237:28]
- assign vld_io_in_bits_3_bits_vs_valid = vdec_io_out_3_bits_vs_valid; // @[VCore.scala 237:28]
- assign vld_io_in_bits_3_bits_sv_addr = vdec_io_out_3_bits_sv_addr; // @[VCore.scala 237:28]
- assign vld_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 237:28]
- assign vld_io_axi_addr_ready = io_ld_addr_ready; // @[VCore.scala 240:9]
- assign vld_io_axi_data_valid = io_ld_data_valid; // @[VCore.scala 240:9]
- assign vld_io_axi_data_bits_id = io_ld_data_bits_id; // @[VCore.scala 240:9]
- assign vld_io_axi_data_bits_data = io_ld_data_bits_data; // @[VCore.scala 240:9]
+ assign vld_io_in_valid = ldvalid != 4'h0; // @[VCore.scala 230:30]
+ assign vld_io_in_bits_0_valid = ldvalid[0]; // @[VCore.scala 233:39]
+ assign vld_io_in_bits_0_bits_op = vdec_io_out_0_bits_op; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_0_bits_f2 = vdec_io_out_0_bits_f2; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_0_bits_sz = vdec_io_out_0_bits_sz; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_0_bits_m = vdec_io_out_0_bits_m; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_0_bits_vd_valid = vdec_io_out_0_bits_vd_valid; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_0_bits_vd_addr = vdec_io_out_0_bits_vd_addr; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_0_bits_vs_valid = vdec_io_out_0_bits_vs_valid; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_0_bits_sv_addr = vdec_io_out_0_bits_sv_addr; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_0_bits_sv_data = vdec_io_out_0_bits_sv_data; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_1_valid = ldvalid[1]; // @[VCore.scala 233:39]
+ assign vld_io_in_bits_1_bits_op = vdec_io_out_1_bits_op; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_1_bits_f2 = vdec_io_out_1_bits_f2; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_1_bits_sz = vdec_io_out_1_bits_sz; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_1_bits_m = vdec_io_out_1_bits_m; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_1_bits_vd_valid = vdec_io_out_1_bits_vd_valid; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_1_bits_vd_addr = vdec_io_out_1_bits_vd_addr; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_1_bits_vs_valid = vdec_io_out_1_bits_vs_valid; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_1_bits_sv_addr = vdec_io_out_1_bits_sv_addr; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_1_bits_sv_data = vdec_io_out_1_bits_sv_data; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_2_valid = ldvalid[2]; // @[VCore.scala 233:39]
+ assign vld_io_in_bits_2_bits_op = vdec_io_out_2_bits_op; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_2_bits_f2 = vdec_io_out_2_bits_f2; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_2_bits_sz = vdec_io_out_2_bits_sz; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_2_bits_m = vdec_io_out_2_bits_m; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_2_bits_vd_valid = vdec_io_out_2_bits_vd_valid; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_2_bits_vd_addr = vdec_io_out_2_bits_vd_addr; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_2_bits_vs_valid = vdec_io_out_2_bits_vs_valid; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_2_bits_sv_addr = vdec_io_out_2_bits_sv_addr; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_2_bits_sv_data = vdec_io_out_2_bits_sv_data; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_3_valid = ldvalid[3]; // @[VCore.scala 233:39]
+ assign vld_io_in_bits_3_bits_op = vdec_io_out_3_bits_op; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_3_bits_f2 = vdec_io_out_3_bits_f2; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_3_bits_sz = vdec_io_out_3_bits_sz; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_3_bits_m = vdec_io_out_3_bits_m; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_3_bits_vd_valid = vdec_io_out_3_bits_vd_valid; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_3_bits_vd_addr = vdec_io_out_3_bits_vd_addr; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_3_bits_vs_valid = vdec_io_out_3_bits_vs_valid; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_3_bits_sv_addr = vdec_io_out_3_bits_sv_addr; // @[VCore.scala 234:28]
+ assign vld_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 234:28]
+ assign vld_io_axi_addr_ready = io_ld_addr_ready; // @[VCore.scala 237:9]
+ assign vld_io_axi_data_valid = io_ld_data_valid; // @[VCore.scala 237:9]
+ assign vld_io_axi_data_bits_id = io_ld_data_bits_id; // @[VCore.scala 237:9]
+ assign vld_io_axi_data_bits_data = io_ld_data_bits_data; // @[VCore.scala 237:9]
assign vst_clock = clock;
assign vst_reset = reset;
- assign vst_io_in_valid = stvalid != 4'h0; // @[VCore.scala 257:30]
- assign vst_io_in_bits_0_valid = stvalid[0]; // @[VCore.scala 260:39]
- assign vst_io_in_bits_0_bits_op = vdec_io_out_0_bits_op; // @[VCore.scala 261:28]
- assign vst_io_in_bits_0_bits_f2 = vdec_io_out_0_bits_f2; // @[VCore.scala 261:28]
- assign vst_io_in_bits_0_bits_sz = vdec_io_out_0_bits_sz; // @[VCore.scala 261:28]
- assign vst_io_in_bits_0_bits_m = vdec_io_out_0_bits_m; // @[VCore.scala 261:28]
- assign vst_io_in_bits_0_bits_vs_valid = vdec_io_out_0_bits_vs_valid; // @[VCore.scala 261:28]
- assign vst_io_in_bits_0_bits_vs_addr = vdec_io_out_0_bits_vs_addr; // @[VCore.scala 261:28]
- assign vst_io_in_bits_0_bits_vs_tag = vdec_io_out_0_bits_vs_tag; // @[VCore.scala 261:28]
- assign vst_io_in_bits_0_bits_sv_addr = vdec_io_out_0_bits_sv_addr; // @[VCore.scala 261:28]
- assign vst_io_in_bits_0_bits_sv_data = vdec_io_out_0_bits_sv_data; // @[VCore.scala 261:28]
- assign vst_io_in_bits_1_valid = stvalid[1]; // @[VCore.scala 260:39]
- assign vst_io_in_bits_1_bits_op = vdec_io_out_1_bits_op; // @[VCore.scala 261:28]
- assign vst_io_in_bits_1_bits_f2 = vdec_io_out_1_bits_f2; // @[VCore.scala 261:28]
- assign vst_io_in_bits_1_bits_sz = vdec_io_out_1_bits_sz; // @[VCore.scala 261:28]
- assign vst_io_in_bits_1_bits_m = vdec_io_out_1_bits_m; // @[VCore.scala 261:28]
- assign vst_io_in_bits_1_bits_vs_valid = vdec_io_out_1_bits_vs_valid; // @[VCore.scala 261:28]
- assign vst_io_in_bits_1_bits_vs_addr = vdec_io_out_1_bits_vs_addr; // @[VCore.scala 261:28]
- assign vst_io_in_bits_1_bits_vs_tag = vdec_io_out_1_bits_vs_tag; // @[VCore.scala 261:28]
- assign vst_io_in_bits_1_bits_sv_addr = vdec_io_out_1_bits_sv_addr; // @[VCore.scala 261:28]
- assign vst_io_in_bits_1_bits_sv_data = vdec_io_out_1_bits_sv_data; // @[VCore.scala 261:28]
- assign vst_io_in_bits_2_valid = stvalid[2]; // @[VCore.scala 260:39]
- assign vst_io_in_bits_2_bits_op = vdec_io_out_2_bits_op; // @[VCore.scala 261:28]
- assign vst_io_in_bits_2_bits_f2 = vdec_io_out_2_bits_f2; // @[VCore.scala 261:28]
- assign vst_io_in_bits_2_bits_sz = vdec_io_out_2_bits_sz; // @[VCore.scala 261:28]
- assign vst_io_in_bits_2_bits_m = vdec_io_out_2_bits_m; // @[VCore.scala 261:28]
- assign vst_io_in_bits_2_bits_vs_valid = vdec_io_out_2_bits_vs_valid; // @[VCore.scala 261:28]
- assign vst_io_in_bits_2_bits_vs_addr = vdec_io_out_2_bits_vs_addr; // @[VCore.scala 261:28]
- assign vst_io_in_bits_2_bits_vs_tag = vdec_io_out_2_bits_vs_tag; // @[VCore.scala 261:28]
- assign vst_io_in_bits_2_bits_sv_addr = vdec_io_out_2_bits_sv_addr; // @[VCore.scala 261:28]
- assign vst_io_in_bits_2_bits_sv_data = vdec_io_out_2_bits_sv_data; // @[VCore.scala 261:28]
- assign vst_io_in_bits_3_valid = stvalid[3]; // @[VCore.scala 260:39]
- assign vst_io_in_bits_3_bits_op = vdec_io_out_3_bits_op; // @[VCore.scala 261:28]
- assign vst_io_in_bits_3_bits_f2 = vdec_io_out_3_bits_f2; // @[VCore.scala 261:28]
- assign vst_io_in_bits_3_bits_sz = vdec_io_out_3_bits_sz; // @[VCore.scala 261:28]
- assign vst_io_in_bits_3_bits_m = vdec_io_out_3_bits_m; // @[VCore.scala 261:28]
- assign vst_io_in_bits_3_bits_vs_valid = vdec_io_out_3_bits_vs_valid; // @[VCore.scala 261:28]
- assign vst_io_in_bits_3_bits_vs_addr = vdec_io_out_3_bits_vs_addr; // @[VCore.scala 261:28]
- assign vst_io_in_bits_3_bits_vs_tag = vdec_io_out_3_bits_vs_tag; // @[VCore.scala 261:28]
- assign vst_io_in_bits_3_bits_sv_addr = vdec_io_out_3_bits_sv_addr; // @[VCore.scala 261:28]
- assign vst_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 261:28]
- assign vst_io_vrfsb = vrf_io_vrfsb_data; // @[VCore.scala 266:16]
- assign vst_io_read_ready = 1'h1; // @[VCore.scala 268:21]
- assign vst_io_read_data = vrf_io_read_6_data; // @[VCore.scala 269:20]
- assign vst_io_axi_addr_ready = io_st_addr_ready; // @[VCore.scala 264:9]
- assign vst_io_axi_data_ready = io_st_data_ready; // @[VCore.scala 264:9]
- assign vst_io_axi_resp_valid = io_st_resp_valid; // @[VCore.scala 264:9]
+ assign vst_io_in_valid = stvalid != 4'h0; // @[VCore.scala 254:30]
+ assign vst_io_in_bits_0_valid = stvalid[0]; // @[VCore.scala 257:39]
+ assign vst_io_in_bits_0_bits_op = vdec_io_out_0_bits_op; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_0_bits_f2 = vdec_io_out_0_bits_f2; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_0_bits_sz = vdec_io_out_0_bits_sz; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_0_bits_m = vdec_io_out_0_bits_m; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_0_bits_vs_valid = vdec_io_out_0_bits_vs_valid; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_0_bits_vs_addr = vdec_io_out_0_bits_vs_addr; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_0_bits_vs_tag = vdec_io_out_0_bits_vs_tag; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_0_bits_sv_addr = vdec_io_out_0_bits_sv_addr; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_0_bits_sv_data = vdec_io_out_0_bits_sv_data; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_1_valid = stvalid[1]; // @[VCore.scala 257:39]
+ assign vst_io_in_bits_1_bits_op = vdec_io_out_1_bits_op; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_1_bits_f2 = vdec_io_out_1_bits_f2; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_1_bits_sz = vdec_io_out_1_bits_sz; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_1_bits_m = vdec_io_out_1_bits_m; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_1_bits_vs_valid = vdec_io_out_1_bits_vs_valid; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_1_bits_vs_addr = vdec_io_out_1_bits_vs_addr; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_1_bits_vs_tag = vdec_io_out_1_bits_vs_tag; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_1_bits_sv_addr = vdec_io_out_1_bits_sv_addr; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_1_bits_sv_data = vdec_io_out_1_bits_sv_data; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_2_valid = stvalid[2]; // @[VCore.scala 257:39]
+ assign vst_io_in_bits_2_bits_op = vdec_io_out_2_bits_op; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_2_bits_f2 = vdec_io_out_2_bits_f2; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_2_bits_sz = vdec_io_out_2_bits_sz; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_2_bits_m = vdec_io_out_2_bits_m; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_2_bits_vs_valid = vdec_io_out_2_bits_vs_valid; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_2_bits_vs_addr = vdec_io_out_2_bits_vs_addr; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_2_bits_vs_tag = vdec_io_out_2_bits_vs_tag; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_2_bits_sv_addr = vdec_io_out_2_bits_sv_addr; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_2_bits_sv_data = vdec_io_out_2_bits_sv_data; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_3_valid = stvalid[3]; // @[VCore.scala 257:39]
+ assign vst_io_in_bits_3_bits_op = vdec_io_out_3_bits_op; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_3_bits_f2 = vdec_io_out_3_bits_f2; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_3_bits_sz = vdec_io_out_3_bits_sz; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_3_bits_m = vdec_io_out_3_bits_m; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_3_bits_vs_valid = vdec_io_out_3_bits_vs_valid; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_3_bits_vs_addr = vdec_io_out_3_bits_vs_addr; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_3_bits_vs_tag = vdec_io_out_3_bits_vs_tag; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_3_bits_sv_addr = vdec_io_out_3_bits_sv_addr; // @[VCore.scala 258:28]
+ assign vst_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 258:28]
+ assign vst_io_vrfsb = vrf_io_vrfsb_data; // @[VCore.scala 263:16]
+ assign vst_io_read_ready = 1'h1; // @[VCore.scala 265:21]
+ assign vst_io_read_data = vrf_io_read_6_data; // @[VCore.scala 266:20]
+ assign vst_io_axi_addr_ready = io_st_addr_ready; // @[VCore.scala 261:9]
+ assign vst_io_axi_data_ready = io_st_data_ready; // @[VCore.scala 261:9]
+ assign vst_io_axi_resp_valid = io_st_resp_valid; // @[VCore.scala 261:9]
assign vrf_clock = clock;
assign vrf_reset = reset;
assign vrf_io_read_0_valid = valu_io_read_0_valid; // @[VCore.scala 140:26]
@@ -123414,12 +123226,12 @@
assign vrf_io_read_4_addr = valu_io_read_4_addr; // @[VCore.scala 141:25]
assign vrf_io_read_5_valid = valu_io_read_5_valid; // @[VCore.scala 140:26]
assign vrf_io_read_5_addr = valu_io_read_5_addr; // @[VCore.scala 141:25]
- assign vrf_io_read_6_valid = vst_io_read_valid | vldst_io_read_valid; // @[VCore.scala 283:45]
- assign vrf_io_read_6_addr = vst_io_read_valid ? vst_io_read_addr : vldst_io_read_addr; // @[VCore.scala 284:29]
- assign vrf_io_scalar_0_valid = valu_io_scalar_0_valid; // @[VCore.scala 162:28]
- assign vrf_io_scalar_0_data = valu_io_scalar_0_data; // @[VCore.scala 163:27]
- assign vrf_io_scalar_1_valid = valu_io_scalar_1_valid; // @[VCore.scala 162:28]
- assign vrf_io_scalar_1_data = valu_io_scalar_1_data; // @[VCore.scala 163:27]
+ assign vrf_io_read_6_valid = vst_io_read_valid | vldst_io_read_valid; // @[VCore.scala 280:45]
+ assign vrf_io_read_6_addr = vst_io_read_valid ? vst_io_read_addr : vldst_io_read_addr; // @[VCore.scala 281:29]
+ assign vrf_io_scalar_0_valid = valu_io_scalar_0_valid; // @[VCore.scala 159:28]
+ assign vrf_io_scalar_0_data = valu_io_scalar_0_data; // @[VCore.scala 160:27]
+ assign vrf_io_scalar_1_valid = valu_io_scalar_1_valid; // @[VCore.scala 159:28]
+ assign vrf_io_scalar_1_data = valu_io_scalar_1_data; // @[VCore.scala 160:27]
assign vrf_io_write_0_valid = valu_io_write_0_valid; // @[VCore.scala 150:27]
assign vrf_io_write_0_addr = valu_io_write_0_addr; // @[VCore.scala 151:26]
assign vrf_io_write_0_data = valu_io_write_0_data; // @[VCore.scala 152:26]
@@ -123432,12 +123244,12 @@
assign vrf_io_write_3_valid = valu_io_write_3_valid; // @[VCore.scala 150:27]
assign vrf_io_write_3_addr = valu_io_write_3_addr; // @[VCore.scala 151:26]
assign vrf_io_write_3_data = valu_io_write_3_data; // @[VCore.scala 152:26]
- assign vrf_io_write_4_valid = vldst_io_write_valid; // @[VCore.scala 273:25]
- assign vrf_io_write_4_addr = vldst_io_write_addr; // @[VCore.scala 274:24]
- assign vrf_io_write_4_data = vldst_io_write_data; // @[VCore.scala 275:24]
- assign vrf_io_write_5_valid = vld_io_write_valid; // @[VCore.scala 277:25]
- assign vrf_io_write_5_addr = vld_io_write_addr; // @[VCore.scala 278:24]
- assign vrf_io_write_5_data = vld_io_write_data; // @[VCore.scala 279:24]
+ assign vrf_io_write_4_valid = vldst_io_write_valid; // @[VCore.scala 270:25]
+ assign vrf_io_write_4_addr = vldst_io_write_addr; // @[VCore.scala 271:24]
+ assign vrf_io_write_4_data = vldst_io_write_data; // @[VCore.scala 272:24]
+ assign vrf_io_write_5_valid = vld_io_write_valid; // @[VCore.scala 274:25]
+ assign vrf_io_write_5_addr = vld_io_write_addr; // @[VCore.scala 275:24]
+ assign vrf_io_write_5_data = vld_io_write_data; // @[VCore.scala 276:24]
assign vrf_io_whint_0_valid = valu_io_whint_0_valid; // @[VCore.scala 154:27]
assign vrf_io_whint_0_addr = valu_io_whint_0_addr; // @[VCore.scala 155:26]
assign vrf_io_whint_1_valid = valu_io_whint_1_valid; // @[VCore.scala 154:27]
@@ -123446,20 +123258,20 @@
assign vrf_io_whint_2_addr = valu_io_whint_2_addr; // @[VCore.scala 155:26]
assign vrf_io_whint_3_valid = valu_io_whint_3_valid; // @[VCore.scala 154:27]
assign vrf_io_whint_3_addr = valu_io_whint_3_addr; // @[VCore.scala 155:26]
- assign vrf_io_conv_valid = vconv_io_out_valid; // @[VCore.scala 187:15]
- assign vrf_io_conv_ready = vconv_io_out_ready; // @[VCore.scala 187:15]
- assign vrf_io_conv_op_conv = vconv_io_out_op_conv; // @[VCore.scala 187:15]
- assign vrf_io_conv_op_init = vconv_io_out_op_init; // @[VCore.scala 187:15]
- assign vrf_io_conv_op_tran = vconv_io_out_op_tran; // @[VCore.scala 187:15]
- assign vrf_io_conv_op_wclr = vconv_io_out_op_wclr; // @[VCore.scala 187:15]
- assign vrf_io_conv_addr1 = vconv_io_out_addr1; // @[VCore.scala 187:15]
- assign vrf_io_conv_addr2 = vconv_io_out_addr2; // @[VCore.scala 187:15]
- assign vrf_io_conv_mode = vconv_io_out_mode; // @[VCore.scala 187:15]
- assign vrf_io_conv_index = vconv_io_out_index; // @[VCore.scala 187:15]
- assign vrf_io_conv_abias = vconv_io_out_abias; // @[VCore.scala 187:15]
- assign vrf_io_conv_bbias = vconv_io_out_bbias; // @[VCore.scala 187:15]
- assign vrf_io_conv_asign = vconv_io_out_asign; // @[VCore.scala 187:15]
- assign vrf_io_conv_bsign = vconv_io_out_bsign; // @[VCore.scala 187:15]
+ assign vrf_io_conv_valid = vconv_io_out_valid; // @[VCore.scala 184:15]
+ assign vrf_io_conv_ready = vconv_io_out_ready; // @[VCore.scala 184:15]
+ assign vrf_io_conv_op_conv = vconv_io_out_op_conv; // @[VCore.scala 184:15]
+ assign vrf_io_conv_op_init = vconv_io_out_op_init; // @[VCore.scala 184:15]
+ assign vrf_io_conv_op_tran = vconv_io_out_op_tran; // @[VCore.scala 184:15]
+ assign vrf_io_conv_op_wclr = vconv_io_out_op_wclr; // @[VCore.scala 184:15]
+ assign vrf_io_conv_addr1 = vconv_io_out_addr1; // @[VCore.scala 184:15]
+ assign vrf_io_conv_addr2 = vconv_io_out_addr2; // @[VCore.scala 184:15]
+ assign vrf_io_conv_mode = vconv_io_out_mode; // @[VCore.scala 184:15]
+ assign vrf_io_conv_index = vconv_io_out_index; // @[VCore.scala 184:15]
+ assign vrf_io_conv_abias = vconv_io_out_abias; // @[VCore.scala 184:15]
+ assign vrf_io_conv_bbias = vconv_io_out_bbias; // @[VCore.scala 184:15]
+ assign vrf_io_conv_asign = vconv_io_out_asign; // @[VCore.scala 184:15]
+ assign vrf_io_conv_bsign = vconv_io_out_bsign; // @[VCore.scala 184:15]
assign vrf_io_vrfsb_set_valid = vdec_io_vrfsb_set_valid; // @[VCore.scala 76:17]
assign vrf_io_vrfsb_set_bits = vdec_io_vrfsb_set_bits; // @[VCore.scala 76:17]
always @(posedge clock) begin
@@ -206508,41 +206320,41 @@
wire [1:0] _opos_T_1 = opos + 2'h1; // @[Slice.scala 39:18]
wire full = ipos[0] == opos[0] & ipos[1] != opos[1]; // @[Slice.scala 47:36]
wire _io_in_ready_T = ~full; // @[Slice.scala 51:22]
- wire _T_3 = ivalid & ~ovalid; // @[Slice.scala 77:18]
- wire _T_5 = ivalid & ovalid; // @[Slice.scala 78:18]
- wire _T_7 = ivalid & ovalid & _io_in_ready_T; // @[Slice.scala 78:28]
- wire _T_8 = ivalid & ~ovalid & empty | _T_7; // @[Slice.scala 77:38]
- wire _T_14 = _T_5 & full; // @[Slice.scala 83:28]
- wire _T_15 = _T_3 & ~empty | _T_14; // @[Slice.scala 82:39]
+ wire _T_3 = ivalid & ~ovalid; // @[Slice.scala 58:18]
+ wire _T_5 = ivalid & ovalid; // @[Slice.scala 59:18]
+ wire _T_7 = ivalid & ovalid & _io_in_ready_T; // @[Slice.scala 59:28]
+ wire _T_8 = ivalid & ~ovalid & empty | _T_7; // @[Slice.scala 58:38]
+ wire _T_14 = _T_5 & full; // @[Slice.scala 64:28]
+ wire _T_15 = _T_3 & ~empty | _T_14; // @[Slice.scala 63:39]
assign io_in_ready = ~full; // @[Slice.scala 51:22]
- assign io_out_valid = ~empty; // @[Slice.scala 107:21]
- assign io_out_bits_cwrite = mem_0_cwrite; // @[Slice.scala 108:18]
- assign io_out_bits_caddr = mem_0_caddr; // @[Slice.scala 108:18]
- assign io_out_bits_cid = mem_0_cid; // @[Slice.scala 108:18]
+ assign io_out_valid = ~empty; // @[Slice.scala 88:21]
+ assign io_out_bits_cwrite = mem_0_cwrite; // @[Slice.scala 89:18]
+ assign io_out_bits_caddr = mem_0_caddr; // @[Slice.scala 89:18]
+ assign io_out_bits_cid = mem_0_cid; // @[Slice.scala 89:18]
always @(posedge clock) begin
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_cwrite <= io_in_bits_cwrite; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_cwrite <= mem_1_cwrite; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_cwrite <= io_in_bits_cwrite; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_cwrite <= mem_1_cwrite; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_caddr <= io_in_bits_caddr; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_caddr <= mem_1_caddr; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_caddr <= io_in_bits_caddr; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_caddr <= mem_1_caddr; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_cid <= io_in_bits_cid; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_cid <= mem_1_cid; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_cid <= io_in_bits_cid; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_cid <= mem_1_cid; // @[Slice.scala 55:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_cwrite <= io_in_bits_cwrite; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_cwrite <= io_in_bits_cwrite; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_caddr <= io_in_bits_caddr; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_caddr <= io_in_bits_caddr; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_cid <= io_in_bits_cid; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_cid <= io_in_bits_cid; // @[Slice.scala 65:14]
end
end
always @(posedge clock or posedge reset) begin
@@ -206658,32 +206470,32 @@
wire [1:0] _opos_T_1 = opos + 2'h1; // @[Slice.scala 39:18]
wire full = ipos[0] == opos[0] & ipos[1] != opos[1]; // @[Slice.scala 47:36]
wire _io_in_ready_T = ~full; // @[Slice.scala 51:22]
- wire _T_3 = ivalid & ~ovalid; // @[Slice.scala 77:18]
- wire _T_5 = ivalid & ovalid; // @[Slice.scala 78:18]
- wire _T_7 = ivalid & ovalid & _io_in_ready_T; // @[Slice.scala 78:28]
- wire _T_8 = ivalid & ~ovalid & empty | _T_7; // @[Slice.scala 77:38]
- wire _T_14 = _T_5 & full; // @[Slice.scala 83:28]
- wire _T_15 = _T_3 & ~empty | _T_14; // @[Slice.scala 82:39]
+ wire _T_3 = ivalid & ~ovalid; // @[Slice.scala 58:18]
+ wire _T_5 = ivalid & ovalid; // @[Slice.scala 59:18]
+ wire _T_7 = ivalid & ovalid & _io_in_ready_T; // @[Slice.scala 59:28]
+ wire _T_8 = ivalid & ~ovalid & empty | _T_7; // @[Slice.scala 58:38]
+ wire _T_14 = _T_5 & full; // @[Slice.scala 64:28]
+ wire _T_15 = _T_3 & ~empty | _T_14; // @[Slice.scala 63:39]
assign io_in_ready = ~full; // @[Slice.scala 51:22]
- assign io_out_valid = ~empty; // @[Slice.scala 107:21]
- assign io_out_bits_wdata = mem_0_wdata; // @[Slice.scala 108:18]
- assign io_out_bits_wmask = mem_0_wmask; // @[Slice.scala 108:18]
+ assign io_out_valid = ~empty; // @[Slice.scala 88:21]
+ assign io_out_bits_wdata = mem_0_wdata; // @[Slice.scala 89:18]
+ assign io_out_bits_wmask = mem_0_wmask; // @[Slice.scala 89:18]
always @(posedge clock) begin
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_wdata <= io_in_bits_wdata; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_wdata <= mem_1_wdata; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_wdata <= io_in_bits_wdata; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_wdata <= mem_1_wdata; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_wmask <= io_in_bits_wmask; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_wmask <= mem_1_wmask; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_wmask <= io_in_bits_wmask; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_wmask <= mem_1_wmask; // @[Slice.scala 55:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_wdata <= io_in_bits_wdata; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_wdata <= io_in_bits_wdata; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_wmask <= io_in_bits_wmask; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_wmask <= io_in_bits_wmask; // @[Slice.scala 65:14]
end
end
always @(posedge clock or posedge reset) begin
@@ -206795,32 +206607,32 @@
wire [1:0] _opos_T_1 = opos + 2'h1; // @[Slice.scala 39:18]
wire full = ipos[0] == opos[0] & ipos[1] != opos[1]; // @[Slice.scala 47:36]
wire _io_in_ready_T = ~full; // @[Slice.scala 51:22]
- wire _T_3 = ivalid & ~ovalid; // @[Slice.scala 77:18]
- wire _T_5 = ivalid & ovalid; // @[Slice.scala 78:18]
- wire _T_7 = ivalid & ovalid & _io_in_ready_T; // @[Slice.scala 78:28]
- wire _T_8 = ivalid & ~ovalid & empty | _T_7; // @[Slice.scala 77:38]
- wire _T_14 = _T_5 & full; // @[Slice.scala 83:28]
- wire _T_15 = _T_3 & ~empty | _T_14; // @[Slice.scala 82:39]
+ wire _T_3 = ivalid & ~ovalid; // @[Slice.scala 58:18]
+ wire _T_5 = ivalid & ovalid; // @[Slice.scala 59:18]
+ wire _T_7 = ivalid & ovalid & _io_in_ready_T; // @[Slice.scala 59:28]
+ wire _T_8 = ivalid & ~ovalid & empty | _T_7; // @[Slice.scala 58:38]
+ wire _T_14 = _T_5 & full; // @[Slice.scala 64:28]
+ wire _T_15 = _T_3 & ~empty | _T_14; // @[Slice.scala 63:39]
assign io_in_ready = ~full; // @[Slice.scala 51:22]
- assign io_out_valid = ~empty; // @[Slice.scala 107:21]
- assign io_out_bits_rid = mem_0_rid; // @[Slice.scala 108:18]
- assign io_out_bits_rdata = mem_0_rdata; // @[Slice.scala 108:18]
+ assign io_out_valid = ~empty; // @[Slice.scala 88:21]
+ assign io_out_bits_rid = mem_0_rid; // @[Slice.scala 89:18]
+ assign io_out_bits_rdata = mem_0_rdata; // @[Slice.scala 89:18]
always @(posedge clock) begin
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_rid <= io_in_bits_rid; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_rid <= mem_1_rid; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_rid <= io_in_bits_rid; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_rid <= mem_1_rid; // @[Slice.scala 55:14]
end
- if (_T_8) begin // @[Slice.scala 78:38]
- mem_0_rdata <= io_in_bits_rdata; // @[Slice.scala 79:14]
- end else if (ovalid & full) begin // @[Slice.scala 73:27]
- mem_0_rdata <= mem_1_rdata; // @[Slice.scala 74:14]
+ if (_T_8) begin // @[Slice.scala 59:38]
+ mem_0_rdata <= io_in_bits_rdata; // @[Slice.scala 60:14]
+ end else if (ovalid & full) begin // @[Slice.scala 54:27]
+ mem_0_rdata <= mem_1_rdata; // @[Slice.scala 55:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_rid <= io_in_bits_rid; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_rid <= io_in_bits_rid; // @[Slice.scala 65:14]
end
- if (_T_15) begin // @[Slice.scala 83:37]
- mem_1_rdata <= io_in_bits_rdata; // @[Slice.scala 84:14]
+ if (_T_15) begin // @[Slice.scala 64:37]
+ mem_1_rdata <= io_in_bits_rdata; // @[Slice.scala 65:14]
end
end
always @(posedge clock or posedge reset) begin
diff --git a/rules/matcha.bzl b/rules/matcha.bzl
index 71a430d..87b4594 100644
--- a/rules/matcha.bzl
+++ b/rules/matcha.bzl
@@ -38,6 +38,11 @@
"smc": "//sw/device/lib/arch:smc_sim_verilator",
}
+DV_CORE_TARGETS = {
+ "secure_core": "@lowrisc_opentitan//sw/device/lib/arch:sim_dv",
+ "smc": "//sw/device/lib/arch:smc_sim_dv",
+}
+
NEXUS_CORE_TARGETS = {
"secure_core": "//sw/device/lib/arch:sc_fpga_nexus",
"smc": "//sw/device/lib/arch:smc_fpga_nexus",
@@ -50,7 +55,7 @@
def device_deps(core):
per_device_deps = {
"sim_verilator": [VERILATOR_CORE_TARGETS.get(core)],
- "sim_dv": ["@lowrisc_opentitan//sw/device/lib/arch:sim_dv"],
+ "sim_dv": [DV_CORE_TARGETS.get(core)],
"fpga_nexus": [NEXUS_CORE_TARGETS.get(core)],
}
return per_device_deps
diff --git a/rules/matcha_test.bzl b/rules/matcha_test.bzl
index 5d791bf..f24991f 100644
--- a/rules/matcha_test.bzl
+++ b/rules/matcha_test.bzl
@@ -14,7 +14,12 @@
"""Rules to build matcha test targets"""
-load("//rules:matcha.bzl", "flash_binary", "opentitan_rom_binary")
+load(
+ "//rules:matcha.bzl",
+ "DV_CORE_TARGETS",
+ "flash_binary",
+ "opentitan_rom_binary",
+)
def matcha_verilator_test(
name,
@@ -56,7 +61,7 @@
sh_test_tags = ["verilator"] + tags
sh_test_runner = "@//util:run_chip_verilator_sim.sh"
sh_test_args = [
- "$(locations %s)" % (verilator_testbench),
+ "$(location %s)" % (verilator_testbench),
"$(location %s)" % (rom_img),
"$(location %s)" % (sec_verilator_binary),
"$(location %s)" % (otp_img),
@@ -168,6 +173,8 @@
signed = False,
dv = None,
test_binary = None,
+ per_device_deps = {"sim_dv": [DV_CORE_TARGETS.get("secure_core")]},
+ word_size = 64,
**kwargs):
"""A helper macro for generating Matcha functional tests.
@@ -188,6 +195,9 @@
signed: Whether to sign the test image. Unsigned by default.
dv: DV test parameters.
test_binary: Use the named binary as the test program rather than building one from srcs/deps.
+ per_device_deps: Target deps that are forwared to flash_binary. Default to build for secure
+ core DV only.
+ word_size: The word size that is forwared to flash_binary. Default to 64 for secure core.
**kwargs: Arguments to forward to `flash_binary`.
This macro emits the following rules:
@@ -208,7 +218,8 @@
flash_binary(
name = test_binary,
signed = signed,
- word_size = 64,
+ per_device_deps = per_device_deps,
+ word_size = word_size,
deps = deps,
**kwargs
)
diff --git a/sw/device/examples/hello_world/BUILD b/sw/device/examples/hello_world/BUILD
index 00ddb67..fa9fce8 100644
--- a/sw/device/examples/hello_world/BUILD
+++ b/sw/device/examples/hello_world/BUILD
@@ -42,3 +42,26 @@
"@lowrisc_opentitan//sw/device/silicon_creator/lib:manifest_def",
],
)
+
+# Use shell test to run the interactive verilator test on UART and GPIO
+sh_test(
+ name = "verilator_hello_world_test",
+ timeout = "long",
+ srcs = [":run_verilator_hello_world.sh"],
+ args = [
+ "$(location //hw:verilator)",
+ "$(location //sw/device/lib/testing/test_rom:test_rom_sim_verilator_scr_vmem)",
+ "$(location :hello_world_sim_verilator_vmem)",
+ "$(location //hw/top_matcha/data:otp_img_rma)",
+ ],
+ data = [
+ ":hello_world_sim_verilator_vmem",
+ ":hello_world_test_expected_gpio.txt",
+ "//hw:verilator",
+ "//hw/top_matcha/data:otp_img_rma",
+ "//sw/device/lib/testing/test_rom:test_rom_sim_verilator_scr_vmem",
+ ],
+ tags = [
+ "verilator",
+ ],
+)
diff --git a/sw/device/examples/hello_world/hello_world_test_expected_gpio.txt b/sw/device/examples/hello_world/hello_world_test_expected_gpio.txt
new file mode 100644
index 0000000..4617c93
--- /dev/null
+++ b/sw/device/examples/hello_world/hello_world_test_expected_gpio.txt
@@ -0,0 +1,16 @@
+XXXXXXXXXXXXXXXX1111111111111111
+XXXXXXXXXXXXXXXX0000000000000000
+XXXXXXXXXXXXXXXX0110110001101100
+XXXXXXXXXXXXXXXX0110010101100101
+XXXXXXXXXXXXXXXX0110010001100100
+XXXXXXXXXXXXXXXX0010000000100000
+XXXXXXXXXXXXXXXX0110011101100111
+XXXXXXXXXXXXXXXX0111000001110000
+XXXXXXXXXXXXXXXX0110100101101001
+XXXXXXXXXXXXXXXX0110111101101111
+XXXXXXXXXXXXXXXX0010000000100000
+XXXXXXXXXXXXXXXX0111010001110100
+XXXXXXXXXXXXXXXX0110010101100101
+XXXXXXXXXXXXXXXX0111001101110011
+XXXXXXXXXXXXXXXX0111010001110100
+XXXXXXXXXXXXXXXX0000101000001010
diff --git a/sw/device/examples/hello_world/run_verilator_hello_world.sh b/sw/device/examples/hello_world/run_verilator_hello_world.sh
new file mode 100755
index 0000000..932dbdd
--- /dev/null
+++ b/sw/device/examples/hello_world/run_verilator_hello_world.sh
@@ -0,0 +1,80 @@
+#!/bin/bash
+#
+# Copyright 2023 Google LLC
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Run verilator interactive simulation on sw/device/examples/hello_world.
+
+function print_usage(
+ echo "Usage: run_verilator_hello_world.sh <verilator testbench> <rom binary> <flash binary> <otp binary>"
+)
+
+if [[ $1 == "--help" ]]; then
+ print_usage
+ exit 0
+fi
+
+if [[ $# -ne 4 ]]; then
+ print_usage
+ exit 1
+fi
+
+if [[ -z ${TEST_UNDECLARED_OUTPUTS_DIR} ]]; then
+ echo "The script only works under bazel test"
+ exit 1
+fi
+
+
+TEST_CYCLES=650000
+
+VCHIP_TB=$1
+ROM_BIN=$2
+FLASH_BIN=$3
+OTP_BIN=$4
+
+if [[ ! -f $(realpath ${VCHIP_TB}) ]]; then
+ echo "Verilator testbench not found. Please make sure //hw:verilator is in data."
+ exit 1
+fi
+
+if [[ ! -f $(realpath ${ROM_BIN}) ]] || [[ ! -f $(realpath ${FLASH_BIN}) ]] ||
+ [[ ! -f $(realpath ${OTP_BIN}) ]]; then
+ echo "Software binaries not found. Please make sure the targets are in data and args."
+ exit 1
+fi
+
+# Run verilator testbench in the background
+${VCHIP_TB} \
+ "--meminit=rom,${ROM_BIN}" \
+ "--meminit=flash,${FLASH_BIN}" \
+ "--meminit=otp,${OTP_BIN}" -c "${TEST_CYCLES}" &
+
+VERILATOR_PID=$!
+
+# Pipe GPIO output to a log file
+sleep 5
+cat gpio0-read | tee "${TEST_UNDECLARED_OUTPUTS_DIR}/gpio0_read.log" &
+
+# Wait for 300s to reach the end of the hello_world initialization.
+sleep 300
+echo 'led gpio test' > "${TEST_UNDECLARED_OUTPUTS_DIR}/uart0_device"
+
+# Wait up to another 350s to complete the verilator simulation.
+timeout 350 tail --pid=${VERILATOR_PID} -f /dev/null
+
+# Check results in GPIO and UART logs.
+cat "${TEST_UNDECLARED_OUTPUTS_DIR}/uart0.log" | grep -q "led gpio test" || exit 1
+
+diff -q "${TEST_UNDECLARED_OUTPUTS_DIR}/gpio0_read.log" \
+ "sw/device/examples/hello_world/hello_world_test_expected_gpio.txt" || exit 1
diff --git a/sw/device/lib/arch/BUILD b/sw/device/lib/arch/BUILD
index 172ae85..373534e 100644
--- a/sw/device/lib/arch/BUILD
+++ b/sw/device/lib/arch/BUILD
@@ -11,6 +11,14 @@
)
cc_library(
+ name = "smc_sim_dv",
+ srcs = ["device_smc_sim_dv.c"],
+ deps = [
+ ":device",
+ ],
+)
+
+cc_library(
name = "smc_sim_verilator",
srcs = ["device_smc_sim_verilator.c"],
deps = [
diff --git a/sw/device/lib/arch/device_smc_sim_dv.c b/sw/device/lib/arch/device_smc_sim_dv.c
new file mode 100644
index 0000000..ef7c4ac
--- /dev/null
+++ b/sw/device/lib/arch/device_smc_sim_dv.c
@@ -0,0 +1,49 @@
+// Copyright 2022 Google LLC.
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#include <assert.h>
+#include <stdbool.h>
+
+#include "sw/device/lib/arch/device.h"
+
+/**
+ * @file
+ * @brief Device-specific symbol definitions for the DV device.
+ */
+
+const device_type_t kDeviceType = kDeviceSimDV;
+
+const uint64_t kClockFreqCpuMhz = 100;
+
+const uint64_t kClockFreqCpuHz = kClockFreqCpuMhz * 1000 * 1000;
+
+uint64_t to_cpu_cycles(uint64_t usec) { return usec * kClockFreqCpuMhz; }
+
+const uint64_t kClockFreqHiSpeedPeripheralHz = 96 * 1000 * 1000; // 96MHz
+
+const uint64_t kClockFreqPeripheralHz = 24 * 1000 * 1000; // 24MHz
+
+const uint64_t kClockFreqUsbHz = 48 * 1000 * 1000; // 48MHz
+
+const uint64_t kClockFreqAonHz = 200 * 1000; // 200kHz
+
+const uint64_t kUartBaudrate = 1 * 1000 * 1000; // 1Mbps
+
+const uint32_t kUartNCOValue =
+ CALCULATE_UART_NCO(kUartBaudrate, kClockFreqPeripheralHz);
+
+const uint32_t kUartTxFifoCpuCycles =
+ CALCULATE_UART_TX_FIFO_CPU_CYCLES(kUartBaudrate, kClockFreqCpuHz);
+
+const uint32_t kAstCheckPollCpuCycles =
+ CALCULATE_AST_CHECK_POLL_CPU_CYCLES(kClockFreqCpuHz);
+
+const uintptr_t kDeviceTestStatusAddress = 0x54030080;
+
+const uintptr_t kDeviceLogBypassUartAddress = 0x54030084;
+
+const bool kJitterEnabled = false;
+
+void device_fpga_version_print(void) {}
diff --git a/sw/device/tests/BUILD b/sw/device/tests/BUILD
index ebe30fd..1f7375c 100644
--- a/sw/device/tests/BUILD
+++ b/sw/device/tests/BUILD
@@ -577,6 +577,7 @@
"verilator_supervisor_mode_test",
"verilator_tlul_mailbox_test",
"verilator_virtual_memory_test",
+ "//sw/device/examples/hello_world:verilator_hello_world_test",
"//sw/device/tests/smc:verilator_kelvin_checksum_test",
"//sw/device/tests/smc:verilator_kelvin_hello_test",
"//sw/device/tests/smc:verilator_ml_top_irq_test",
diff --git a/util/run_chip_verilator_sim.sh b/util/run_chip_verilator_sim.sh
index 6358763..7819142 100755
--- a/util/run_chip_verilator_sim.sh
+++ b/util/run_chip_verilator_sim.sh
@@ -21,12 +21,6 @@
exit 0
fi
-# In bazel build the verilator target has multiple outputs, so we need to trim
-# the non-executable one.
-while [[ $1 != *"Vchip_sim_tb" ]]; do
- shift 1
-done
-
VCHIP_TB=$1
ROM_BIN=$2
FLASH_BIN=$3
