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/*
Copyright 2024 Google LLC
Copyright (C) 2019-2022 Antmicro
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
SPDX-License-Identifier: Apache-2.0
*/
package DMAController.DMAConfig
import chisel3._
object DMAConfig {
val addrWidth = 32
val readDataWidth = 32
val writeDataWidth = 32
val readMaxBurst = 0
val writeMaxBurst = 256
val reader4KBarrier = false
val writer4KBarrier = true
val controlDataWidth = 32
val controlAddrWidth = 32
val controlRegCount = 16
val fifoDepth = 512
}