[HW][Kelvin][Sram_1rwm_256x288.v]"ifdef fpga" move

1. Move 2 registers defintion and assign statement inside "ifdef FPGA" branch.
2. It will fix the both VCS and ASIC synthesis reported lint errors.

Change-Id: Ia2e9cb040caa4bc79f6c96d1a27be1388ebed911

hw/top_matcha/ip/ml_top/rtl/Sram_1rwm_256x288.v

diff --git a/hw/top_matcha/ip/ml_top/rtl/Sram_1rwm_256x288.v b/hw/top_matcha/ip/ml_top/rtl/Sram_1rwm_256x288.v
index 2327e3d..610fd94 100644
--- a/hw/top_matcha/ip/ml_top/rtl/Sram_1rwm_256x288.v
+++ b/hw/top_matcha/ip/ml_top/rtl/Sram_1rwm_256x288.v
@@ -9,13 +9,12 @@
   input          volt_sel
 );
 
+`ifdef FPGA
 reg [287:0] mem [0:255];
 reg [7:0] raddr;
 
 assign rdata = mem[raddr];
 
-`ifdef FPGA
-
 always @(posedge clock) begin
   for (int i = 0; i < 32; i++) begin
     if (valid & write & wmask[i]) begin