Merge "[HW][ml_top] Fix lint for undriven inputs."

hw/top_matcha/ip/ml_top/rtl/ml_dmem.sv

diff --git a/hw/top_matcha/ip/ml_top/rtl/ml_dmem.sv b/hw/top_matcha/ip/ml_top/rtl/ml_dmem.sv
index ac1a588..7c71d09 100644
--- a/hw/top_matcha/ip/ml_top/rtl/ml_dmem.sv
+++ b/hw/top_matcha/ip/ml_top/rtl/ml_dmem.sv
@@ -84,6 +84,7 @@
 
   // cfg_en (LSB) is unused in memory module and does not qualify volt_sel
   assign ram_cfg.ram_cfg = { 3'b0, volt_sel_i, 1'b0 };
+  assign ram_cfg.rf_cfg = 5'b0;
 
   // xbar_sram only support Byte-Mask for now. i.e 8 data bits per mask bit.
   assign xbar_wmask_b = {xbar_wmask[248], xbar_wmask[240], xbar_wmask[232], xbar_wmask[224],

hw/top_matcha/ip/ml_top/rtl/ml_top.sv

diff --git a/hw/top_matcha/ip/ml_top/rtl/ml_top.sv b/hw/top_matcha/ip/ml_top/rtl/ml_top.sv
index 3900a48..43e5d2c 100644
--- a/hw/top_matcha/ip/ml_top/rtl/ml_top.sv
+++ b/hw/top_matcha/ip/ml_top/rtl/ml_top.sv
@@ -81,6 +81,16 @@
     hw2reg.error_status.d_mem_disable_access.de = 1'b0;
   end
 
+  assign hw2reg.init_end.valid.d = 1'b0;
+  assign hw2reg.init_end.valid.de = 1'b0;
+  assign hw2reg.init_end.address.d = 22'b0;
+  assign hw2reg.init_end.address.de = 22'b0;
+  assign hw2reg.init_status.init_pending.d = 1'b0;
+  assign hw2reg.init_status.init_pending.de = 1'b0;
+  assign hw2reg.init_status.init_done.d = 1'b0;
+  assign hw2reg.init_status.init_done.de = 1'b0;
+  assign core0_cid[7] = 1'b0;
+
   // ML_top Control
   ml_top_core_reg_top u_reg (
     .clk_i,