sw/device/tests/kelvin/fpga_tests/kelvin_test_sc.c

/*
 * Copyright 2023 Google LLC
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */


#include "hw/ip/ml_top/data/ml_top_regs.h"  // Generated.
#include "hw/top_matcha/sw/autogen/top_matcha.h"
#include "sw/device/lib/arch/device.h"
#include "sw/device/lib/dif/dif_rv_plic.h"
#include "sw/device/lib/dif/dif_smc_ctrl.h"
#include "sw/device/lib/dif/dif_tlul_mailbox.h"
#include "sw/device/lib/dif/dif_uart.h"
#include "sw/device/lib/runtime/irq.h"
#include "sw/device/lib/runtime/print.h"
#include "sw/device/lib/spi_flash.h"
#include "sw/device/lib/testing/test_framework/check.h"
#include "sw/device/lib/testing/test_framework/ottf_test_config.h"
#include "sw/device/lib/testing/test_framework/status.h"
#include "sw/device/lib/testing/test_framework/test_util.h"

/*
 * SC - Initialize SMC, load kelvin program, and print status to UART.
 * SMC - Print to UART and orchestrate ML core/programs.
 */

OTTF_DEFINE_TEST_CONFIG();

static dif_smc_ctrl_t smc_ctrl;
static dif_uart_t uart;
static dif_rv_plic_t plic_sec;
static dif_tlul_mailbox_t tlul_mailbox;

volatile uint32_t message;

void ottf_external_isr(void) {
  dif_rv_plic_irq_id_t plic_irq_id;
  uint32_t rx;
  CHECK_DIF_OK(dif_rv_plic_irq_claim(&plic_sec, kTopMatchaPlicTargetIbex0,
                                     &plic_irq_id));
  CHECK_DIF_OK(
      dif_tlul_mailbox_irq_acknowledge(&tlul_mailbox, kDifTlulMailboxIrqRtirq));
  CHECK_DIF_OK(dif_tlul_mailbox_read_message(&tlul_mailbox, &rx));
  message = rx;
  CHECK_DIF_OK(dif_rv_plic_irq_complete(&plic_sec, kTopMatchaPlicTargetIbex0,
                                        plic_irq_id));
}

void _ottf_main(void) {
  test_status_set(kTestStatusInTest);
  init_uart(TOP_MATCHA_UART0_BASE_ADDR, &uart);
  LOG_INFO("kelvin_test_sc");
  const uintptr_t spi_host_addr = TOP_MATCHA_SPI_HOST0_BASE_ADDR;
  const uintptr_t flash_ctrl_addr = TOP_MATCHA_FLASH_CTRL_CORE_BASE_ADDR;
  const uintptr_t otp_addr = TOP_MATCHA_OTP_CTRL_CORE_BASE_ADDR;
  spi_flash_init(spi_host_addr, flash_ctrl_addr, otp_addr);

  // Copy binary to SMC RAM.
  CHECK_DIF_OK(load_file_from_tar(
      "smc.bin", (void*)TOP_MATCHA_RAM_SMC_BASE_ADDR,
      (TOP_MATCHA_RAM_SMC_BASE_ADDR + TOP_MATCHA_RAM_SMC_SIZE_BYTES)));

  mmio_region_t ml_dmem =
      mmio_region_from_addr(TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR);

  // Fill the memory with zeroes.
  for (int i = 0; i < TOP_MATCHA_ML_TOP_DMEM_SIZE_BYTES / sizeof(uint32_t);
       ++i) {
    mmio_region_write32(ml_dmem, i * sizeof(uint32_t), 0);
  }

  // Setup mailbox.
  CHECK_DIF_OK(dif_tlul_mailbox_init(
      mmio_region_from_addr(TOP_MATCHA_TLUL_MAILBOX_SEC_BASE_ADDR),
      &tlul_mailbox));
  CHECK_DIF_OK(dif_tlul_mailbox_irq_set_enabled(
      &tlul_mailbox, kDifTlulMailboxIrqRtirq, kDifToggleEnabled));
  CHECK_DIF_OK(dif_tlul_mailbox_irq_set_enabled(
      &tlul_mailbox, kDifTlulMailboxIrqWtirq, kDifToggleEnabled));
  CHECK_DIF_OK(dif_tlul_mailbox_irq_set_enabled(
      &tlul_mailbox, kDifTlulMailboxIrqEirq, kDifToggleEnabled));

  // Set Interrupt.
  CHECK_DIF_OK(dif_rv_plic_init(
      mmio_region_from_addr(TOP_MATCHA_RV_PLIC_BASE_ADDR), &plic_sec));
  CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
      &plic_sec, kTopMatchaPlicIrqIdTlulMailboxSecRtirq,
      kTopMatchaPlicTargetIbex0, kDifToggleEnabled));
  CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
      &plic_sec, kTopMatchaPlicIrqIdTlulMailboxSecRtirq, 1));
  irq_global_ctrl(true);
  irq_external_ctrl(true);

  // Enable SMC.
  CHECK_DIF_OK(dif_smc_ctrl_init(
      mmio_region_from_addr(TOP_MATCHA_SMC_CTRL_BASE_ADDR), &smc_ctrl));
  CHECK_DIF_OK(dif_smc_ctrl_set_en(&smc_ctrl));

  // Copy binary to ML_DMEM.
  char kelvin_bin_name[256] = {'\0'};
  size_t bin_offset = 0;
  dif_result_t kelvin_load_result;
  int test_num = 0;
  int failed_test = 0;
  while ((kelvin_load_result = load_file_prefix_from_tar(
              "kelvin_", (void*)TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR,
              (TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR +
               TOP_MATCHA_ML_TOP_DMEM_SIZE_BYTES),
              &bin_offset, kelvin_bin_name, sizeof(kelvin_bin_name))) !=
         kDifOutOfRange) {
    CHECK_DIF_OK(kelvin_load_result, "Failed to load %s", kelvin_bin_name);
    test_num++;
    LOG_INFO("Test %d: Run kelvin binary %s", test_num, kelvin_bin_name);
    uint32_t tx = 0;
    // Send to smc to kickoff ML program
    CHECK_DIF_OK(dif_tlul_mailbox_send_message(&tlul_mailbox, &tx));
    // Wait for mailbox interrupt
    asm volatile("wfi");
    if (message != (1 << ML_TOP_INTR_STATE_FINISH_BIT)) {
      LOG_ERROR("    Test finish with fault");
      failed_test++;
    }
  }
  LOG_INFO("Total test: %d, failed test: %d", test_num, failed_test);
  if (failed_test == 0) {
    test_status_set(kTestStatusPassed);
  } else {
    test_status_set(kTestStatusFailed);
  }
  asm volatile("wfi");
}