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opensecura / hw / matcha / aa7a5c5539edd0913ff61e08180ec9cdd373a3ce
commitaa7a5c5539edd0913ff61e08180ec9cdd373a3ce[log] [tgz]
authorStefan Hall <stefanhall@google.com>Wed Dec 11 18:08:06 2024 -0800
committerStefan Hall <stefanhall@google.com>Fri Jan 17 11:59:15 2025 -0800
tree5e11958e83e53ebaeffd5f26761c59199b8151fb
parent405954e94ffb73ff11073af03113936e453d4a6d [diff]
Generate Complete Matcha Area rpt with DC using OT dvsim tools

Generate Complete Matcha Area rpt with DC using OT dvsim tools

Scripts were written to be compatible with edacloud environment

This CL should be considered an intermediate CL to get the flow in a
state that is running and is not the final state of files in the syn
flow and power flow. Consider evaluating the commented code in
run-syn.tcl to determine the best path forward for constraining the
design.

Files below may not be required at this time, but are part of OT syn
flow and depending on settings used for syn (set in hjson files) they
can be required for syn.
`hw/syn/tools/dc/<filename>`
 - gtech-constraints.sdc :: gtech appear to be google placeholder libraries and
   constraints that seem to allow for quick and dirty synthesis. Not a
   lot of details publicly available but may be something worth looking
   at at some point. Possibly these are used before a technology is
   chosen, for easier 1-1 comparison of projects in different
   technologies, or  or for faster syn.
 - gtech-setup.tcl
 - sweep.tcl     :: Script to do wire-load-model-based sweep syntheses
 - at-plot.py    :: Parse reports from sweep.tcl
 - testsynth.tcl :: Script to do wire-load-model-based test synthesis

Change-Id: I6df1f2fd0433e191a603803dbb1f89f83748b565
11 files changed
tree: 5e11958e83e53ebaeffd5f26761c59199b8151fb
  1. constraints/
  2. doc/
  3. hw/
  4. platforms/
  5. rules/
  6. sw/
  7. third_party/
  8. toolchains/
  9. util/
  10. .bazelrc
  11. .bazelversion
  12. .gitignore
  13. BUILD.bazel
  14. CONTRIBUTING.md
  15. LICENSE
  16. PREUPLOAD.cfg
  17. README.md
  18. WORKSPACE
README.md

Matcha

About the project

Matcha is an open-source reference hardware implementation for Project Open Se Cura, a low-power, secure embedded platform for ambient ML applications.

About this repository

This repository contains hardware (RTL), software, and utilities written as part of the Matcha project.

Documentation

The project contains comprehensive documentation of the SOC, all IPs, and tools.

How to contribute

Have a look at our GettingStarted Guide for guidelines on how to contribute code to this repository.

Licensing

Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).

Prerequisites

Development for matcha requires that the necessary tools and prerequisites be installed. See GettingStarted Guide

To setup the build system, run following steps at root of repo:

source build/setup.sh

Install the prerequisites:

m prereqs

Install the tools used for development:

m tools

Code/Repo Structure

<root_dir>/hw/matcha/
    hw/top_matcha/
        BUILD
        cdc/
        data/
        dv/
        formal/
        ip/
        ip_autogen/
        lint/
        rdc/
        rtl/
        sw/
        syn/
        util/
    hw/
        BUILD
        Makefile
    sw/
        BUILD
        device/
    util/
        BUILD
        dvsim_matcha/
        make_new_dif/
        openocd/
        topgen_util/
        topgen_matcha.py

<root_dir>/hw/opentitan_upstream/
<root_dir>/build/
<root_dir>/Manifest/
<root_dir>/Makefile
<root_dir>/GettingStarted.md
<toot_dir>/...

Quick start guide and cheat sheet

For following steps, make sure the above “Prerequisites” steps have been run if the repo is been checked out at the first time.

Build RTL top Level and generate registers, interrupt and address map:

m matcha_hw_generate_all

Build verilator simulation target:

m matcha_hw_verilator_sim

Run matcha verilator test suite

m matcha_hw_verilator_tests

Run FPGA compilation flow for Nexus FPGA board:

m matcha_hw_fpga_nexus

Bazel debug

Run matcha single test with messages to stdout

bazel test --test_output=streamed //sw/device/tests:verilator_mailbox_test

Run matcha test suites

bazel test --test_output=streamed //sw/device/tests:verilator_test_suite

Run FPGA compilation flow for Nexus FPGA board with debug commands:

bazel build -s //hw/bitstream/vivado:fpga_nexus

Simulation logs

Enable tracing on a single test

bazel test --test_output=streamed  --test_timeout=1000000 --test_arg=--trace //sw/device/tests:verilator_cam_ctrl_test

Note: --test_timeout=1000000 sets timeout in seconds. This helps prevent timeout issues then using trace.

Waveform dump and peripheral logs for a test located in:

<root_dir>/hw/matcha/bazel-testlogs/sw/device/tests/<test_name>/test.outputs/output.zip
    sim.fst (if tracing is enabled)
    uart0.log
    smc_uart.log
    spi0.log
    usb0.log

Note: The trace_core_#.log files available in output.zip is currently a TODO item.

The FPGA compiled bitstream and reports (resource utilization, pin assignment, etc) can be found in following directory:

<matcha_root_dir>/bazel-bin/hw/bitstream/vivado/build.fpga_nexus/synth-vivado/google_systems_chip_matcha_nexus_0.1.runs/impl_1/chip_matcha_nexus.bit <matcha_root_dir>/bazel-bin/hw/bitstream/vivado/build.fpga_nexus/synth-vivado/google_systems_chip_matcha_nexus_0.1.runs/impl_1/.rpt <matcha_root_dir>/bazel-bin/hw/bitstream/vivado/build.fpga_nexus/synth-vivado/google_systems_chip_matcha_nexus_0.1.runs/synth_1/.rpt

DV flow

Setup DV flow