Add targets.bzl for top level targets - Used in verilator and future fpga targets to easily extend bazel targets - Rename chip_sim_tb to matcha_sim_tb Change-Id: I36a45aba0f6ef293bf4b9c270dc1ea9c9f759428
diff --git a/hw/BUILD b/hw/BUILD index 85d820d..a5722c2 100644 --- a/hw/BUILD +++ b/hw/BUILD
@@ -4,7 +4,8 @@ # SPDX-License-Identifier: Apache-2.0 load("@bazel_skylib//rules:common_settings.bzl", "string_list_flag") -load("//rules:verilator.bzl", "target_fusesoc_build") +load("@lowrisc_opentitan//rules:fusesoc.bzl", "fusesoc_build") +load("//rules:targets.bzl", "get_targets") package(default_visibility = ["//visibility:public"]) @@ -18,31 +19,38 @@ ], ) -target_fusesoc_build( - name = "matcha", +TARGETS = get_targets() + +[fusesoc_build( + name = "{}_verilator_real".format(target), + srcs = [ + ":all_files", + "//hw/top_{}:all_files".format(target), + "//hw/top_{}/dv/verilator:all_files".format(target), + ], + cores = [ + "//:cores", + "//hw/ip:BUILD", + "//hw/top_{}:BUILD".format(target), + ], + data = ["@lowrisc_opentitan//hw/ip/otbn:all_files"], + make_options = ":make_options", output_groups = { - "binary": ["sim-verilator/Vchip_sim_tb"], + "binary": ["sim-verilator/V{}_sim_tb".format(target)], }, -) + systems = ["lowrisc:dv:chip_{}_verilator_sim".format(target)], + tags = [ + "manual", + "verilator", + ], + target = "sim", +) for target in TARGETS] -target_fusesoc_build( - name = "sencha", - output_groups = { - "binary": ["sim-verilator/Vsencha_sim_tb"], - }, -) - -filegroup( - name = "matcha_verilator_bin", - srcs = [":matcha_verilator_real"], +[filegroup( + name = "{}_verilator_bin".format(target), + srcs = [":{}_verilator_real".format(target)], output_group = "binary", -) - -filegroup( - name = "sencha_verilator_bin", - srcs = [":sencha_verilator_real"], - output_group = "binary", -) +) for target in TARGETS] # This is used in CI steps that do not want to run Verilator tests, and thus # do not want to accidentally build the Verilator model. This causes the @@ -66,25 +74,15 @@ """, ) -alias( - name = "matcha_verilator", +[alias( + name = "{}_verilator".format(target), actual = select({ ":disable_verilator_build": ":verilator_stub", - "//conditions:default": ":matcha_verilator_bin", + "//conditions:default": ":{}_verilator_bin".format(target), }), tags = ["verilator"], visibility = ["//visibility:public"], -) - -alias( - name = "sencha_verilator", - actual = select({ - ":disable_verilator_build": ":verilator_stub", - "//conditions:default": ":sencha_verilator_bin", - }), - tags = ["verilator"], - visibility = ["//visibility:public"], -) +) for target in TARGETS] filegroup( name = "all_files",
diff --git a/hw/top_matcha/dv/verilator/chip_sim.core b/hw/top_matcha/dv/verilator/chip_sim.core index 7806dd4..d287c97 100644 --- a/hw/top_matcha/dv/verilator/chip_sim.core +++ b/hw/top_matcha/dv/verilator/chip_sim.core
@@ -3,7 +3,7 @@ # Copyright lowRISC contributors # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:matcha_verilator_sim:0.1" +name: "lowrisc:dv:chip_matcha_verilator_sim:0.1" description: "Matcha toplevel for simulation with Verilator" filesets: files_sim_verilator: @@ -76,7 +76,7 @@ default: &default_target filesets: - files_sim_verilator - toplevel: chip_sim_tb + toplevel: matcha_sim_tb sim: parameters: @@ -93,7 +93,7 @@ default_tool: verilator filesets: - files_sim_verilator - toplevel: chip_sim_tb + toplevel: matcha_sim_tb tools: verilator: mode: cc @@ -109,7 +109,7 @@ - '--unroll-count 512' # TODO: Variable expansion depends on edalize internals. Find better solution. # (Applies to LDFLAGS expansion below as well) - - '-CFLAGS "$(CFLAGS_FOR_BUILD) -std=c++11 -Wall -DVM_TRACE_FMT_FST -DVL_USER_STOP -DTOPLEVEL_NAME=chip_sim_tb"' + - '-CFLAGS "$(CFLAGS_FOR_BUILD) -std=c++11 -Wall -DVM_TRACE_FMT_FST -DVL_USER_STOP -DTOPLEVEL_NAME=matcha_sim_tb"' - '-LDFLAGS "$(LDFLAGS_FOR_BUILD) -pthread -lutil -lelf"' - '-Wall' # Execute simulation with four threads by default, which works best
diff --git a/hw/top_matcha/dv/verilator/chip_sim_tb.cc b/hw/top_matcha/dv/verilator/chip_sim_tb.cc index 9ff7a15..d76a1fa 100644 --- a/hw/top_matcha/dv/verilator/chip_sim_tb.cc +++ b/hw/top_matcha/dv/verilator/chip_sim_tb.cc
@@ -23,13 +23,13 @@ #include "verilator_sim_ctrl.h" int main(int argc, char **argv) { - chip_sim_tb top; + matcha_sim_tb top; VerilatorMemUtil memutil; VerilatorSimCtrl &simctrl = VerilatorSimCtrl::GetInstance(); simctrl.SetTop(&top, &top.clk_i, &top.rst_ni, VerilatorSimCtrlFlags::ResetPolarityNegative); - std::string top_scope("TOP.chip_sim_tb.u_dut.top_matcha"); + std::string top_scope("TOP.matcha_sim_tb.u_dut.top_matcha"); std::string ram1p_adv_scope( "u_prim_ram_1p_adv.u_mem." "gen_generic.u_impl_generic");
diff --git a/hw/top_matcha/dv/verilator/chip_sim_tb.sv b/hw/top_matcha/dv/verilator/chip_sim_tb.sv index e106812..e4a4932 100644 --- a/hw/top_matcha/dv/verilator/chip_sim_tb.sv +++ b/hw/top_matcha/dv/verilator/chip_sim_tb.sv
@@ -13,7 +13,7 @@ // See the License for the specific language governing permissions and // limitations under the License. -module chip_sim_tb ( +module matcha_sim_tb ( // Clock and Reset input clk_i, input rst_ni @@ -324,4 +324,4 @@ `undef TEST_DONE_SEC -endmodule // chip_sim_tb +endmodule // matcha_sim_tb
diff --git a/hw/top_sencha/dv/verilator/chip_sim.core b/hw/top_sencha/dv/verilator/chip_sim.core index 33fc3a7..d49956d 100644 --- a/hw/top_sencha/dv/verilator/chip_sim.core +++ b/hw/top_sencha/dv/verilator/chip_sim.core
@@ -3,7 +3,7 @@ # Copyright lowRISC contributors # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:sencha_verilator_sim:0.1" +name: "lowrisc:dv:chip_sencha_verilator_sim:0.1" description: "Sencha toplevel for simulation with Verilator" filesets: files_sim_verilator:
diff --git a/rules/targets.bzl b/rules/targets.bzl new file mode 100644 index 0000000..32ba996 --- /dev/null +++ b/rules/targets.bzl
@@ -0,0 +1,8 @@ +# Copyright 2024 Google LLC. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +def get_targets(): + """Keep top level targets here to be included elsewhere.""" + + return ["matcha","sencha"]
diff --git a/rules/verilator.bzl b/rules/verilator.bzl deleted file mode 100644 index f186b85..0000000 --- a/rules/verilator.bzl +++ /dev/null
@@ -1,41 +0,0 @@ -# Copyright 2024 Google LLC. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -"""Support rules for building target specific verilated simulators""" - -load( - "@lowrisc_opentitan//rules:fusesoc.bzl", - "fusesoc_build", -) - -def target_fusesoc_build(name, output_groups): - """A helper macro for building verilator targets. - - Args: - name: The name of the top level target. - output_groups: Verilator testbench passed to fusesoc_build. - """ - - fusesoc_build( - name = "{}_verilator_real".format(name), - srcs = [ - ":all_files", - "//hw/top_{}:all_files".format(name), - "//hw/top_{}/dv/verilator:all_files".format(name), - ], - cores = [ - "//:cores", - "//hw/ip:BUILD", - "//hw/top_{}:BUILD".format(name), - ], - data = ["@lowrisc_opentitan//hw/ip/otbn:all_files"], - make_options = ":make_options", - output_groups = output_groups, - systems = ["lowrisc:dv:{}_verilator_sim".format(name)], - tags = [ - "manual", - "verilator", - ], - target = "sim", - )