Add sram_ctrl tests to edacloud.

Change-Id: Ia5b173f1c264879bb91b2304e6e7e589362618d4

hw/top_matcha/dv/chip_sim_cfg.hjson

diff --git a/hw/top_matcha/dv/chip_sim_cfg.hjson b/hw/top_matcha/dv/chip_sim_cfg.hjson
index 7ed049b..c5e8959 100644
--- a/hw/top_matcha/dv/chip_sim_cfg.hjson
+++ b/hw/top_matcha/dv/chip_sim_cfg.hjson
@@ -1573,14 +1573,14 @@
     {
       name: chip_sw_sram_ctrl_scrambled_access
       uvm_test_seq: chip_sw_sram_ctrl_scrambled_access_vseq
-      sw_images: ["//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test:1"]
+      sw_images: ["//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test:1:matcha"]
       en_run_modes: ["sw_test_mode_test_rom"]
       run_opts: ["+sw_test_timeout_ns=12_000_000", "+en_scb_tl_err_chk=0"]
     }
     {
       name: chip_sw_sram_ctrl_scrambled_access_jitter_en
       uvm_test_seq: chip_sw_sram_ctrl_scrambled_access_vseq
-      sw_images: ["//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test:1"]
+      sw_images: ["//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test:1:matcha"]
       en_run_modes: ["sw_test_mode_test_rom"]
       run_opts: ["+sw_test_timeout_ns=12_000_000",
                  "+en_jitter=1", "+en_scb_tl_err_chk=0"]
@@ -1588,7 +1588,7 @@
     {
       name: chip_sw_sram_ctrl_execution_main
       uvm_test_seq: chip_sw_sram_ctrl_execution_main_vseq
-      sw_images: ["//sw/device/tests/sim_dv:sram_ctrl_execution_main_test:1"]
+      sw_images: ["//sw/device/tests/sim_dv:sram_ctrl_execution_main_test:1:matcha"]
       en_run_modes: ["sw_test_mode_test_rom"]
     }
     {
@@ -2140,6 +2140,8 @@
         "chip_sw_spi_device_pass_through",
         "chip_sw_spi_device_tx_rx",
         "chip_sw_spi_host_tx_rx",
+        "chip_sw_sram_ctrl_execution_main",
+        "chip_sw_sram_ctrl_scrambled_access",
         "chip_sw_sram_ctrl_smoketest",
         "chip_sw_sysrst_ctrl_in_irq",
         "chip_sw_sysrst_ctrl_inputs",
@@ -2242,6 +2244,9 @@
         "chip_sw_spi_device_pass_through",
         "chip_sw_spi_device_tx_rx",
         "chip_sw_spi_host_tx_rx",
+        "chip_sw_sram_ctrl_execution_main",
+        "chip_sw_sram_ctrl_scrambled_access",
+        "chip_sw_sram_ctrl_scrambled_access_jitter_en",
         "chip_sw_sram_ctrl_smoketest",
         "chip_sw_uart_smoketest",
         "chip_sw_sysrst_ctrl_in_irq",

sw/device/tests/sim_dv/BUILD

diff --git a/sw/device/tests/sim_dv/BUILD b/sw/device/tests/sim_dv/BUILD
index c45c6f5..d9f748d 100644
--- a/sw/device/tests/sim_dv/BUILD
+++ b/sw/device/tests/sim_dv/BUILD
@@ -451,3 +451,34 @@
         "@lowrisc_opentitan//sw/device/lib/testing:rv_plic_testutils",
     ],
 )
+
+matcha_dv_test(
+    name = "sram_ctrl_execution_main_test",
+    srcs = ["@lowrisc_opentitan//sw/device/tests/sim_dv:sram_ctrl_execution_main_test.c"],
+    deps = [
+        "//sw/device/tests:test_dv_lib_opentitan",
+        "@lowrisc_opentitan//hw/ip/otp_ctrl/data:otp_ctrl_regs",
+        "@lowrisc_opentitan//sw/device/lib/base:bitfield",
+        "@lowrisc_opentitan//sw/device/lib/base:macros",
+        "@lowrisc_opentitan//sw/device/lib/base:multibits",
+        "@lowrisc_opentitan//sw/device/lib/dif:sram_ctrl",
+        "@lowrisc_opentitan//sw/device/lib/testing:lc_ctrl_testutils",
+        "@lowrisc_opentitan//sw/device/lib/testing:otp_ctrl_testutils",
+        "@lowrisc_opentitan//sw/device/lib/testing:sram_ctrl_testutils",
+    ],
+)
+
+matcha_dv_test(
+    name = "sram_ctrl_scrambled_access_test",
+    srcs = ["@lowrisc_opentitan//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test.c"],
+    deps = [
+        "//sw/device/lib/dif:rstmgr",
+        "//sw/device/tests:test_dv_lib_opentitan",
+        "@lowrisc_opentitan//hw/ip/sram_ctrl/data:sram_ctrl_regs",
+        "@lowrisc_opentitan//sw/device/lib/base:macros",
+        "@lowrisc_opentitan//sw/device/lib/base:multibits",
+        "@lowrisc_opentitan//sw/device/lib/base:stdasm",
+        "@lowrisc_opentitan//sw/device/lib/testing:rstmgr_testutils",
+        "@lowrisc_opentitan//sw/device/lib/testing:sram_ctrl_testutils",
+    ],
+)