Add chip_csr_bit_bash and chip_padctrl_attributes to edacloud

  - Fixed Bug: 281760247

Change-Id: I257cf74333c642f7996412102efd4b38474b7418

hw/top_matcha/dv/chip_sim_cfg.hjson

diff --git a/hw/top_matcha/dv/chip_sim_cfg.hjson b/hw/top_matcha/dv/chip_sim_cfg.hjson
index 9486b91..61adfc4 100644
--- a/hw/top_matcha/dv/chip_sim_cfg.hjson
+++ b/hw/top_matcha/dv/chip_sim_cfg.hjson
@@ -2059,6 +2059,8 @@
       // TODO(b/287644985): Track the dv tests to be implemented.
       name: edacloud_nightly
       tests: [
+        "chip_csr_bit_bash",
+        "chip_padctrl_attributes",
         "chip_plic_all_irqs",
         "chip_rv_dm_ndm_reset_req",
         "chip_sw_aes_smoketest",
@@ -2145,6 +2147,8 @@
     {
       name: edacloud_all
       tests: [
+        "chip_csr_bit_bash",
+        "chip_padctrl_attributes",
         "chip_plic_all_irqs",
         "chip_rv_dm_ndm_reset_req",
         "chip_sw_aes_smoketest",

hw/top_matcha/ip/dma/data/dma.hjson

diff --git a/hw/top_matcha/ip/dma/data/dma.hjson b/hw/top_matcha/ip/dma/data/dma.hjson
index d28e8c7..276e9fe 100644
--- a/hw/top_matcha/ip/dma/data/dma.hjson
+++ b/hw/top_matcha/ip/dma/data/dma.hjson
@@ -119,7 +119,9 @@
               Write 1 to enable reader interrupt.
             '''
           },
-        ]
+        ],
+        tags: [
+        "excl:CsrAllTests:CsrExclWrite"],
       },
 
       // "INTR_STATE" is used here instead of IP name of "INTR_STATUS" to match the

util/topgen_matcha/gen_dv.py

diff --git a/util/topgen_matcha/gen_dv.py b/util/topgen_matcha/gen_dv.py
index 189829d..a0c9549 100755
--- a/util/topgen_matcha/gen_dv.py
+++ b/util/topgen_matcha/gen_dv.py
@@ -1,4 +1,4 @@
-# Copyright 2022 Google LLC
+# Copyright 2022-2023 Google LLC
 # Copyright lowRISC contributors.
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
@@ -31,10 +31,16 @@
                                          resource_filename('reggen', '.')])
     uvm_reg_tpl = lookup.get_template('top_uvm_reg.sv.tpl')
 
+    # isp_wrapper is excluded from CSR tests
+    create_isp_wrapper = "1'b1"
+    if "cover_reg_top" in outdir:
+        create_isp_wrapper = "1'b0"
+
     # Expand template
     try:
         to_write = uvm_reg_tpl.render(top=top,
-                                      dv_base_names=dv_base_names)
+                                      dv_base_names=dv_base_names,
+                                      create_isp_wrapper=create_isp_wrapper)
     except:  # noqa: E722
         log.error(exceptions.text_error_template().render())
         return 1

util/topgen_matcha/top_uvm_reg.sv.tpl

diff --git a/util/topgen_matcha/top_uvm_reg.sv.tpl b/util/topgen_matcha/top_uvm_reg.sv.tpl
index 1e6dde5..2ba63c7 100644
--- a/util/topgen_matcha/top_uvm_reg.sv.tpl
+++ b/util/topgen_matcha/top_uvm_reg.sv.tpl
@@ -1,3 +1,4 @@
+// Copyright 2022-2023 Google LLC.
 // Copyright lowRISC contributors.
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
@@ -16,6 +17,8 @@
 ##
 ##    dv_base_names  a DvBaseNames object for the base register type
 ##
+##    create_isp_wrapper	Create isp_wrapper RAL model based on the context
+##
 ## Like uvm_reg.sv.tpl, we use functions from uvm_reg_base.sv.tpl to define
 ## per-device-interface code.
 ##
@@ -88,6 +91,8 @@
             inst_name == "tlul_mailbox_smc" or
             inst_name == "rv_core_ibex_smc"):
           create_block = "1'b0"
+        elif inst_name == "isp_wrapper":
+          create_block = create_isp_wrapper
 %>\
     bit create_${if_inst} = ${create_block};
     rand ${bcname(esc_if_name)} ${if_inst};