[ml_top/hw] Clean interlock deps after FPU removal HDL change: https://spacebeaker-review.git.corp.google.com/c/shodan/experimental-kelvin/+/42689 Change-Id: Id81c43371fe516e22215395c6292d16498c0056c
diff --git a/hw/top_matcha/ip/ml_top/rtl/kelvin.v b/hw/top_matcha/ip/ml_top/rtl/kelvin.v index 9518e6c..eef8063 100644 --- a/hw/top_matcha/ip/ml_top/rtl/kelvin.v +++ b/hw/top_matcha/ip/ml_top/rtl/kelvin.v
@@ -1,4 +1,4 @@ -// SHA: 55e14cfc9047c4e5432d0e3af7ab30e76857d1a1 +// SHA: f34e03a9f8d551620cabd4624ca28ebe96cfd3f4 module Regfile( input clock, input reset, @@ -21845,76 +21845,76 @@ wire mask_2 = decode_0_io_inst_ready & decode_1_io_inst_ready; // @[SCore.scala 84:46] wire mask_3 = mask_2 & decode_2_io_inst_ready; // @[SCore.scala 85:73] wire _fetch_io_inst_lanes_0_ready_T = decode_0_io_inst_ready; // @[SCore.scala 90:61] - wire [31:0] scoreboard_spec2 = decode_1_io_scoreboard_spec | decode_0_io_scoreboard_spec; // @[SCore.scala 123:55] - wire [31:0] scoreboard_spec3 = decode_2_io_scoreboard_spec | scoreboard_spec2; // @[SCore.scala 124:55] - reg mluInvalidate; // @[SCore.scala 210:30] - wire _regfile_io_writeData_0_valid_T = csr_io_rd_valid | alu_0_io_rd_valid; // @[SCore.scala 240:48] + wire [31:0] scoreboard_spec2 = decode_1_io_scoreboard_spec | decode_0_io_scoreboard_spec; // @[SCore.scala 113:55] + wire [31:0] scoreboard_spec3 = decode_2_io_scoreboard_spec | scoreboard_spec2; // @[SCore.scala 114:55] + reg mluInvalidate; // @[SCore.scala 200:30] + wire _regfile_io_writeData_0_valid_T = csr_io_rd_valid | alu_0_io_rd_valid; // @[SCore.scala 230:48] wire [4:0] _regfile_io_writeData_0_addr_T = csr_io_rd_valid ? csr_io_rd_addr : 5'h0; // @[Library.scala 8:8] wire [4:0] _regfile_io_writeData_0_addr_T_1 = alu_0_io_rd_valid ? alu_0_io_rd_addr : 5'h0; // @[Library.scala 8:8] - wire [4:0] _regfile_io_writeData_0_addr_T_2 = _regfile_io_writeData_0_addr_T | _regfile_io_writeData_0_addr_T_1; // @[SCore.scala 245:36] + wire [4:0] _regfile_io_writeData_0_addr_T_2 = _regfile_io_writeData_0_addr_T | _regfile_io_writeData_0_addr_T_1; // @[SCore.scala 235:36] wire [4:0] _regfile_io_writeData_0_addr_T_3 = bru_0_io_rd_valid ? bru_0_io_rd_addr : 5'h0; // @[Library.scala 8:8] - wire [4:0] _regfile_io_writeData_0_addr_T_4 = _regfile_io_writeData_0_addr_T_2 | _regfile_io_writeData_0_addr_T_3; // @[SCore.scala 246:54] + wire [4:0] _regfile_io_writeData_0_addr_T_4 = _regfile_io_writeData_0_addr_T_2 | _regfile_io_writeData_0_addr_T_3; // @[SCore.scala 236:54] wire [4:0] _regfile_io_writeData_0_addr_T_5 = io_vcore_rd_0_valid ? io_vcore_rd_0_addr : 5'h0; // @[Library.scala 8:8] wire [31:0] _regfile_io_writeData_0_data_T = csr_io_rd_valid ? csr_io_rd_data : 32'h0; // @[Library.scala 8:8] wire [31:0] _regfile_io_writeData_0_data_T_1 = alu_0_io_rd_valid ? alu_0_io_rd_data : 32'h0; // @[Library.scala 8:8] - wire [31:0] _regfile_io_writeData_0_data_T_2 = _regfile_io_writeData_0_data_T | _regfile_io_writeData_0_data_T_1; // @[SCore.scala 251:36] + wire [31:0] _regfile_io_writeData_0_data_T_2 = _regfile_io_writeData_0_data_T | _regfile_io_writeData_0_data_T_1; // @[SCore.scala 241:36] wire [31:0] _regfile_io_writeData_0_data_T_3 = bru_0_io_rd_valid ? bru_0_io_rd_data : 32'h0; // @[Library.scala 8:8] - wire [31:0] _regfile_io_writeData_0_data_T_4 = _regfile_io_writeData_0_data_T_2 | _regfile_io_writeData_0_data_T_3; // @[SCore.scala 252:54] + wire [31:0] _regfile_io_writeData_0_data_T_4 = _regfile_io_writeData_0_data_T_2 | _regfile_io_writeData_0_data_T_3; // @[SCore.scala 242:54] wire [31:0] _regfile_io_writeData_0_data_T_5 = io_vcore_rd_0_valid ? io_vcore_rd_0_data : 32'h0; // @[Library.scala 8:8] - wire [1:0] _T_15 = csr_io_rd_valid + alu_0_io_rd_valid; // @[SCore.scala 256:23] - wire [1:0] _GEN_3 = {{1'd0}, bru_0_io_rd_valid}; // @[SCore.scala 257:32] - wire [2:0] _T_16 = _T_15 + _GEN_3; // @[SCore.scala 257:32] - wire [2:0] _GEN_4 = {{2'd0}, io_vcore_rd_0_valid}; // @[SCore.scala 257:54] - wire [3:0] _T_17 = _T_16 + _GEN_4; // @[SCore.scala 257:54] - wire _T_18 = _T_17 <= 4'h1; // @[SCore.scala 258:35] - wire _regfile_io_writeData_1_valid_T = alu_1_io_rd_valid; // @[SCore.scala 240:48] + wire [1:0] _T_15 = csr_io_rd_valid + alu_0_io_rd_valid; // @[SCore.scala 246:23] + wire [1:0] _GEN_3 = {{1'd0}, bru_0_io_rd_valid}; // @[SCore.scala 247:32] + wire [2:0] _T_16 = _T_15 + _GEN_3; // @[SCore.scala 247:32] + wire [2:0] _GEN_4 = {{2'd0}, io_vcore_rd_0_valid}; // @[SCore.scala 247:54] + wire [3:0] _T_17 = _T_16 + _GEN_4; // @[SCore.scala 247:54] + wire _T_18 = _T_17 <= 4'h1; // @[SCore.scala 248:35] + wire _regfile_io_writeData_1_valid_T = alu_1_io_rd_valid; // @[SCore.scala 230:48] wire [4:0] _regfile_io_writeData_1_addr_T_1 = alu_1_io_rd_valid ? alu_1_io_rd_addr : 5'h0; // @[Library.scala 8:8] wire [4:0] _regfile_io_writeData_1_addr_T_3 = bru_1_io_rd_valid ? bru_1_io_rd_addr : 5'h0; // @[Library.scala 8:8] - wire [4:0] _regfile_io_writeData_1_addr_T_4 = _regfile_io_writeData_1_addr_T_1 | _regfile_io_writeData_1_addr_T_3; // @[SCore.scala 246:54] + wire [4:0] _regfile_io_writeData_1_addr_T_4 = _regfile_io_writeData_1_addr_T_1 | _regfile_io_writeData_1_addr_T_3; // @[SCore.scala 236:54] wire [4:0] _regfile_io_writeData_1_addr_T_5 = io_vcore_rd_1_valid ? io_vcore_rd_1_addr : 5'h0; // @[Library.scala 8:8] wire [31:0] _regfile_io_writeData_1_data_T_1 = alu_1_io_rd_valid ? alu_1_io_rd_data : 32'h0; // @[Library.scala 8:8] wire [31:0] _regfile_io_writeData_1_data_T_3 = bru_1_io_rd_valid ? bru_1_io_rd_data : 32'h0; // @[Library.scala 8:8] - wire [31:0] _regfile_io_writeData_1_data_T_4 = _regfile_io_writeData_1_data_T_1 | _regfile_io_writeData_1_data_T_3; // @[SCore.scala 252:54] + wire [31:0] _regfile_io_writeData_1_data_T_4 = _regfile_io_writeData_1_data_T_1 | _regfile_io_writeData_1_data_T_3; // @[SCore.scala 242:54] wire [31:0] _regfile_io_writeData_1_data_T_5 = io_vcore_rd_1_valid ? io_vcore_rd_1_data : 32'h0; // @[Library.scala 8:8] - wire [1:0] _T_22 = {{1'd0}, alu_1_io_rd_valid}; // @[SCore.scala 256:23] - wire [1:0] _GEN_5 = {{1'd0}, bru_1_io_rd_valid}; // @[SCore.scala 257:32] - wire [2:0] _T_23 = _T_22 + _GEN_5; // @[SCore.scala 257:32] - wire [2:0] _GEN_6 = {{2'd0}, io_vcore_rd_1_valid}; // @[SCore.scala 257:54] - wire [3:0] _T_24 = _T_23 + _GEN_6; // @[SCore.scala 257:54] - wire _T_25 = _T_24 <= 4'h1; // @[SCore.scala 258:35] - wire _regfile_io_writeData_2_valid_T = alu_2_io_rd_valid; // @[SCore.scala 240:48] + wire [1:0] _T_22 = {{1'd0}, alu_1_io_rd_valid}; // @[SCore.scala 246:23] + wire [1:0] _GEN_5 = {{1'd0}, bru_1_io_rd_valid}; // @[SCore.scala 247:32] + wire [2:0] _T_23 = _T_22 + _GEN_5; // @[SCore.scala 247:32] + wire [2:0] _GEN_6 = {{2'd0}, io_vcore_rd_1_valid}; // @[SCore.scala 247:54] + wire [3:0] _T_24 = _T_23 + _GEN_6; // @[SCore.scala 247:54] + wire _T_25 = _T_24 <= 4'h1; // @[SCore.scala 248:35] + wire _regfile_io_writeData_2_valid_T = alu_2_io_rd_valid; // @[SCore.scala 230:48] wire [4:0] _regfile_io_writeData_2_addr_T_1 = alu_2_io_rd_valid ? alu_2_io_rd_addr : 5'h0; // @[Library.scala 8:8] wire [4:0] _regfile_io_writeData_2_addr_T_3 = bru_2_io_rd_valid ? bru_2_io_rd_addr : 5'h0; // @[Library.scala 8:8] - wire [4:0] _regfile_io_writeData_2_addr_T_4 = _regfile_io_writeData_2_addr_T_1 | _regfile_io_writeData_2_addr_T_3; // @[SCore.scala 246:54] + wire [4:0] _regfile_io_writeData_2_addr_T_4 = _regfile_io_writeData_2_addr_T_1 | _regfile_io_writeData_2_addr_T_3; // @[SCore.scala 236:54] wire [4:0] _regfile_io_writeData_2_addr_T_5 = io_vcore_rd_2_valid ? io_vcore_rd_2_addr : 5'h0; // @[Library.scala 8:8] wire [31:0] _regfile_io_writeData_2_data_T_1 = alu_2_io_rd_valid ? alu_2_io_rd_data : 32'h0; // @[Library.scala 8:8] wire [31:0] _regfile_io_writeData_2_data_T_3 = bru_2_io_rd_valid ? bru_2_io_rd_data : 32'h0; // @[Library.scala 8:8] - wire [31:0] _regfile_io_writeData_2_data_T_4 = _regfile_io_writeData_2_data_T_1 | _regfile_io_writeData_2_data_T_3; // @[SCore.scala 252:54] + wire [31:0] _regfile_io_writeData_2_data_T_4 = _regfile_io_writeData_2_data_T_1 | _regfile_io_writeData_2_data_T_3; // @[SCore.scala 242:54] wire [31:0] _regfile_io_writeData_2_data_T_5 = io_vcore_rd_2_valid ? io_vcore_rd_2_data : 32'h0; // @[Library.scala 8:8] - wire [1:0] _T_29 = {{1'd0}, alu_2_io_rd_valid}; // @[SCore.scala 256:23] - wire [1:0] _GEN_7 = {{1'd0}, bru_2_io_rd_valid}; // @[SCore.scala 257:32] - wire [2:0] _T_30 = _T_29 + _GEN_7; // @[SCore.scala 257:32] - wire [2:0] _GEN_8 = {{2'd0}, io_vcore_rd_2_valid}; // @[SCore.scala 257:54] - wire [3:0] _T_31 = _T_30 + _GEN_8; // @[SCore.scala 257:54] - wire _T_32 = _T_31 <= 4'h1; // @[SCore.scala 258:35] - wire _regfile_io_writeData_3_valid_T = alu_3_io_rd_valid; // @[SCore.scala 240:48] + wire [1:0] _T_29 = {{1'd0}, alu_2_io_rd_valid}; // @[SCore.scala 246:23] + wire [1:0] _GEN_7 = {{1'd0}, bru_2_io_rd_valid}; // @[SCore.scala 247:32] + wire [2:0] _T_30 = _T_29 + _GEN_7; // @[SCore.scala 247:32] + wire [2:0] _GEN_8 = {{2'd0}, io_vcore_rd_2_valid}; // @[SCore.scala 247:54] + wire [3:0] _T_31 = _T_30 + _GEN_8; // @[SCore.scala 247:54] + wire _T_32 = _T_31 <= 4'h1; // @[SCore.scala 248:35] + wire _regfile_io_writeData_3_valid_T = alu_3_io_rd_valid; // @[SCore.scala 230:48] wire [4:0] _regfile_io_writeData_3_addr_T_1 = alu_3_io_rd_valid ? alu_3_io_rd_addr : 5'h0; // @[Library.scala 8:8] wire [4:0] _regfile_io_writeData_3_addr_T_3 = bru_3_io_rd_valid ? bru_3_io_rd_addr : 5'h0; // @[Library.scala 8:8] - wire [4:0] _regfile_io_writeData_3_addr_T_4 = _regfile_io_writeData_3_addr_T_1 | _regfile_io_writeData_3_addr_T_3; // @[SCore.scala 246:54] + wire [4:0] _regfile_io_writeData_3_addr_T_4 = _regfile_io_writeData_3_addr_T_1 | _regfile_io_writeData_3_addr_T_3; // @[SCore.scala 236:54] wire [4:0] _regfile_io_writeData_3_addr_T_5 = io_vcore_rd_3_valid ? io_vcore_rd_3_addr : 5'h0; // @[Library.scala 8:8] wire [31:0] _regfile_io_writeData_3_data_T_1 = alu_3_io_rd_valid ? alu_3_io_rd_data : 32'h0; // @[Library.scala 8:8] wire [31:0] _regfile_io_writeData_3_data_T_3 = bru_3_io_rd_valid ? bru_3_io_rd_data : 32'h0; // @[Library.scala 8:8] - wire [31:0] _regfile_io_writeData_3_data_T_4 = _regfile_io_writeData_3_data_T_1 | _regfile_io_writeData_3_data_T_3; // @[SCore.scala 252:54] + wire [31:0] _regfile_io_writeData_3_data_T_4 = _regfile_io_writeData_3_data_T_1 | _regfile_io_writeData_3_data_T_3; // @[SCore.scala 242:54] wire [31:0] _regfile_io_writeData_3_data_T_5 = io_vcore_rd_3_valid ? io_vcore_rd_3_data : 32'h0; // @[Library.scala 8:8] - wire [1:0] _T_36 = {{1'd0}, alu_3_io_rd_valid}; // @[SCore.scala 256:23] - wire [1:0] _GEN_9 = {{1'd0}, bru_3_io_rd_valid}; // @[SCore.scala 257:32] - wire [2:0] _T_37 = _T_36 + _GEN_9; // @[SCore.scala 257:32] - wire [2:0] _GEN_10 = {{2'd0}, io_vcore_rd_3_valid}; // @[SCore.scala 257:54] - wire [3:0] _T_38 = _T_37 + _GEN_10; // @[SCore.scala 257:54] - wire _T_39 = _T_38 <= 4'h1; // @[SCore.scala 258:35] - reg slogValid; // @[SCore.scala 302:26] - reg [1:0] slogAddr; // @[SCore.scala 303:21] - wire [2:0] _GEN_2 = decode_0_io_slog ? decode_0_io_inst_inst[14:12] : {{1'd0}, slogAddr}; // @[SCore.scala 307:17 308:14 303:21] + wire [1:0] _T_36 = {{1'd0}, alu_3_io_rd_valid}; // @[SCore.scala 246:23] + wire [1:0] _GEN_9 = {{1'd0}, bru_3_io_rd_valid}; // @[SCore.scala 247:32] + wire [2:0] _T_37 = _T_36 + _GEN_9; // @[SCore.scala 247:32] + wire [2:0] _GEN_10 = {{2'd0}, io_vcore_rd_3_valid}; // @[SCore.scala 247:54] + wire [3:0] _T_38 = _T_37 + _GEN_10; // @[SCore.scala 247:54] + wire _T_39 = _T_38 <= 4'h1; // @[SCore.scala 248:35] + reg slogValid; // @[SCore.scala 292:26] + reg [1:0] slogAddr; // @[SCore.scala 293:21] + wire [2:0] _GEN_2 = decode_0_io_slog ? decode_0_io_inst_inst[14:12] : {{1'd0}, slogAddr}; // @[SCore.scala 297:17 298:14 293:21] wire [1:0] _io_slog_addr_T = slogValid ? slogAddr : 2'h0; // @[Library.scala 8:8] Regfile regfile ( // @[Regfile.scala 9:18] .clock(regfile_clock), @@ -22618,132 +22618,132 @@ .io_rd_addr(dvu_io_rd_addr), .io_rd_data(dvu_io_rd_data) ); - assign io_halted = csr_io_halted; // @[SCore.scala 179:13] - assign io_fault = csr_io_fault; // @[SCore.scala 180:13] - assign io_ibus_valid = fetch_io_ibus_valid; // @[SCore.scala 291:11] - assign io_ibus_addr = fetch_io_ibus_addr; // @[SCore.scala 291:11] - assign io_dbus_valid = lsu_io_dbus_valid; // @[SCore.scala 295:11] - assign io_dbus_write = lsu_io_dbus_write; // @[SCore.scala 295:11] - assign io_dbus_addr = lsu_io_dbus_addr; // @[SCore.scala 295:11] - assign io_dbus_adrx = lsu_io_dbus_adrx; // @[SCore.scala 295:11] - assign io_dbus_size = lsu_io_dbus_size; // @[SCore.scala 295:11] - assign io_dbus_wdata = lsu_io_dbus_wdata; // @[SCore.scala 295:11] - assign io_dbus_wmask = lsu_io_dbus_wmask; // @[SCore.scala 295:11] - assign io_ubus_valid = lsu_io_ubus_valid; // @[SCore.scala 296:11] - assign io_ubus_write = lsu_io_ubus_write; // @[SCore.scala 296:11] - assign io_ubus_addr = lsu_io_ubus_addr; // @[SCore.scala 296:11] - assign io_ubus_wdata = lsu_io_ubus_wdata; // @[SCore.scala 296:11] - assign io_ubus_wmask = lsu_io_ubus_wmask; // @[SCore.scala 296:11] - assign io_vldst = lsu_io_vldst; // @[SCore.scala 298:12] - assign io_vcore_vinst_0_valid = decode_0_io_vinst_valid; // @[SCore.scala 282:23] - assign io_vcore_vinst_0_addr = decode_0_io_vinst_addr; // @[SCore.scala 282:23] - assign io_vcore_vinst_0_inst = decode_0_io_vinst_inst; // @[SCore.scala 282:23] - assign io_vcore_vinst_0_op = decode_0_io_vinst_op; // @[SCore.scala 282:23] - assign io_vcore_vinst_1_valid = decode_1_io_vinst_valid; // @[SCore.scala 282:23] - assign io_vcore_vinst_1_addr = decode_1_io_vinst_addr; // @[SCore.scala 282:23] - assign io_vcore_vinst_1_inst = decode_1_io_vinst_inst; // @[SCore.scala 282:23] - assign io_vcore_vinst_1_op = decode_1_io_vinst_op; // @[SCore.scala 282:23] - assign io_vcore_vinst_2_valid = decode_2_io_vinst_valid; // @[SCore.scala 282:23] - assign io_vcore_vinst_2_addr = decode_2_io_vinst_addr; // @[SCore.scala 282:23] - assign io_vcore_vinst_2_inst = decode_2_io_vinst_inst; // @[SCore.scala 282:23] - assign io_vcore_vinst_2_op = decode_2_io_vinst_op; // @[SCore.scala 282:23] - assign io_vcore_vinst_3_valid = decode_3_io_vinst_valid; // @[SCore.scala 282:23] - assign io_vcore_vinst_3_addr = decode_3_io_vinst_addr; // @[SCore.scala 282:23] - assign io_vcore_vinst_3_inst = decode_3_io_vinst_inst; // @[SCore.scala 282:23] - assign io_vcore_vinst_3_op = decode_3_io_vinst_op; // @[SCore.scala 282:23] - assign io_vcore_rs_0_data = regfile_io_readData_0_data; // @[SCore.scala 286:20] - assign io_vcore_rs_1_data = regfile_io_readData_1_data; // @[SCore.scala 286:20] - assign io_vcore_rs_2_data = regfile_io_readData_2_data; // @[SCore.scala 286:20] - assign io_vcore_rs_3_data = regfile_io_readData_3_data; // @[SCore.scala 286:20] - assign io_vcore_rs_4_data = regfile_io_readData_4_data; // @[SCore.scala 286:20] - assign io_vcore_rs_5_data = regfile_io_readData_5_data; // @[SCore.scala 286:20] - assign io_vcore_rs_6_data = regfile_io_readData_6_data; // @[SCore.scala 286:20] - assign io_vcore_rs_7_data = regfile_io_readData_7_data; // @[SCore.scala 286:20] - assign io_iflush_valid = iflush; // @[SCore.scala 166:19] + assign io_halted = csr_io_halted; // @[SCore.scala 169:13] + assign io_fault = csr_io_fault; // @[SCore.scala 170:13] + assign io_ibus_valid = fetch_io_ibus_valid; // @[SCore.scala 281:11] + assign io_ibus_addr = fetch_io_ibus_addr; // @[SCore.scala 281:11] + assign io_dbus_valid = lsu_io_dbus_valid; // @[SCore.scala 285:11] + assign io_dbus_write = lsu_io_dbus_write; // @[SCore.scala 285:11] + assign io_dbus_addr = lsu_io_dbus_addr; // @[SCore.scala 285:11] + assign io_dbus_adrx = lsu_io_dbus_adrx; // @[SCore.scala 285:11] + assign io_dbus_size = lsu_io_dbus_size; // @[SCore.scala 285:11] + assign io_dbus_wdata = lsu_io_dbus_wdata; // @[SCore.scala 285:11] + assign io_dbus_wmask = lsu_io_dbus_wmask; // @[SCore.scala 285:11] + assign io_ubus_valid = lsu_io_ubus_valid; // @[SCore.scala 286:11] + assign io_ubus_write = lsu_io_ubus_write; // @[SCore.scala 286:11] + assign io_ubus_addr = lsu_io_ubus_addr; // @[SCore.scala 286:11] + assign io_ubus_wdata = lsu_io_ubus_wdata; // @[SCore.scala 286:11] + assign io_ubus_wmask = lsu_io_ubus_wmask; // @[SCore.scala 286:11] + assign io_vldst = lsu_io_vldst; // @[SCore.scala 288:12] + assign io_vcore_vinst_0_valid = decode_0_io_vinst_valid; // @[SCore.scala 272:23] + assign io_vcore_vinst_0_addr = decode_0_io_vinst_addr; // @[SCore.scala 272:23] + assign io_vcore_vinst_0_inst = decode_0_io_vinst_inst; // @[SCore.scala 272:23] + assign io_vcore_vinst_0_op = decode_0_io_vinst_op; // @[SCore.scala 272:23] + assign io_vcore_vinst_1_valid = decode_1_io_vinst_valid; // @[SCore.scala 272:23] + assign io_vcore_vinst_1_addr = decode_1_io_vinst_addr; // @[SCore.scala 272:23] + assign io_vcore_vinst_1_inst = decode_1_io_vinst_inst; // @[SCore.scala 272:23] + assign io_vcore_vinst_1_op = decode_1_io_vinst_op; // @[SCore.scala 272:23] + assign io_vcore_vinst_2_valid = decode_2_io_vinst_valid; // @[SCore.scala 272:23] + assign io_vcore_vinst_2_addr = decode_2_io_vinst_addr; // @[SCore.scala 272:23] + assign io_vcore_vinst_2_inst = decode_2_io_vinst_inst; // @[SCore.scala 272:23] + assign io_vcore_vinst_2_op = decode_2_io_vinst_op; // @[SCore.scala 272:23] + assign io_vcore_vinst_3_valid = decode_3_io_vinst_valid; // @[SCore.scala 272:23] + assign io_vcore_vinst_3_addr = decode_3_io_vinst_addr; // @[SCore.scala 272:23] + assign io_vcore_vinst_3_inst = decode_3_io_vinst_inst; // @[SCore.scala 272:23] + assign io_vcore_vinst_3_op = decode_3_io_vinst_op; // @[SCore.scala 272:23] + assign io_vcore_rs_0_data = regfile_io_readData_0_data; // @[SCore.scala 276:20] + assign io_vcore_rs_1_data = regfile_io_readData_1_data; // @[SCore.scala 276:20] + assign io_vcore_rs_2_data = regfile_io_readData_2_data; // @[SCore.scala 276:20] + assign io_vcore_rs_3_data = regfile_io_readData_3_data; // @[SCore.scala 276:20] + assign io_vcore_rs_4_data = regfile_io_readData_4_data; // @[SCore.scala 276:20] + assign io_vcore_rs_5_data = regfile_io_readData_5_data; // @[SCore.scala 276:20] + assign io_vcore_rs_6_data = regfile_io_readData_6_data; // @[SCore.scala 276:20] + assign io_vcore_rs_7_data = regfile_io_readData_7_data; // @[SCore.scala 276:20] + assign io_iflush_valid = iflush; // @[SCore.scala 156:19] assign io_dflush_valid = lsu_io_flush_valid; // @[SCore.scala 59:19] assign io_dflush_all = lsu_io_flush_all; // @[SCore.scala 60:19] - assign io_slog_valid = slogValid; // @[SCore.scala 311:17] - assign io_slog_addr = {{3'd0}, _io_slog_addr_T}; // @[SCore.scala 312:17] + assign io_slog_valid = slogValid; // @[SCore.scala 301:17] + assign io_slog_addr = {{3'd0}, _io_slog_addr_T}; // @[SCore.scala 302:17] assign io_slog_data = slogValid ? regfile_io_readData_0_data : 32'h0; // @[Library.scala 8:8] assign regfile_clock = clock; assign regfile_reset = reset; - assign regfile_io_readAddr_0_valid = decode_0_io_rs1Read_valid; // @[SCore.scala 228:36] - assign regfile_io_readAddr_0_addr = decode_0_io_rs1Read_addr; // @[SCore.scala 228:36] - assign regfile_io_readAddr_1_valid = decode_0_io_rs2Read_valid; // @[SCore.scala 229:36] - assign regfile_io_readAddr_1_addr = decode_0_io_rs2Read_addr; // @[SCore.scala 229:36] - assign regfile_io_readAddr_2_valid = decode_1_io_rs1Read_valid; // @[SCore.scala 228:36] - assign regfile_io_readAddr_2_addr = decode_1_io_rs1Read_addr; // @[SCore.scala 228:36] - assign regfile_io_readAddr_3_valid = decode_1_io_rs2Read_valid; // @[SCore.scala 229:36] - assign regfile_io_readAddr_3_addr = decode_1_io_rs2Read_addr; // @[SCore.scala 229:36] - assign regfile_io_readAddr_4_valid = decode_2_io_rs1Read_valid; // @[SCore.scala 228:36] - assign regfile_io_readAddr_4_addr = decode_2_io_rs1Read_addr; // @[SCore.scala 228:36] - assign regfile_io_readAddr_5_valid = decode_2_io_rs2Read_valid; // @[SCore.scala 229:36] - assign regfile_io_readAddr_5_addr = decode_2_io_rs2Read_addr; // @[SCore.scala 229:36] - assign regfile_io_readAddr_6_valid = decode_3_io_rs1Read_valid; // @[SCore.scala 228:36] - assign regfile_io_readAddr_6_addr = decode_3_io_rs1Read_addr; // @[SCore.scala 228:36] - assign regfile_io_readAddr_7_valid = decode_3_io_rs2Read_valid; // @[SCore.scala 229:36] - assign regfile_io_readAddr_7_addr = decode_3_io_rs2Read_addr; // @[SCore.scala 229:36] - assign regfile_io_readSet_0_valid = decode_0_io_rs1Set_valid; // @[SCore.scala 230:35] - assign regfile_io_readSet_0_value = decode_0_io_rs1Set_value; // @[SCore.scala 230:35] - assign regfile_io_readSet_1_valid = decode_0_io_rs2Set_valid; // @[SCore.scala 231:35] - assign regfile_io_readSet_1_value = decode_0_io_rs2Set_value; // @[SCore.scala 231:35] - assign regfile_io_readSet_2_valid = decode_1_io_rs1Set_valid; // @[SCore.scala 230:35] - assign regfile_io_readSet_2_value = decode_1_io_rs1Set_value; // @[SCore.scala 230:35] - assign regfile_io_readSet_3_valid = decode_1_io_rs2Set_valid; // @[SCore.scala 231:35] - assign regfile_io_readSet_3_value = decode_1_io_rs2Set_value; // @[SCore.scala 231:35] - assign regfile_io_readSet_4_valid = decode_2_io_rs1Set_valid; // @[SCore.scala 230:35] - assign regfile_io_readSet_4_value = decode_2_io_rs1Set_value; // @[SCore.scala 230:35] - assign regfile_io_readSet_5_valid = decode_2_io_rs2Set_valid; // @[SCore.scala 231:35] - assign regfile_io_readSet_5_value = decode_2_io_rs2Set_value; // @[SCore.scala 231:35] - assign regfile_io_readSet_6_valid = decode_3_io_rs1Set_valid; // @[SCore.scala 230:35] - assign regfile_io_readSet_6_value = decode_3_io_rs1Set_value; // @[SCore.scala 230:35] - assign regfile_io_readSet_7_valid = decode_3_io_rs2Set_valid; // @[SCore.scala 231:35] - assign regfile_io_readSet_7_value = decode_3_io_rs2Set_value; // @[SCore.scala 231:35] - assign regfile_io_writeAddr_0_valid = decode_0_io_rdMark_valid; // @[SCore.scala 232:29] - assign regfile_io_writeAddr_0_addr = decode_0_io_rdMark_addr; // @[SCore.scala 232:29] - assign regfile_io_writeAddr_1_valid = decode_1_io_rdMark_valid; // @[SCore.scala 232:29] - assign regfile_io_writeAddr_1_addr = decode_1_io_rdMark_addr; // @[SCore.scala 232:29] - assign regfile_io_writeAddr_2_valid = decode_2_io_rdMark_valid; // @[SCore.scala 232:29] - assign regfile_io_writeAddr_2_addr = decode_2_io_rdMark_addr; // @[SCore.scala 232:29] - assign regfile_io_writeAddr_3_valid = decode_3_io_rdMark_valid; // @[SCore.scala 232:29] - assign regfile_io_writeAddr_3_addr = decode_3_io_rdMark_addr; // @[SCore.scala 232:29] - assign regfile_io_busAddr_0_bypass = decode_0_io_busRead_bypass; // @[SCore.scala 233:27] - assign regfile_io_busAddr_0_immen = decode_0_io_busRead_immen; // @[SCore.scala 233:27] - assign regfile_io_busAddr_0_immed = decode_0_io_busRead_immed; // @[SCore.scala 233:27] - assign regfile_io_busAddr_1_bypass = decode_1_io_busRead_bypass; // @[SCore.scala 233:27] - assign regfile_io_busAddr_1_immed = decode_1_io_busRead_immed; // @[SCore.scala 233:27] - assign regfile_io_busAddr_2_bypass = decode_2_io_busRead_bypass; // @[SCore.scala 233:27] - assign regfile_io_busAddr_2_immed = decode_2_io_busRead_immed; // @[SCore.scala 233:27] - assign regfile_io_busAddr_3_bypass = decode_3_io_busRead_bypass; // @[SCore.scala 233:27] - assign regfile_io_busAddr_3_immed = decode_3_io_busRead_immed; // @[SCore.scala 233:27] - assign regfile_io_writeData_0_valid = _regfile_io_writeData_0_valid_T | bru_0_io_rd_valid | io_vcore_rd_0_valid; // @[SCore.scala 241:79] - assign regfile_io_writeData_0_addr = _regfile_io_writeData_0_addr_T_4 | _regfile_io_writeData_0_addr_T_5; // @[SCore.scala 247:54] - assign regfile_io_writeData_0_data = _regfile_io_writeData_0_data_T_4 | _regfile_io_writeData_0_data_T_5; // @[SCore.scala 253:54] - assign regfile_io_writeData_1_valid = _regfile_io_writeData_1_valid_T | bru_1_io_rd_valid | io_vcore_rd_1_valid; // @[SCore.scala 241:79] - assign regfile_io_writeData_1_addr = _regfile_io_writeData_1_addr_T_4 | _regfile_io_writeData_1_addr_T_5; // @[SCore.scala 247:54] - assign regfile_io_writeData_1_data = _regfile_io_writeData_1_data_T_4 | _regfile_io_writeData_1_data_T_5; // @[SCore.scala 253:54] - assign regfile_io_writeData_2_valid = _regfile_io_writeData_2_valid_T | bru_2_io_rd_valid | io_vcore_rd_2_valid; // @[SCore.scala 241:79] - assign regfile_io_writeData_2_addr = _regfile_io_writeData_2_addr_T_4 | _regfile_io_writeData_2_addr_T_5; // @[SCore.scala 247:54] - assign regfile_io_writeData_2_data = _regfile_io_writeData_2_data_T_4 | _regfile_io_writeData_2_data_T_5; // @[SCore.scala 253:54] - assign regfile_io_writeData_3_valid = _regfile_io_writeData_3_valid_T | bru_3_io_rd_valid | io_vcore_rd_3_valid; // @[SCore.scala 241:79] - assign regfile_io_writeData_3_addr = _regfile_io_writeData_3_addr_T_4 | _regfile_io_writeData_3_addr_T_5; // @[SCore.scala 247:54] - assign regfile_io_writeData_3_data = _regfile_io_writeData_3_data_T_4 | _regfile_io_writeData_3_data_T_5; // @[SCore.scala 253:54] - assign regfile_io_writeData_4_valid = mlu_io_rd_valid | dvu_io_rd_valid; // @[SCore.scala 261:52] - assign regfile_io_writeData_4_addr = mlu_io_rd_valid ? mlu_io_rd_addr : dvu_io_rd_addr; // @[SCore.scala 262:38] - assign regfile_io_writeData_4_data = mlu_io_rd_valid ? mlu_io_rd_data : dvu_io_rd_data; // @[SCore.scala 263:38] - assign regfile_io_writeData_5_valid = lsu_io_rd_valid; // @[SCore.scala 266:33] - assign regfile_io_writeData_5_addr = lsu_io_rd_addr; // @[SCore.scala 267:33] - assign regfile_io_writeData_5_data = lsu_io_rd_data; // @[SCore.scala 268:33] - assign regfile_io_writeMask_0_valid = 1'h0; // @[SCore.scala 270:33] - assign regfile_io_writeMask_1_valid = regfile_io_writeMask_0_valid | bru_0_io_taken_valid; // @[SCore.scala 271:66] - assign regfile_io_writeMask_2_valid = regfile_io_writeMask_1_valid | bru_1_io_taken_valid; // @[SCore.scala 273:66] - assign regfile_io_writeMask_3_valid = regfile_io_writeMask_2_valid | bru_2_io_taken_valid; // @[SCore.scala 275:66] - assign regfile_io_writeMask_4_valid = mluInvalidate; // @[SCore.scala 277:33] + assign regfile_io_readAddr_0_valid = decode_0_io_rs1Read_valid; // @[SCore.scala 218:36] + assign regfile_io_readAddr_0_addr = decode_0_io_rs1Read_addr; // @[SCore.scala 218:36] + assign regfile_io_readAddr_1_valid = decode_0_io_rs2Read_valid; // @[SCore.scala 219:36] + assign regfile_io_readAddr_1_addr = decode_0_io_rs2Read_addr; // @[SCore.scala 219:36] + assign regfile_io_readAddr_2_valid = decode_1_io_rs1Read_valid; // @[SCore.scala 218:36] + assign regfile_io_readAddr_2_addr = decode_1_io_rs1Read_addr; // @[SCore.scala 218:36] + assign regfile_io_readAddr_3_valid = decode_1_io_rs2Read_valid; // @[SCore.scala 219:36] + assign regfile_io_readAddr_3_addr = decode_1_io_rs2Read_addr; // @[SCore.scala 219:36] + assign regfile_io_readAddr_4_valid = decode_2_io_rs1Read_valid; // @[SCore.scala 218:36] + assign regfile_io_readAddr_4_addr = decode_2_io_rs1Read_addr; // @[SCore.scala 218:36] + assign regfile_io_readAddr_5_valid = decode_2_io_rs2Read_valid; // @[SCore.scala 219:36] + assign regfile_io_readAddr_5_addr = decode_2_io_rs2Read_addr; // @[SCore.scala 219:36] + assign regfile_io_readAddr_6_valid = decode_3_io_rs1Read_valid; // @[SCore.scala 218:36] + assign regfile_io_readAddr_6_addr = decode_3_io_rs1Read_addr; // @[SCore.scala 218:36] + assign regfile_io_readAddr_7_valid = decode_3_io_rs2Read_valid; // @[SCore.scala 219:36] + assign regfile_io_readAddr_7_addr = decode_3_io_rs2Read_addr; // @[SCore.scala 219:36] + assign regfile_io_readSet_0_valid = decode_0_io_rs1Set_valid; // @[SCore.scala 220:35] + assign regfile_io_readSet_0_value = decode_0_io_rs1Set_value; // @[SCore.scala 220:35] + assign regfile_io_readSet_1_valid = decode_0_io_rs2Set_valid; // @[SCore.scala 221:35] + assign regfile_io_readSet_1_value = decode_0_io_rs2Set_value; // @[SCore.scala 221:35] + assign regfile_io_readSet_2_valid = decode_1_io_rs1Set_valid; // @[SCore.scala 220:35] + assign regfile_io_readSet_2_value = decode_1_io_rs1Set_value; // @[SCore.scala 220:35] + assign regfile_io_readSet_3_valid = decode_1_io_rs2Set_valid; // @[SCore.scala 221:35] + assign regfile_io_readSet_3_value = decode_1_io_rs2Set_value; // @[SCore.scala 221:35] + assign regfile_io_readSet_4_valid = decode_2_io_rs1Set_valid; // @[SCore.scala 220:35] + assign regfile_io_readSet_4_value = decode_2_io_rs1Set_value; // @[SCore.scala 220:35] + assign regfile_io_readSet_5_valid = decode_2_io_rs2Set_valid; // @[SCore.scala 221:35] + assign regfile_io_readSet_5_value = decode_2_io_rs2Set_value; // @[SCore.scala 221:35] + assign regfile_io_readSet_6_valid = decode_3_io_rs1Set_valid; // @[SCore.scala 220:35] + assign regfile_io_readSet_6_value = decode_3_io_rs1Set_value; // @[SCore.scala 220:35] + assign regfile_io_readSet_7_valid = decode_3_io_rs2Set_valid; // @[SCore.scala 221:35] + assign regfile_io_readSet_7_value = decode_3_io_rs2Set_value; // @[SCore.scala 221:35] + assign regfile_io_writeAddr_0_valid = decode_0_io_rdMark_valid; // @[SCore.scala 222:29] + assign regfile_io_writeAddr_0_addr = decode_0_io_rdMark_addr; // @[SCore.scala 222:29] + assign regfile_io_writeAddr_1_valid = decode_1_io_rdMark_valid; // @[SCore.scala 222:29] + assign regfile_io_writeAddr_1_addr = decode_1_io_rdMark_addr; // @[SCore.scala 222:29] + assign regfile_io_writeAddr_2_valid = decode_2_io_rdMark_valid; // @[SCore.scala 222:29] + assign regfile_io_writeAddr_2_addr = decode_2_io_rdMark_addr; // @[SCore.scala 222:29] + assign regfile_io_writeAddr_3_valid = decode_3_io_rdMark_valid; // @[SCore.scala 222:29] + assign regfile_io_writeAddr_3_addr = decode_3_io_rdMark_addr; // @[SCore.scala 222:29] + assign regfile_io_busAddr_0_bypass = decode_0_io_busRead_bypass; // @[SCore.scala 223:27] + assign regfile_io_busAddr_0_immen = decode_0_io_busRead_immen; // @[SCore.scala 223:27] + assign regfile_io_busAddr_0_immed = decode_0_io_busRead_immed; // @[SCore.scala 223:27] + assign regfile_io_busAddr_1_bypass = decode_1_io_busRead_bypass; // @[SCore.scala 223:27] + assign regfile_io_busAddr_1_immed = decode_1_io_busRead_immed; // @[SCore.scala 223:27] + assign regfile_io_busAddr_2_bypass = decode_2_io_busRead_bypass; // @[SCore.scala 223:27] + assign regfile_io_busAddr_2_immed = decode_2_io_busRead_immed; // @[SCore.scala 223:27] + assign regfile_io_busAddr_3_bypass = decode_3_io_busRead_bypass; // @[SCore.scala 223:27] + assign regfile_io_busAddr_3_immed = decode_3_io_busRead_immed; // @[SCore.scala 223:27] + assign regfile_io_writeData_0_valid = _regfile_io_writeData_0_valid_T | bru_0_io_rd_valid | io_vcore_rd_0_valid; // @[SCore.scala 231:79] + assign regfile_io_writeData_0_addr = _regfile_io_writeData_0_addr_T_4 | _regfile_io_writeData_0_addr_T_5; // @[SCore.scala 237:54] + assign regfile_io_writeData_0_data = _regfile_io_writeData_0_data_T_4 | _regfile_io_writeData_0_data_T_5; // @[SCore.scala 243:54] + assign regfile_io_writeData_1_valid = _regfile_io_writeData_1_valid_T | bru_1_io_rd_valid | io_vcore_rd_1_valid; // @[SCore.scala 231:79] + assign regfile_io_writeData_1_addr = _regfile_io_writeData_1_addr_T_4 | _regfile_io_writeData_1_addr_T_5; // @[SCore.scala 237:54] + assign regfile_io_writeData_1_data = _regfile_io_writeData_1_data_T_4 | _regfile_io_writeData_1_data_T_5; // @[SCore.scala 243:54] + assign regfile_io_writeData_2_valid = _regfile_io_writeData_2_valid_T | bru_2_io_rd_valid | io_vcore_rd_2_valid; // @[SCore.scala 231:79] + assign regfile_io_writeData_2_addr = _regfile_io_writeData_2_addr_T_4 | _regfile_io_writeData_2_addr_T_5; // @[SCore.scala 237:54] + assign regfile_io_writeData_2_data = _regfile_io_writeData_2_data_T_4 | _regfile_io_writeData_2_data_T_5; // @[SCore.scala 243:54] + assign regfile_io_writeData_3_valid = _regfile_io_writeData_3_valid_T | bru_3_io_rd_valid | io_vcore_rd_3_valid; // @[SCore.scala 231:79] + assign regfile_io_writeData_3_addr = _regfile_io_writeData_3_addr_T_4 | _regfile_io_writeData_3_addr_T_5; // @[SCore.scala 237:54] + assign regfile_io_writeData_3_data = _regfile_io_writeData_3_data_T_4 | _regfile_io_writeData_3_data_T_5; // @[SCore.scala 243:54] + assign regfile_io_writeData_4_valid = mlu_io_rd_valid | dvu_io_rd_valid; // @[SCore.scala 251:52] + assign regfile_io_writeData_4_addr = mlu_io_rd_valid ? mlu_io_rd_addr : dvu_io_rd_addr; // @[SCore.scala 252:38] + assign regfile_io_writeData_4_data = mlu_io_rd_valid ? mlu_io_rd_data : dvu_io_rd_data; // @[SCore.scala 253:38] + assign regfile_io_writeData_5_valid = lsu_io_rd_valid; // @[SCore.scala 256:33] + assign regfile_io_writeData_5_addr = lsu_io_rd_addr; // @[SCore.scala 257:33] + assign regfile_io_writeData_5_data = lsu_io_rd_data; // @[SCore.scala 258:33] + assign regfile_io_writeMask_0_valid = 1'h0; // @[SCore.scala 260:33] + assign regfile_io_writeMask_1_valid = regfile_io_writeMask_0_valid | bru_0_io_taken_valid; // @[SCore.scala 261:66] + assign regfile_io_writeMask_2_valid = regfile_io_writeMask_1_valid | bru_1_io_taken_valid; // @[SCore.scala 263:66] + assign regfile_io_writeMask_3_valid = regfile_io_writeMask_2_valid | bru_2_io_taken_valid; // @[SCore.scala 265:66] + assign regfile_io_writeMask_4_valid = mluInvalidate; // @[SCore.scala 267:33] assign fetch_clock = clock; assign fetch_reset = reset; assign fetch_io_csr_value_0 = io_csr_in_value_0; // @[SCore.scala 70:16] - assign fetch_io_ibus_ready = io_ibus_ready; // @[SCore.scala 291:11] - assign fetch_io_ibus_rdata = io_ibus_rdata; // @[SCore.scala 291:11] + assign fetch_io_ibus_ready = io_ibus_ready; // @[SCore.scala 281:11] + assign fetch_io_ibus_rdata = io_ibus_rdata; // @[SCore.scala 281:11] assign fetch_io_inst_lanes_0_ready = decode_0_io_inst_ready; // @[SCore.scala 90:61] assign fetch_io_inst_lanes_1_ready = decode_1_io_inst_ready & decode_0_io_inst_ready; // @[SCore.scala 90:61] assign fetch_io_inst_lanes_2_ready = decode_2_io_inst_ready & mask_2; // @[SCore.scala 90:61] @@ -22766,14 +22766,14 @@ assign decode_0_io_inst_addr = fetch_io_inst_lanes_0_addr; // @[SCore.scala 91:28] assign decode_0_io_inst_inst = fetch_io_inst_lanes_0_inst; // @[SCore.scala 92:28] assign decode_0_io_inst_brchFwd = fetch_io_inst_lanes_0_brchFwd; // @[SCore.scala 93:31] - assign decode_0_io_scoreboard_regd = regfile_io_scoreboard_regd; // @[SCore.scala 130:32] - assign decode_0_io_scoreboard_comb = regfile_io_scoreboard_comb; // @[SCore.scala 129:32] - assign decode_0_io_mactive = io_vcore_mactive; // @[SCore.scala 139:24] - assign decode_0_io_lsu_ready = lsu_io_req_0_ready; // @[SCore.scala 191:28] - assign decode_0_io_dvu_ready = dvu_io_req_ready; // @[SCore.scala 215:14] - assign decode_0_io_vinst_ready = io_vcore_vinst_0_ready; // @[SCore.scala 282:23] + assign decode_0_io_scoreboard_regd = regfile_io_scoreboard_regd; // @[SCore.scala 120:32] + assign decode_0_io_scoreboard_comb = regfile_io_scoreboard_comb; // @[SCore.scala 119:32] + assign decode_0_io_mactive = io_vcore_mactive; // @[SCore.scala 129:24] + assign decode_0_io_lsu_ready = lsu_io_req_0_ready; // @[SCore.scala 181:28] + assign decode_0_io_dvu_ready = dvu_io_req_ready; // @[SCore.scala 205:14] + assign decode_0_io_vinst_ready = io_vcore_vinst_0_ready; // @[SCore.scala 272:23] assign decode_0_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 46:43] - assign decode_0_io_interlock = bru_0_io_interlock; // @[SCore.scala 110:26] + assign decode_0_io_interlock = bru_0_io_interlock; // @[SCore.scala 100:26] assign decode_1_clock = clock; assign decode_1_reset = reset; assign decode_1_io_halted = csr_io_halted; // @[SCore.scala 96:25] @@ -22781,15 +22781,15 @@ assign decode_1_io_inst_addr = fetch_io_inst_lanes_1_addr; // @[SCore.scala 91:28] assign decode_1_io_inst_inst = fetch_io_inst_lanes_1_inst; // @[SCore.scala 92:28] assign decode_1_io_inst_brchFwd = fetch_io_inst_lanes_1_brchFwd; // @[SCore.scala 93:31] - assign decode_1_io_scoreboard_regd = regfile_io_scoreboard_regd | decode_0_io_scoreboard_spec; // @[SCore.scala 132:62] - assign decode_1_io_scoreboard_comb = regfile_io_scoreboard_comb | decode_0_io_scoreboard_spec; // @[SCore.scala 131:62] - assign decode_1_io_lsu_ready = lsu_io_req_1_ready; // @[SCore.scala 191:28] - assign decode_1_io_vinst_ready = io_vcore_vinst_1_ready; // @[SCore.scala 282:23] + assign decode_1_io_scoreboard_regd = regfile_io_scoreboard_regd | decode_0_io_scoreboard_spec; // @[SCore.scala 122:62] + assign decode_1_io_scoreboard_comb = regfile_io_scoreboard_comb | decode_0_io_scoreboard_spec; // @[SCore.scala 121:62] + assign decode_1_io_lsu_ready = lsu_io_req_1_ready; // @[SCore.scala 181:28] + assign decode_1_io_vinst_ready = io_vcore_vinst_1_ready; // @[SCore.scala 272:23] assign decode_1_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 46:43] - assign decode_1_io_interlock = decode_0_io_interlock; // @[SCore.scala 111:44] - assign decode_1_io_serializeIn_mul = decode_0_io_serializeOut_mul; // @[SCore.scala 117:28] - assign decode_1_io_serializeIn_jump = decode_0_io_serializeOut_jump; // @[SCore.scala 117:28] - assign decode_1_io_serializeIn_brcond = decode_0_io_serializeOut_brcond; // @[SCore.scala 117:28] + assign decode_1_io_interlock = decode_0_io_interlock; // @[SCore.scala 101:26] + assign decode_1_io_serializeIn_mul = decode_0_io_serializeOut_mul; // @[SCore.scala 107:28] + assign decode_1_io_serializeIn_jump = decode_0_io_serializeOut_jump; // @[SCore.scala 107:28] + assign decode_1_io_serializeIn_brcond = decode_0_io_serializeOut_brcond; // @[SCore.scala 107:28] assign decode_2_clock = clock; assign decode_2_reset = reset; assign decode_2_io_halted = csr_io_halted; // @[SCore.scala 96:25] @@ -22797,15 +22797,15 @@ assign decode_2_io_inst_addr = fetch_io_inst_lanes_2_addr; // @[SCore.scala 91:28] assign decode_2_io_inst_inst = fetch_io_inst_lanes_2_inst; // @[SCore.scala 92:28] assign decode_2_io_inst_brchFwd = fetch_io_inst_lanes_2_brchFwd; // @[SCore.scala 93:31] - assign decode_2_io_scoreboard_regd = regfile_io_scoreboard_regd | scoreboard_spec2; // @[SCore.scala 134:62] - assign decode_2_io_scoreboard_comb = regfile_io_scoreboard_comb | scoreboard_spec2; // @[SCore.scala 133:62] - assign decode_2_io_lsu_ready = lsu_io_req_2_ready; // @[SCore.scala 191:28] - assign decode_2_io_vinst_ready = io_vcore_vinst_2_ready; // @[SCore.scala 282:23] + assign decode_2_io_scoreboard_regd = regfile_io_scoreboard_regd | scoreboard_spec2; // @[SCore.scala 124:62] + assign decode_2_io_scoreboard_comb = regfile_io_scoreboard_comb | scoreboard_spec2; // @[SCore.scala 123:62] + assign decode_2_io_lsu_ready = lsu_io_req_2_ready; // @[SCore.scala 181:28] + assign decode_2_io_vinst_ready = io_vcore_vinst_2_ready; // @[SCore.scala 272:23] assign decode_2_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 46:43] - assign decode_2_io_interlock = decode_1_io_interlock; // @[SCore.scala 112:44] - assign decode_2_io_serializeIn_mul = decode_1_io_serializeOut_mul; // @[SCore.scala 118:28] - assign decode_2_io_serializeIn_jump = decode_1_io_serializeOut_jump; // @[SCore.scala 118:28] - assign decode_2_io_serializeIn_brcond = decode_1_io_serializeOut_brcond; // @[SCore.scala 118:28] + assign decode_2_io_interlock = decode_1_io_interlock; // @[SCore.scala 102:26] + assign decode_2_io_serializeIn_mul = decode_1_io_serializeOut_mul; // @[SCore.scala 108:28] + assign decode_2_io_serializeIn_jump = decode_1_io_serializeOut_jump; // @[SCore.scala 108:28] + assign decode_2_io_serializeIn_brcond = decode_1_io_serializeOut_brcond; // @[SCore.scala 108:28] assign decode_3_clock = clock; assign decode_3_reset = reset; assign decode_3_io_halted = csr_io_halted; // @[SCore.scala 96:25] @@ -22813,200 +22813,200 @@ assign decode_3_io_inst_addr = fetch_io_inst_lanes_3_addr; // @[SCore.scala 91:28] assign decode_3_io_inst_inst = fetch_io_inst_lanes_3_inst; // @[SCore.scala 92:28] assign decode_3_io_inst_brchFwd = fetch_io_inst_lanes_3_brchFwd; // @[SCore.scala 93:31] - assign decode_3_io_scoreboard_regd = regfile_io_scoreboard_regd | scoreboard_spec3; // @[SCore.scala 136:62] - assign decode_3_io_scoreboard_comb = regfile_io_scoreboard_comb | scoreboard_spec3; // @[SCore.scala 135:62] - assign decode_3_io_lsu_ready = lsu_io_req_3_ready; // @[SCore.scala 191:28] - assign decode_3_io_vinst_ready = io_vcore_vinst_3_ready; // @[SCore.scala 282:23] + assign decode_3_io_scoreboard_regd = regfile_io_scoreboard_regd | scoreboard_spec3; // @[SCore.scala 126:62] + assign decode_3_io_scoreboard_comb = regfile_io_scoreboard_comb | scoreboard_spec3; // @[SCore.scala 125:62] + assign decode_3_io_lsu_ready = lsu_io_req_3_ready; // @[SCore.scala 181:28] + assign decode_3_io_vinst_ready = io_vcore_vinst_3_ready; // @[SCore.scala 272:23] assign decode_3_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 46:43] - assign decode_3_io_interlock = decode_2_io_interlock; // @[SCore.scala 113:44] - assign decode_3_io_serializeIn_mul = decode_2_io_serializeOut_mul; // @[SCore.scala 119:28] - assign decode_3_io_serializeIn_jump = decode_2_io_serializeOut_jump; // @[SCore.scala 119:28] - assign decode_3_io_serializeIn_brcond = decode_2_io_serializeOut_brcond; // @[SCore.scala 119:28] + assign decode_3_io_interlock = decode_2_io_interlock; // @[SCore.scala 103:26] + assign decode_3_io_serializeIn_mul = decode_2_io_serializeOut_mul; // @[SCore.scala 109:28] + assign decode_3_io_serializeIn_jump = decode_2_io_serializeOut_jump; // @[SCore.scala 109:28] + assign decode_3_io_serializeIn_brcond = decode_2_io_serializeOut_brcond; // @[SCore.scala 109:28] assign alu_0_clock = clock; assign alu_0_reset = reset; - assign alu_0_io_req_valid = decode_0_io_alu_valid; // @[SCore.scala 147:19] - assign alu_0_io_req_addr = decode_0_io_alu_addr; // @[SCore.scala 147:19] - assign alu_0_io_req_op = decode_0_io_alu_op; // @[SCore.scala 147:19] - assign alu_0_io_rs1_valid = regfile_io_readData_0_valid; // @[SCore.scala 148:19] - assign alu_0_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 148:19] - assign alu_0_io_rs2_valid = regfile_io_readData_1_valid; // @[SCore.scala 149:19] - assign alu_0_io_rs2_data = regfile_io_readData_1_data; // @[SCore.scala 149:19] + assign alu_0_io_req_valid = decode_0_io_alu_valid; // @[SCore.scala 137:19] + assign alu_0_io_req_addr = decode_0_io_alu_addr; // @[SCore.scala 137:19] + assign alu_0_io_req_op = decode_0_io_alu_op; // @[SCore.scala 137:19] + assign alu_0_io_rs1_valid = regfile_io_readData_0_valid; // @[SCore.scala 138:19] + assign alu_0_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 138:19] + assign alu_0_io_rs2_valid = regfile_io_readData_1_valid; // @[SCore.scala 139:19] + assign alu_0_io_rs2_data = regfile_io_readData_1_data; // @[SCore.scala 139:19] assign alu_1_clock = clock; assign alu_1_reset = reset; - assign alu_1_io_req_valid = decode_1_io_alu_valid; // @[SCore.scala 147:19] - assign alu_1_io_req_addr = decode_1_io_alu_addr; // @[SCore.scala 147:19] - assign alu_1_io_req_op = decode_1_io_alu_op; // @[SCore.scala 147:19] - assign alu_1_io_rs1_valid = regfile_io_readData_2_valid; // @[SCore.scala 148:19] - assign alu_1_io_rs1_data = regfile_io_readData_2_data; // @[SCore.scala 148:19] - assign alu_1_io_rs2_valid = regfile_io_readData_3_valid; // @[SCore.scala 149:19] - assign alu_1_io_rs2_data = regfile_io_readData_3_data; // @[SCore.scala 149:19] + assign alu_1_io_req_valid = decode_1_io_alu_valid; // @[SCore.scala 137:19] + assign alu_1_io_req_addr = decode_1_io_alu_addr; // @[SCore.scala 137:19] + assign alu_1_io_req_op = decode_1_io_alu_op; // @[SCore.scala 137:19] + assign alu_1_io_rs1_valid = regfile_io_readData_2_valid; // @[SCore.scala 138:19] + assign alu_1_io_rs1_data = regfile_io_readData_2_data; // @[SCore.scala 138:19] + assign alu_1_io_rs2_valid = regfile_io_readData_3_valid; // @[SCore.scala 139:19] + assign alu_1_io_rs2_data = regfile_io_readData_3_data; // @[SCore.scala 139:19] assign alu_2_clock = clock; assign alu_2_reset = reset; - assign alu_2_io_req_valid = decode_2_io_alu_valid; // @[SCore.scala 147:19] - assign alu_2_io_req_addr = decode_2_io_alu_addr; // @[SCore.scala 147:19] - assign alu_2_io_req_op = decode_2_io_alu_op; // @[SCore.scala 147:19] - assign alu_2_io_rs1_valid = regfile_io_readData_4_valid; // @[SCore.scala 148:19] - assign alu_2_io_rs1_data = regfile_io_readData_4_data; // @[SCore.scala 148:19] - assign alu_2_io_rs2_valid = regfile_io_readData_5_valid; // @[SCore.scala 149:19] - assign alu_2_io_rs2_data = regfile_io_readData_5_data; // @[SCore.scala 149:19] + assign alu_2_io_req_valid = decode_2_io_alu_valid; // @[SCore.scala 137:19] + assign alu_2_io_req_addr = decode_2_io_alu_addr; // @[SCore.scala 137:19] + assign alu_2_io_req_op = decode_2_io_alu_op; // @[SCore.scala 137:19] + assign alu_2_io_rs1_valid = regfile_io_readData_4_valid; // @[SCore.scala 138:19] + assign alu_2_io_rs1_data = regfile_io_readData_4_data; // @[SCore.scala 138:19] + assign alu_2_io_rs2_valid = regfile_io_readData_5_valid; // @[SCore.scala 139:19] + assign alu_2_io_rs2_data = regfile_io_readData_5_data; // @[SCore.scala 139:19] assign alu_3_clock = clock; assign alu_3_reset = reset; - assign alu_3_io_req_valid = decode_3_io_alu_valid; // @[SCore.scala 147:19] - assign alu_3_io_req_addr = decode_3_io_alu_addr; // @[SCore.scala 147:19] - assign alu_3_io_req_op = decode_3_io_alu_op; // @[SCore.scala 147:19] - assign alu_3_io_rs1_valid = regfile_io_readData_6_valid; // @[SCore.scala 148:19] - assign alu_3_io_rs1_data = regfile_io_readData_6_data; // @[SCore.scala 148:19] - assign alu_3_io_rs2_valid = regfile_io_readData_7_valid; // @[SCore.scala 149:19] - assign alu_3_io_rs2_data = regfile_io_readData_7_data; // @[SCore.scala 149:19] + assign alu_3_io_req_valid = decode_3_io_alu_valid; // @[SCore.scala 137:19] + assign alu_3_io_req_addr = decode_3_io_alu_addr; // @[SCore.scala 137:19] + assign alu_3_io_req_op = decode_3_io_alu_op; // @[SCore.scala 137:19] + assign alu_3_io_rs1_valid = regfile_io_readData_6_valid; // @[SCore.scala 138:19] + assign alu_3_io_rs1_data = regfile_io_readData_6_data; // @[SCore.scala 138:19] + assign alu_3_io_rs2_valid = regfile_io_readData_7_valid; // @[SCore.scala 139:19] + assign alu_3_io_rs2_data = regfile_io_readData_7_data; // @[SCore.scala 139:19] assign bru_0_clock = clock; assign bru_0_reset = reset; - assign bru_0_io_req_valid = decode_0_io_bru_valid; // @[SCore.scala 155:19] - assign bru_0_io_req_fwd = decode_0_io_bru_fwd; // @[SCore.scala 155:19] - assign bru_0_io_req_op = decode_0_io_bru_op; // @[SCore.scala 155:19] - assign bru_0_io_req_pc = decode_0_io_bru_pc; // @[SCore.scala 155:19] - assign bru_0_io_req_target = decode_0_io_bru_target; // @[SCore.scala 155:19] - assign bru_0_io_req_link = decode_0_io_bru_link; // @[SCore.scala 155:19] - assign bru_0_io_csr_out_mode = csr_io_bru_out_mode; // @[SCore.scala 161:17] - assign bru_0_io_csr_out_mepc = csr_io_bru_out_mepc; // @[SCore.scala 161:17] - assign bru_0_io_csr_out_mtvec = csr_io_bru_out_mtvec; // @[SCore.scala 161:17] - assign bru_0_io_rs1_valid = regfile_io_readData_0_valid; // @[SCore.scala 156:19] - assign bru_0_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 156:19] - assign bru_0_io_rs2_valid = regfile_io_readData_1_valid; // @[SCore.scala 157:19] - assign bru_0_io_rs2_data = regfile_io_readData_1_data; // @[SCore.scala 157:19] - assign bru_0_io_target_data = regfile_io_target_0_data; // @[SCore.scala 158:22] + assign bru_0_io_req_valid = decode_0_io_bru_valid; // @[SCore.scala 145:19] + assign bru_0_io_req_fwd = decode_0_io_bru_fwd; // @[SCore.scala 145:19] + assign bru_0_io_req_op = decode_0_io_bru_op; // @[SCore.scala 145:19] + assign bru_0_io_req_pc = decode_0_io_bru_pc; // @[SCore.scala 145:19] + assign bru_0_io_req_target = decode_0_io_bru_target; // @[SCore.scala 145:19] + assign bru_0_io_req_link = decode_0_io_bru_link; // @[SCore.scala 145:19] + assign bru_0_io_csr_out_mode = csr_io_bru_out_mode; // @[SCore.scala 151:17] + assign bru_0_io_csr_out_mepc = csr_io_bru_out_mepc; // @[SCore.scala 151:17] + assign bru_0_io_csr_out_mtvec = csr_io_bru_out_mtvec; // @[SCore.scala 151:17] + assign bru_0_io_rs1_valid = regfile_io_readData_0_valid; // @[SCore.scala 146:19] + assign bru_0_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 146:19] + assign bru_0_io_rs2_valid = regfile_io_readData_1_valid; // @[SCore.scala 147:19] + assign bru_0_io_rs2_data = regfile_io_readData_1_data; // @[SCore.scala 147:19] + assign bru_0_io_target_data = regfile_io_target_0_data; // @[SCore.scala 148:22] assign bru_1_clock = clock; assign bru_1_reset = reset; - assign bru_1_io_req_valid = decode_1_io_bru_valid; // @[SCore.scala 155:19] - assign bru_1_io_req_fwd = decode_1_io_bru_fwd; // @[SCore.scala 155:19] - assign bru_1_io_req_op = decode_1_io_bru_op; // @[SCore.scala 155:19] - assign bru_1_io_req_pc = decode_1_io_bru_pc; // @[SCore.scala 155:19] - assign bru_1_io_req_target = decode_1_io_bru_target; // @[SCore.scala 155:19] - assign bru_1_io_req_link = decode_1_io_bru_link; // @[SCore.scala 155:19] + assign bru_1_io_req_valid = decode_1_io_bru_valid; // @[SCore.scala 145:19] + assign bru_1_io_req_fwd = decode_1_io_bru_fwd; // @[SCore.scala 145:19] + assign bru_1_io_req_op = decode_1_io_bru_op; // @[SCore.scala 145:19] + assign bru_1_io_req_pc = decode_1_io_bru_pc; // @[SCore.scala 145:19] + assign bru_1_io_req_target = decode_1_io_bru_target; // @[SCore.scala 145:19] + assign bru_1_io_req_link = decode_1_io_bru_link; // @[SCore.scala 145:19] assign bru_1_io_csr_out_mode = 1'h0; // @[Csr.scala 48:14] assign bru_1_io_csr_out_mepc = 32'h0; // @[Csr.scala 49:14] assign bru_1_io_csr_out_mtvec = 32'h0; // @[Csr.scala 50:15] - assign bru_1_io_rs1_valid = regfile_io_readData_2_valid; // @[SCore.scala 156:19] - assign bru_1_io_rs1_data = regfile_io_readData_2_data; // @[SCore.scala 156:19] - assign bru_1_io_rs2_valid = regfile_io_readData_3_valid; // @[SCore.scala 157:19] - assign bru_1_io_rs2_data = regfile_io_readData_3_data; // @[SCore.scala 157:19] - assign bru_1_io_target_data = regfile_io_target_1_data; // @[SCore.scala 158:22] + assign bru_1_io_rs1_valid = regfile_io_readData_2_valid; // @[SCore.scala 146:19] + assign bru_1_io_rs1_data = regfile_io_readData_2_data; // @[SCore.scala 146:19] + assign bru_1_io_rs2_valid = regfile_io_readData_3_valid; // @[SCore.scala 147:19] + assign bru_1_io_rs2_data = regfile_io_readData_3_data; // @[SCore.scala 147:19] + assign bru_1_io_target_data = regfile_io_target_1_data; // @[SCore.scala 148:22] assign bru_2_clock = clock; assign bru_2_reset = reset; - assign bru_2_io_req_valid = decode_2_io_bru_valid; // @[SCore.scala 155:19] - assign bru_2_io_req_fwd = decode_2_io_bru_fwd; // @[SCore.scala 155:19] - assign bru_2_io_req_op = decode_2_io_bru_op; // @[SCore.scala 155:19] - assign bru_2_io_req_pc = decode_2_io_bru_pc; // @[SCore.scala 155:19] - assign bru_2_io_req_target = decode_2_io_bru_target; // @[SCore.scala 155:19] - assign bru_2_io_req_link = decode_2_io_bru_link; // @[SCore.scala 155:19] + assign bru_2_io_req_valid = decode_2_io_bru_valid; // @[SCore.scala 145:19] + assign bru_2_io_req_fwd = decode_2_io_bru_fwd; // @[SCore.scala 145:19] + assign bru_2_io_req_op = decode_2_io_bru_op; // @[SCore.scala 145:19] + assign bru_2_io_req_pc = decode_2_io_bru_pc; // @[SCore.scala 145:19] + assign bru_2_io_req_target = decode_2_io_bru_target; // @[SCore.scala 145:19] + assign bru_2_io_req_link = decode_2_io_bru_link; // @[SCore.scala 145:19] assign bru_2_io_csr_out_mode = 1'h0; // @[Csr.scala 48:14] assign bru_2_io_csr_out_mepc = 32'h0; // @[Csr.scala 49:14] assign bru_2_io_csr_out_mtvec = 32'h0; // @[Csr.scala 50:15] - assign bru_2_io_rs1_valid = regfile_io_readData_4_valid; // @[SCore.scala 156:19] - assign bru_2_io_rs1_data = regfile_io_readData_4_data; // @[SCore.scala 156:19] - assign bru_2_io_rs2_valid = regfile_io_readData_5_valid; // @[SCore.scala 157:19] - assign bru_2_io_rs2_data = regfile_io_readData_5_data; // @[SCore.scala 157:19] - assign bru_2_io_target_data = regfile_io_target_2_data; // @[SCore.scala 158:22] + assign bru_2_io_rs1_valid = regfile_io_readData_4_valid; // @[SCore.scala 146:19] + assign bru_2_io_rs1_data = regfile_io_readData_4_data; // @[SCore.scala 146:19] + assign bru_2_io_rs2_valid = regfile_io_readData_5_valid; // @[SCore.scala 147:19] + assign bru_2_io_rs2_data = regfile_io_readData_5_data; // @[SCore.scala 147:19] + assign bru_2_io_target_data = regfile_io_target_2_data; // @[SCore.scala 148:22] assign bru_3_clock = clock; assign bru_3_reset = reset; - assign bru_3_io_req_valid = decode_3_io_bru_valid; // @[SCore.scala 155:19] - assign bru_3_io_req_fwd = decode_3_io_bru_fwd; // @[SCore.scala 155:19] - assign bru_3_io_req_op = decode_3_io_bru_op; // @[SCore.scala 155:19] - assign bru_3_io_req_pc = decode_3_io_bru_pc; // @[SCore.scala 155:19] - assign bru_3_io_req_target = decode_3_io_bru_target; // @[SCore.scala 155:19] - assign bru_3_io_req_link = decode_3_io_bru_link; // @[SCore.scala 155:19] + assign bru_3_io_req_valid = decode_3_io_bru_valid; // @[SCore.scala 145:19] + assign bru_3_io_req_fwd = decode_3_io_bru_fwd; // @[SCore.scala 145:19] + assign bru_3_io_req_op = decode_3_io_bru_op; // @[SCore.scala 145:19] + assign bru_3_io_req_pc = decode_3_io_bru_pc; // @[SCore.scala 145:19] + assign bru_3_io_req_target = decode_3_io_bru_target; // @[SCore.scala 145:19] + assign bru_3_io_req_link = decode_3_io_bru_link; // @[SCore.scala 145:19] assign bru_3_io_csr_out_mode = 1'h0; // @[Csr.scala 48:14] assign bru_3_io_csr_out_mepc = 32'h0; // @[Csr.scala 49:14] assign bru_3_io_csr_out_mtvec = 32'h0; // @[Csr.scala 50:15] - assign bru_3_io_rs1_valid = regfile_io_readData_6_valid; // @[SCore.scala 156:19] - assign bru_3_io_rs1_data = regfile_io_readData_6_data; // @[SCore.scala 156:19] - assign bru_3_io_rs2_valid = regfile_io_readData_7_valid; // @[SCore.scala 157:19] - assign bru_3_io_rs2_data = regfile_io_readData_7_data; // @[SCore.scala 157:19] - assign bru_3_io_target_data = regfile_io_target_3_data; // @[SCore.scala 158:22] + assign bru_3_io_rs1_valid = regfile_io_readData_6_valid; // @[SCore.scala 146:19] + assign bru_3_io_rs1_data = regfile_io_readData_6_data; // @[SCore.scala 146:19] + assign bru_3_io_rs2_valid = regfile_io_readData_7_valid; // @[SCore.scala 147:19] + assign bru_3_io_rs2_data = regfile_io_readData_7_data; // @[SCore.scala 147:19] + assign bru_3_io_target_data = regfile_io_target_3_data; // @[SCore.scala 148:22] assign csr_clock = clock; assign csr_reset = reset; - assign csr_io_csr_in_value_0 = io_csr_in_value_0; // @[SCore.scala 170:14] - assign csr_io_req_valid = decode_0_io_csr_valid; // @[SCore.scala 172:14] - assign csr_io_req_addr = decode_0_io_csr_addr; // @[SCore.scala 172:14] - assign csr_io_req_index = decode_0_io_csr_index; // @[SCore.scala 172:14] - assign csr_io_req_op = decode_0_io_csr_op; // @[SCore.scala 172:14] - assign csr_io_rs1_valid = regfile_io_readData_0_valid; // @[SCore.scala 173:14] - assign csr_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 173:14] - assign csr_io_bru_in_mode_valid = bru_0_io_csr_in_mode_valid; // @[SCore.scala 161:17] - assign csr_io_bru_in_mode_bits = bru_0_io_csr_in_mode_bits; // @[SCore.scala 161:17] - assign csr_io_bru_in_mcause_valid = bru_0_io_csr_in_mcause_valid; // @[SCore.scala 161:17] - assign csr_io_bru_in_mcause_bits = bru_0_io_csr_in_mcause_bits; // @[SCore.scala 161:17] - assign csr_io_bru_in_mepc_valid = bru_0_io_csr_in_mepc_valid; // @[SCore.scala 161:17] - assign csr_io_bru_in_mepc_bits = bru_0_io_csr_in_mepc_bits; // @[SCore.scala 161:17] - assign csr_io_bru_in_mtval_valid = bru_0_io_csr_in_mtval_valid; // @[SCore.scala 161:17] - assign csr_io_bru_in_mtval_bits = bru_0_io_csr_in_mtval_bits; // @[SCore.scala 161:17] - assign csr_io_bru_in_halt = bru_0_io_csr_in_halt; // @[SCore.scala 161:17] - assign csr_io_bru_in_fault = bru_0_io_csr_in_fault; // @[SCore.scala 161:17] - assign csr_io_vcore_undef = io_vcore_undef; // @[SCore.scala 175:22] + assign csr_io_csr_in_value_0 = io_csr_in_value_0; // @[SCore.scala 160:14] + assign csr_io_req_valid = decode_0_io_csr_valid; // @[SCore.scala 162:14] + assign csr_io_req_addr = decode_0_io_csr_addr; // @[SCore.scala 162:14] + assign csr_io_req_index = decode_0_io_csr_index; // @[SCore.scala 162:14] + assign csr_io_req_op = decode_0_io_csr_op; // @[SCore.scala 162:14] + assign csr_io_rs1_valid = regfile_io_readData_0_valid; // @[SCore.scala 163:14] + assign csr_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 163:14] + assign csr_io_bru_in_mode_valid = bru_0_io_csr_in_mode_valid; // @[SCore.scala 151:17] + assign csr_io_bru_in_mode_bits = bru_0_io_csr_in_mode_bits; // @[SCore.scala 151:17] + assign csr_io_bru_in_mcause_valid = bru_0_io_csr_in_mcause_valid; // @[SCore.scala 151:17] + assign csr_io_bru_in_mcause_bits = bru_0_io_csr_in_mcause_bits; // @[SCore.scala 151:17] + assign csr_io_bru_in_mepc_valid = bru_0_io_csr_in_mepc_valid; // @[SCore.scala 151:17] + assign csr_io_bru_in_mepc_bits = bru_0_io_csr_in_mepc_bits; // @[SCore.scala 151:17] + assign csr_io_bru_in_mtval_valid = bru_0_io_csr_in_mtval_valid; // @[SCore.scala 151:17] + assign csr_io_bru_in_mtval_bits = bru_0_io_csr_in_mtval_bits; // @[SCore.scala 151:17] + assign csr_io_bru_in_halt = bru_0_io_csr_in_halt; // @[SCore.scala 151:17] + assign csr_io_bru_in_fault = bru_0_io_csr_in_fault; // @[SCore.scala 151:17] + assign csr_io_vcore_undef = io_vcore_undef; // @[SCore.scala 165:22] assign lsu_clock = clock; assign lsu_reset = reset; - assign lsu_io_req_0_valid = decode_0_io_lsu_valid; // @[SCore.scala 187:25] - assign lsu_io_req_0_addr = decode_0_io_lsu_addr; // @[SCore.scala 189:25] - assign lsu_io_req_0_op = decode_0_io_lsu_op; // @[SCore.scala 190:25] - assign lsu_io_req_1_valid = decode_1_io_lsu_valid; // @[SCore.scala 187:25] - assign lsu_io_req_1_addr = decode_1_io_lsu_addr; // @[SCore.scala 189:25] - assign lsu_io_req_1_op = decode_1_io_lsu_op; // @[SCore.scala 190:25] - assign lsu_io_req_2_valid = decode_2_io_lsu_valid; // @[SCore.scala 187:25] - assign lsu_io_req_2_addr = decode_2_io_lsu_addr; // @[SCore.scala 189:25] - assign lsu_io_req_2_op = decode_2_io_lsu_op; // @[SCore.scala 190:25] - assign lsu_io_req_3_valid = decode_3_io_lsu_valid; // @[SCore.scala 187:25] - assign lsu_io_req_3_addr = decode_3_io_lsu_addr; // @[SCore.scala 189:25] - assign lsu_io_req_3_op = decode_3_io_lsu_op; // @[SCore.scala 190:25] - assign lsu_io_busPort_addr_0 = regfile_io_busPort_addr_0; // @[SCore.scala 184:18] - assign lsu_io_busPort_addr_1 = regfile_io_busPort_addr_1; // @[SCore.scala 184:18] - assign lsu_io_busPort_addr_2 = regfile_io_busPort_addr_2; // @[SCore.scala 184:18] - assign lsu_io_busPort_addr_3 = regfile_io_busPort_addr_3; // @[SCore.scala 184:18] - assign lsu_io_busPort_data_0 = regfile_io_busPort_data_0; // @[SCore.scala 184:18] - assign lsu_io_busPort_data_1 = regfile_io_busPort_data_1; // @[SCore.scala 184:18] - assign lsu_io_busPort_data_2 = regfile_io_busPort_data_2; // @[SCore.scala 184:18] - assign lsu_io_busPort_data_3 = regfile_io_busPort_data_3; // @[SCore.scala 184:18] - assign lsu_io_dbus_ready = io_dbus_ready; // @[SCore.scala 295:11] - assign lsu_io_dbus_rdata = io_dbus_rdata; // @[SCore.scala 295:11] + assign lsu_io_req_0_valid = decode_0_io_lsu_valid; // @[SCore.scala 177:25] + assign lsu_io_req_0_addr = decode_0_io_lsu_addr; // @[SCore.scala 179:25] + assign lsu_io_req_0_op = decode_0_io_lsu_op; // @[SCore.scala 180:25] + assign lsu_io_req_1_valid = decode_1_io_lsu_valid; // @[SCore.scala 177:25] + assign lsu_io_req_1_addr = decode_1_io_lsu_addr; // @[SCore.scala 179:25] + assign lsu_io_req_1_op = decode_1_io_lsu_op; // @[SCore.scala 180:25] + assign lsu_io_req_2_valid = decode_2_io_lsu_valid; // @[SCore.scala 177:25] + assign lsu_io_req_2_addr = decode_2_io_lsu_addr; // @[SCore.scala 179:25] + assign lsu_io_req_2_op = decode_2_io_lsu_op; // @[SCore.scala 180:25] + assign lsu_io_req_3_valid = decode_3_io_lsu_valid; // @[SCore.scala 177:25] + assign lsu_io_req_3_addr = decode_3_io_lsu_addr; // @[SCore.scala 179:25] + assign lsu_io_req_3_op = decode_3_io_lsu_op; // @[SCore.scala 180:25] + assign lsu_io_busPort_addr_0 = regfile_io_busPort_addr_0; // @[SCore.scala 174:18] + assign lsu_io_busPort_addr_1 = regfile_io_busPort_addr_1; // @[SCore.scala 174:18] + assign lsu_io_busPort_addr_2 = regfile_io_busPort_addr_2; // @[SCore.scala 174:18] + assign lsu_io_busPort_addr_3 = regfile_io_busPort_addr_3; // @[SCore.scala 174:18] + assign lsu_io_busPort_data_0 = regfile_io_busPort_data_0; // @[SCore.scala 174:18] + assign lsu_io_busPort_data_1 = regfile_io_busPort_data_1; // @[SCore.scala 174:18] + assign lsu_io_busPort_data_2 = regfile_io_busPort_data_2; // @[SCore.scala 174:18] + assign lsu_io_busPort_data_3 = regfile_io_busPort_data_3; // @[SCore.scala 174:18] + assign lsu_io_dbus_ready = io_dbus_ready; // @[SCore.scala 285:11] + assign lsu_io_dbus_rdata = io_dbus_rdata; // @[SCore.scala 285:11] assign lsu_io_flush_ready = io_dflush_ready; // @[SCore.scala 62:22] - assign lsu_io_ubus_ready = io_ubus_ready; // @[SCore.scala 296:11] - assign lsu_io_ubus_rdata = io_ubus_rdata; // @[SCore.scala 296:11] + assign lsu_io_ubus_ready = io_ubus_ready; // @[SCore.scala 286:11] + assign lsu_io_ubus_rdata = io_ubus_rdata; // @[SCore.scala 286:11] assign mlu_clock = clock; assign mlu_reset = reset; - assign mlu_io_req_0_valid = decode_0_io_mlu_valid; // @[SCore.scala 196:17] - assign mlu_io_req_0_addr = decode_0_io_mlu_addr; // @[SCore.scala 196:17] - assign mlu_io_req_0_op = decode_0_io_mlu_op; // @[SCore.scala 196:17] - assign mlu_io_req_1_valid = decode_1_io_mlu_valid; // @[SCore.scala 197:17] - assign mlu_io_req_1_addr = decode_1_io_mlu_addr; // @[SCore.scala 197:17] - assign mlu_io_req_1_op = decode_1_io_mlu_op; // @[SCore.scala 197:17] - assign mlu_io_req_2_valid = decode_2_io_mlu_valid; // @[SCore.scala 198:17] - assign mlu_io_req_2_addr = decode_2_io_mlu_addr; // @[SCore.scala 198:17] - assign mlu_io_req_2_op = decode_2_io_mlu_op; // @[SCore.scala 198:17] - assign mlu_io_req_3_valid = decode_3_io_mlu_valid; // @[SCore.scala 199:17] - assign mlu_io_req_3_addr = decode_3_io_mlu_addr; // @[SCore.scala 199:17] - assign mlu_io_req_3_op = decode_3_io_mlu_op; // @[SCore.scala 199:17] - assign mlu_io_rs1_0_valid = regfile_io_readData_0_valid; // @[SCore.scala 200:17] - assign mlu_io_rs1_0_data = regfile_io_readData_0_data; // @[SCore.scala 200:17] - assign mlu_io_rs1_1_valid = regfile_io_readData_2_valid; // @[SCore.scala 201:17] - assign mlu_io_rs1_1_data = regfile_io_readData_2_data; // @[SCore.scala 201:17] - assign mlu_io_rs1_2_valid = regfile_io_readData_4_valid; // @[SCore.scala 202:17] - assign mlu_io_rs1_2_data = regfile_io_readData_4_data; // @[SCore.scala 202:17] - assign mlu_io_rs1_3_valid = regfile_io_readData_6_valid; // @[SCore.scala 203:17] - assign mlu_io_rs1_3_data = regfile_io_readData_6_data; // @[SCore.scala 203:17] - assign mlu_io_rs2_0_valid = regfile_io_readData_1_valid; // @[SCore.scala 204:17] - assign mlu_io_rs2_0_data = regfile_io_readData_1_data; // @[SCore.scala 204:17] - assign mlu_io_rs2_1_valid = regfile_io_readData_3_valid; // @[SCore.scala 205:17] - assign mlu_io_rs2_1_data = regfile_io_readData_3_data; // @[SCore.scala 205:17] - assign mlu_io_rs2_2_valid = regfile_io_readData_5_valid; // @[SCore.scala 206:17] - assign mlu_io_rs2_2_data = regfile_io_readData_5_data; // @[SCore.scala 206:17] - assign mlu_io_rs2_3_valid = regfile_io_readData_7_valid; // @[SCore.scala 207:17] - assign mlu_io_rs2_3_data = regfile_io_readData_7_data; // @[SCore.scala 207:17] + assign mlu_io_req_0_valid = decode_0_io_mlu_valid; // @[SCore.scala 186:17] + assign mlu_io_req_0_addr = decode_0_io_mlu_addr; // @[SCore.scala 186:17] + assign mlu_io_req_0_op = decode_0_io_mlu_op; // @[SCore.scala 186:17] + assign mlu_io_req_1_valid = decode_1_io_mlu_valid; // @[SCore.scala 187:17] + assign mlu_io_req_1_addr = decode_1_io_mlu_addr; // @[SCore.scala 187:17] + assign mlu_io_req_1_op = decode_1_io_mlu_op; // @[SCore.scala 187:17] + assign mlu_io_req_2_valid = decode_2_io_mlu_valid; // @[SCore.scala 188:17] + assign mlu_io_req_2_addr = decode_2_io_mlu_addr; // @[SCore.scala 188:17] + assign mlu_io_req_2_op = decode_2_io_mlu_op; // @[SCore.scala 188:17] + assign mlu_io_req_3_valid = decode_3_io_mlu_valid; // @[SCore.scala 189:17] + assign mlu_io_req_3_addr = decode_3_io_mlu_addr; // @[SCore.scala 189:17] + assign mlu_io_req_3_op = decode_3_io_mlu_op; // @[SCore.scala 189:17] + assign mlu_io_rs1_0_valid = regfile_io_readData_0_valid; // @[SCore.scala 190:17] + assign mlu_io_rs1_0_data = regfile_io_readData_0_data; // @[SCore.scala 190:17] + assign mlu_io_rs1_1_valid = regfile_io_readData_2_valid; // @[SCore.scala 191:17] + assign mlu_io_rs1_1_data = regfile_io_readData_2_data; // @[SCore.scala 191:17] + assign mlu_io_rs1_2_valid = regfile_io_readData_4_valid; // @[SCore.scala 192:17] + assign mlu_io_rs1_2_data = regfile_io_readData_4_data; // @[SCore.scala 192:17] + assign mlu_io_rs1_3_valid = regfile_io_readData_6_valid; // @[SCore.scala 193:17] + assign mlu_io_rs1_3_data = regfile_io_readData_6_data; // @[SCore.scala 193:17] + assign mlu_io_rs2_0_valid = regfile_io_readData_1_valid; // @[SCore.scala 194:17] + assign mlu_io_rs2_0_data = regfile_io_readData_1_data; // @[SCore.scala 194:17] + assign mlu_io_rs2_1_valid = regfile_io_readData_3_valid; // @[SCore.scala 195:17] + assign mlu_io_rs2_1_data = regfile_io_readData_3_data; // @[SCore.scala 195:17] + assign mlu_io_rs2_2_valid = regfile_io_readData_5_valid; // @[SCore.scala 196:17] + assign mlu_io_rs2_2_data = regfile_io_readData_5_data; // @[SCore.scala 196:17] + assign mlu_io_rs2_3_valid = regfile_io_readData_7_valid; // @[SCore.scala 197:17] + assign mlu_io_rs2_3_data = regfile_io_readData_7_data; // @[SCore.scala 197:17] assign dvu_clock = clock; assign dvu_reset = reset; - assign dvu_io_req_valid = decode_0_io_dvu_valid; // @[SCore.scala 215:14] - assign dvu_io_req_addr = decode_0_io_dvu_addr; // @[SCore.scala 215:14] - assign dvu_io_req_op = decode_0_io_dvu_op; // @[SCore.scala 215:14] - assign dvu_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 216:14] - assign dvu_io_rs2_data = regfile_io_readData_1_data; // @[SCore.scala 217:14] - assign dvu_io_rd_ready = ~mlu_io_rd_valid; // @[SCore.scala 218:22] + assign dvu_io_req_valid = decode_0_io_dvu_valid; // @[SCore.scala 205:14] + assign dvu_io_req_addr = decode_0_io_dvu_addr; // @[SCore.scala 205:14] + assign dvu_io_req_op = decode_0_io_dvu_op; // @[SCore.scala 205:14] + assign dvu_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 206:14] + assign dvu_io_rs2_data = regfile_io_readData_1_data; // @[SCore.scala 207:14] + assign dvu_io_rd_ready = ~mlu_io_rd_valid; // @[SCore.scala 208:22] always @(posedge clock) begin slogAddr <= _GEN_2[1:0]; `ifndef SYNTHESIS @@ -23080,7 +23080,7 @@ if (`STOP_COND) begin `endif if (_T_5 & ~_T_18) begin - $fatal; // @[SCore.scala 256:11] + $fatal; // @[SCore.scala 246:11] end `ifdef STOP_COND end @@ -23091,7 +23091,7 @@ if (`PRINTF_COND) begin `endif if (_T_5 & ~_T_18) begin - $fwrite(32'h80000002,"Assertion failed\n at SCore.scala:256 assert((csr0Valid +&\n"); // @[SCore.scala 256:11] + $fwrite(32'h80000002,"Assertion failed\n at SCore.scala:246 assert((csr0Valid +&\n"); // @[SCore.scala 246:11] end `ifdef PRINTF_COND end @@ -23102,7 +23102,7 @@ if (`STOP_COND) begin `endif if (_T_5 & ~_T_25) begin - $fatal; // @[SCore.scala 256:11] + $fatal; // @[SCore.scala 246:11] end `ifdef STOP_COND end @@ -23113,7 +23113,7 @@ if (`PRINTF_COND) begin `endif if (_T_5 & ~_T_25) begin - $fwrite(32'h80000002,"Assertion failed\n at SCore.scala:256 assert((csr0Valid +&\n"); // @[SCore.scala 256:11] + $fwrite(32'h80000002,"Assertion failed\n at SCore.scala:246 assert((csr0Valid +&\n"); // @[SCore.scala 246:11] end `ifdef PRINTF_COND end @@ -23124,7 +23124,7 @@ if (`STOP_COND) begin `endif if (_T_5 & ~_T_32) begin - $fatal; // @[SCore.scala 256:11] + $fatal; // @[SCore.scala 246:11] end `ifdef STOP_COND end @@ -23135,7 +23135,7 @@ if (`PRINTF_COND) begin `endif if (_T_5 & ~_T_32) begin - $fwrite(32'h80000002,"Assertion failed\n at SCore.scala:256 assert((csr0Valid +&\n"); // @[SCore.scala 256:11] + $fwrite(32'h80000002,"Assertion failed\n at SCore.scala:246 assert((csr0Valid +&\n"); // @[SCore.scala 246:11] end `ifdef PRINTF_COND end @@ -23146,7 +23146,7 @@ if (`STOP_COND) begin `endif if (_T_5 & ~_T_39) begin - $fatal; // @[SCore.scala 256:11] + $fatal; // @[SCore.scala 246:11] end `ifdef STOP_COND end @@ -23157,7 +23157,7 @@ if (`PRINTF_COND) begin `endif if (_T_5 & ~_T_39) begin - $fwrite(32'h80000002,"Assertion failed\n at SCore.scala:256 assert((csr0Valid +&\n"); // @[SCore.scala 256:11] + $fwrite(32'h80000002,"Assertion failed\n at SCore.scala:246 assert((csr0Valid +&\n"); // @[SCore.scala 246:11] end `ifdef PRINTF_COND end @@ -23168,7 +23168,7 @@ if (`STOP_COND) begin `endif if (_T_5 & ~(~(mlu_io_rd_valid & (dvu_io_rd_valid & dvu_io_rd_ready)))) begin - $fatal; // @[SCore.scala 264:9] + $fatal; // @[SCore.scala 254:9] end `ifdef STOP_COND end @@ -23180,8 +23180,8 @@ `endif if (_T_5 & ~(~(mlu_io_rd_valid & (dvu_io_rd_valid & dvu_io_rd_ready)))) begin $fwrite(32'h80000002, - "Assertion failed\n at SCore.scala:264 assert(!(mlu.io.rd.valid && (dvu.io.rd.valid && dvu.io.rd.ready))) // TODO: stall dvu on mlu write\n" - ); // @[SCore.scala 264:9] + "Assertion failed\n at SCore.scala:254 assert(!(mlu.io.rd.valid && (dvu.io.rd.valid && dvu.io.rd.ready))) // TODO: stall dvu on mlu write\n" + ); // @[SCore.scala 254:9] end `ifdef PRINTF_COND end @@ -23203,10 +23203,10 @@ end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[SCore.scala 302:26] - slogValid <= 1'h0; // @[SCore.scala 302:26] + if (reset) begin // @[SCore.scala 292:26] + slogValid <= 1'h0; // @[SCore.scala 292:26] end else begin - slogValid <= decode_0_io_slog; // @[SCore.scala 306:13] + slogValid <= decode_0_io_slog; // @[SCore.scala 296:13] end end // Register and memory initialization