sw/device/tests/smc/smc_tlul_mailbox_test.c

/*
 * Copyright 2023 Google LLC
 * Copyright lowRISC contributors
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */


#include "hw/top_matcha/sw/autogen/top_matcha.h"
#include "sw/device/lib/arch/device.h"
#include "sw/device/lib/dif/dif_rv_plic.h"
#include "sw/device/lib/dif/dif_smc_ctrl.h"
#include "sw/device/lib/dif/dif_tlul_mailbox.h"
#include "sw/device/lib/runtime/hart.h"
#include "sw/device/lib/runtime/log.h"
#include "sw/device/lib/runtime/print.h"
#include "sw/device/lib/testing/test_framework/check.h"
#include "sw/device/lib/testing/test_framework/ottf_test_config.h"
#include "sw/device/lib/testing/test_framework/test_util.h"

OTTF_DEFINE_TEST_CONFIG();

static dif_uart_t smc_uart;
static dif_tlul_mailbox_t tlul_mailbox;
static dif_rv_plic_t plic_smc;

void ottf_external_isr(void) {
  LOG_INFO("SMC woken!");

  uint32_t tx, rx;
  dif_rv_plic_irq_id_t plic_irq_id;

  // Clear IRQ from the tlul_mailbox and claim it from the PLIC.
  CHECK_DIF_OK(
      dif_tlul_mailbox_irq_acknowledge(&tlul_mailbox, kDifTlulMailboxIrqRtirq));
  CHECK_DIF_OK(dif_rv_plic_irq_claim(&plic_smc, kTopMatchaPlicTargetIbex0Smc,
                                     &plic_irq_id));

  // Read messages and send a reply to the secure core.
  CHECK_DIF_OK(dif_tlul_mailbox_read_message(&tlul_mailbox, &rx));
  CHECK(
      rx == 0xCAFEB0BA,
      "Message from secure core incorrect - expected: 0xcafeb0ba | actual: %x",
      rx);

  CHECK_DIF_OK(dif_tlul_mailbox_read_message(&tlul_mailbox, &rx));
  CHECK(
      rx == 0xDEADBEEF,
      "Message from secure core incorrect - expected: 0xdeadbeef | actual: %x",
      rx);

  tx = 0xBEEFB0BA;
  CHECK_DIF_OK(dif_tlul_mailbox_send_message(&tlul_mailbox, &tx));

  CHECK_DIF_OK(dif_rv_plic_irq_complete(&plic_smc, kTopMatchaPlicTargetIbex0Smc,
                                        plic_irq_id));
}

void _ottf_main(void) {
  // Initialize the SMC UART to enable logging for non-DV simulation platforms.
  if (kDeviceType != kDeviceSimDV) {
    init_uart(TOP_MATCHA_SMC_UART_BASE_ADDR, &smc_uart);
  }

  LOG_INFO("Hello from the SMC!");
  CHECK_DIF_OK(dif_tlul_mailbox_init(
                   mmio_region_from_addr(TOP_MATCHA_TLUL_MAILBOX_SMC_BASE_ADDR),
                   &tlul_mailbox),
               "Enabling tlul_mailbox interrupts failed");
  CHECK_DIF_OK(dif_tlul_mailbox_irq_set_enabled(
      &tlul_mailbox, kDifTlulMailboxIrqRtirq, kDifToggleEnabled));
  CHECK_DIF_OK(dif_tlul_mailbox_irq_set_enabled(
      &tlul_mailbox, kDifTlulMailboxIrqWtirq, kDifToggleEnabled));
  CHECK_DIF_OK(dif_tlul_mailbox_irq_set_enabled(
      &tlul_mailbox, kDifTlulMailboxIrqEirq, kDifToggleEnabled));

  CHECK_DIF_OK(dif_rv_plic_init(
      mmio_region_from_addr(TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR), &plic_smc));

  // Set the PLIC priority and interrupt enable only, as threshold is default 0.
  // Since this is the SMC PLIC, the only target is the SMC.
  CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
      &plic_smc, kTopMatchaPlicIrqIdTlulMailboxSmcRtirq,
      kTopMatchaPlicTargetIbex0Smc, kDifToggleEnabled));
  CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
      &plic_smc, kTopMatchaPlicIrqIdTlulMailboxSmcRtirq, 1));

  // Enable M-mode external interrupts.
  asm volatile("csrs mstatus, %0\n" : : "r"(0x8));
  asm volatile("csrs mie, %0\n" : : "r"(0x800));

  asm volatile("wfi");
  // ISR returns to next instruction.
  asm volatile("wfi");
}