sw/device/tests/smc/smc_rv_timer_test.c

/*
 * Copyright 2023 Google LLC
 * Copyright lowRISC contributors
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#include <stdbool.h>

#include "hw/top_matcha/sw/autogen/top_matcha.h"
#include "sw/device/lib/arch/device.h"
#include "sw/device/lib/dif/dif_rv_plic.h"
#include "sw/device/lib/dif/dif_rv_timer.h"
#include "sw/device/lib/runtime/hart.h"
#include "sw/device/lib/runtime/irq.h"
#include "sw/device/lib/runtime/log.h"
#include "sw/device/lib/runtime/print.h"
#include "sw/device/lib/testing/test_framework/check.h"
#include "sw/device/lib/testing/test_framework/ottf_test_config.h"
#include "sw/device/lib/testing/test_framework/test_util.h"

static dif_rv_timer_t rv_timer;
static dif_rv_timer_t rv_timer2;
static dif_rv_plic_t plic_smc;
static dif_uart_t smc_uart;
static volatile bool timer_isr_seen = false;
static volatile bool timer2_isr_seen = false;

OTTF_DEFINE_TEST_CONFIG();

void ottf_timer_isr(void) {
  CHECK(!timer_isr_seen);
  timer_isr_seen = true;
  CHECK_DIF_OK(
      dif_rv_timer_counter_set_enabled(&rv_timer, 0, kDifToggleDisabled));
  CHECK_DIF_OK(dif_rv_timer_irq_acknowledge(
      &rv_timer, kDifRvTimerIrqTimerExpiredHart0Timer0));
}

void ottf_external_isr(void) {
  dif_rv_plic_irq_id_t interrupt_id;
  CHECK_DIF_OK(dif_rv_plic_irq_claim(&plic_smc, kTopMatchaPlicTargetIbex0Smc,
                                     &interrupt_id));

  top_matcha_plic_peripheral_smc_t peripheral_id =
      top_matcha_plic_interrupt_for_peripheral_smc[interrupt_id];
  CHECK(peripheral_id == kTopMatchaPlicPeripheralRvTimerSmc2,
        "External IRQ not from RV_TIMER_SMC2");

  CHECK(!timer2_isr_seen);
  timer2_isr_seen = true;

  CHECK_DIF_OK(
      dif_rv_timer_counter_set_enabled(&rv_timer2, 0, kDifToggleDisabled));
  CHECK_DIF_OK(dif_rv_timer_irq_acknowledge(
      &rv_timer2, kDifRvTimerIrqTimerExpiredHart0Timer0));

  CHECK_DIF_OK(dif_rv_plic_irq_complete(&plic_smc, kTopMatchaPlicTargetIbex0Smc,
                                        interrupt_id));
}

void _ottf_main(void) {
  // Initialize the SMC UART to enable logging for non-DV simulation platforms.
  if (kDeviceType != kDeviceSimDV) {
    init_uart(TOP_MATCHA_SMC_UART_BASE_ADDR, &smc_uart);
  }

  CHECK_DIF_OK(dif_rv_plic_init(
      mmio_region_from_addr(TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR), &plic_smc));
  CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
      &plic_smc, kTopMatchaPlicIrqIdRvTimerSmc2TimerExpiredHart0Timer0,
      kDifRvPlicMaxPriority));
  CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
      &plic_smc, kTopMatchaPlicIrqIdRvTimerSmc2TimerExpiredHart0Timer0,
      kTopMatchaPlicTargetIbex0Smc, kDifToggleEnabled));

  test_status_set(kTestStatusInTest);
  irq_timer_ctrl(true);
  irq_external_ctrl(true);
  irq_global_ctrl(true);

  uint64_t counter_start, counter_end;
  dif_rv_timer_tick_params_t tick_params;
  CHECK_DIF_OK(dif_rv_timer_approximate_tick_params(kClockFreqPeripheralHz,
                                                    1000000, &tick_params));

  LOG_INFO("Test RV_TIMER_SMC");
  CHECK_DIF_OK(dif_rv_timer_init(
      mmio_region_from_addr(TOP_MATCHA_RV_TIMER_SMC_BASE_ADDR), &rv_timer));
  CHECK_DIF_OK(dif_rv_timer_set_tick_params(&rv_timer, 0, tick_params));
  CHECK_DIF_OK(dif_rv_timer_irq_set_enabled(
      &rv_timer, kDifRvTimerIrqTimerExpiredHart0Timer0, kDifToggleEnabled));

  CHECK_DIF_OK(dif_rv_timer_counter_read(&rv_timer, 0, &counter_start));
  CHECK_DIF_OK(dif_rv_timer_arm(&rv_timer, 0, 0, counter_start + 1000));
  CHECK_DIF_OK(
      dif_rv_timer_counter_set_enabled(&rv_timer, 0, kDifToggleEnabled));
  while (true) {
    wait_for_interrupt();
    if (timer_isr_seen) {
      break;
    }
  }
  CHECK_DIF_OK(dif_rv_timer_counter_read(&rv_timer, 0, &counter_end));
  CHECK(counter_end - counter_start >= 1000);
  CHECK(counter_end - counter_start < 2000);

  LOG_INFO("Test RV_TIMER_SMC2");
  CHECK_DIF_OK(dif_rv_timer_init(
      mmio_region_from_addr(TOP_MATCHA_RV_TIMER_SMC2_BASE_ADDR), &rv_timer2));
  CHECK_DIF_OK(dif_rv_timer_set_tick_params(&rv_timer2, 0, tick_params));
  CHECK_DIF_OK(dif_rv_timer_irq_set_enabled(
      &rv_timer2, kDifRvTimerIrqTimerExpiredHart0Timer0, kDifToggleEnabled));

  CHECK_DIF_OK(dif_rv_timer_counter_read(&rv_timer2, 0, &counter_start));
  CHECK_DIF_OK(dif_rv_timer_arm(&rv_timer2, 0, 0, counter_start + 1000));
  CHECK_DIF_OK(
      dif_rv_timer_counter_set_enabled(&rv_timer2, 0, kDifToggleEnabled));
  while (true) {
    wait_for_interrupt();
    if (timer2_isr_seen) {
      break;
    }
  }
  CHECK_DIF_OK(dif_rv_timer_counter_read(&rv_timer2, 0, &counter_end));
  // This check allows a slightly longer duration than the above --
  // the ISR handler for external vs core timer takes a little longer.
  CHECK(counter_end - counter_start >= 1000);
  CHECK(counter_end - counter_start < 3000);

  test_status_set(kTestStatusPassed);

  __builtin_unreachable();
}